tegra20.dtsi 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211
  1. /include/ "skeleton.dtsi"
  2. / {
  3. compatible = "nvidia,tegra20";
  4. interrupt-parent = <&intc>;
  5. pmc@7000f400 {
  6. compatible = "nvidia,tegra20-pmc";
  7. reg = <0x7000e400 0x400>;
  8. };
  9. intc: interrupt-controller@50041000 {
  10. compatible = "arm,cortex-a9-gic";
  11. interrupt-controller;
  12. #interrupt-cells = <3>;
  13. reg = < 0x50041000 0x1000 >,
  14. < 0x50040100 0x0100 >;
  15. };
  16. pmu {
  17. compatible = "arm,cortex-a9-pmu";
  18. interrupts = <0 56 0x04
  19. 0 57 0x04>;
  20. };
  21. apbdma: dma@6000a000 {
  22. compatible = "nvidia,tegra20-apbdma";
  23. reg = <0x6000a000 0x1200>;
  24. interrupts = < 0 104 0x04
  25. 0 105 0x04
  26. 0 106 0x04
  27. 0 107 0x04
  28. 0 108 0x04
  29. 0 109 0x04
  30. 0 110 0x04
  31. 0 111 0x04
  32. 0 112 0x04
  33. 0 113 0x04
  34. 0 114 0x04
  35. 0 115 0x04
  36. 0 116 0x04
  37. 0 117 0x04
  38. 0 118 0x04
  39. 0 119 0x04 >;
  40. };
  41. i2c@7000c000 {
  42. #address-cells = <1>;
  43. #size-cells = <0>;
  44. compatible = "nvidia,tegra20-i2c";
  45. reg = <0x7000C000 0x100>;
  46. interrupts = < 0 38 0x04 >;
  47. };
  48. i2c@7000c400 {
  49. #address-cells = <1>;
  50. #size-cells = <0>;
  51. compatible = "nvidia,tegra20-i2c";
  52. reg = <0x7000C400 0x100>;
  53. interrupts = < 0 84 0x04 >;
  54. };
  55. i2c@7000c500 {
  56. #address-cells = <1>;
  57. #size-cells = <0>;
  58. compatible = "nvidia,tegra20-i2c";
  59. reg = <0x7000C500 0x100>;
  60. interrupts = < 0 92 0x04 >;
  61. };
  62. i2c@7000d000 {
  63. #address-cells = <1>;
  64. #size-cells = <0>;
  65. compatible = "nvidia,tegra20-i2c-dvc";
  66. reg = <0x7000D000 0x200>;
  67. interrupts = < 0 53 0x04 >;
  68. };
  69. tegra_i2s1: i2s@70002800 {
  70. compatible = "nvidia,tegra20-i2s";
  71. reg = <0x70002800 0x200>;
  72. interrupts = < 0 13 0x04 >;
  73. nvidia,dma-request-selector = < &apbdma 2 >;
  74. };
  75. tegra_i2s2: i2s@70002a00 {
  76. compatible = "nvidia,tegra20-i2s";
  77. reg = <0x70002a00 0x200>;
  78. interrupts = < 0 3 0x04 >;
  79. nvidia,dma-request-selector = < &apbdma 1 >;
  80. };
  81. das@70000c00 {
  82. compatible = "nvidia,tegra20-das";
  83. reg = <0x70000c00 0x80>;
  84. };
  85. gpio: gpio@6000d000 {
  86. compatible = "nvidia,tegra20-gpio";
  87. reg = < 0x6000d000 0x1000 >;
  88. interrupts = < 0 32 0x04
  89. 0 33 0x04
  90. 0 34 0x04
  91. 0 35 0x04
  92. 0 55 0x04
  93. 0 87 0x04
  94. 0 89 0x04 >;
  95. #gpio-cells = <2>;
  96. gpio-controller;
  97. #interrupt-cells = <2>;
  98. interrupt-controller;
  99. };
  100. pinmux: pinmux@70000000 {
  101. compatible = "nvidia,tegra20-pinmux";
  102. reg = < 0x70000014 0x10 /* Tri-state registers */
  103. 0x70000080 0x20 /* Mux registers */
  104. 0x700000a0 0x14 /* Pull-up/down registers */
  105. 0x70000868 0xa8 >; /* Pad control registers */
  106. };
  107. serial@70006000 {
  108. compatible = "nvidia,tegra20-uart";
  109. reg = <0x70006000 0x40>;
  110. reg-shift = <2>;
  111. interrupts = < 0 36 0x04 >;
  112. };
  113. serial@70006040 {
  114. compatible = "nvidia,tegra20-uart";
  115. reg = <0x70006040 0x40>;
  116. reg-shift = <2>;
  117. interrupts = < 0 37 0x04 >;
  118. };
  119. serial@70006200 {
  120. compatible = "nvidia,tegra20-uart";
  121. reg = <0x70006200 0x100>;
  122. reg-shift = <2>;
  123. interrupts = < 0 46 0x04 >;
  124. };
  125. serial@70006300 {
  126. compatible = "nvidia,tegra20-uart";
  127. reg = <0x70006300 0x100>;
  128. reg-shift = <2>;
  129. interrupts = < 0 90 0x04 >;
  130. };
  131. serial@70006400 {
  132. compatible = "nvidia,tegra20-uart";
  133. reg = <0x70006400 0x100>;
  134. reg-shift = <2>;
  135. interrupts = < 0 91 0x04 >;
  136. };
  137. emc@7000f400 {
  138. #address-cells = <1>;
  139. #size-cells = <0>;
  140. compatible = "nvidia,tegra20-emc";
  141. reg = <0x7000f400 0x200>;
  142. };
  143. sdhci@c8000000 {
  144. compatible = "nvidia,tegra20-sdhci";
  145. reg = <0xc8000000 0x200>;
  146. interrupts = < 0 14 0x04 >;
  147. };
  148. sdhci@c8000200 {
  149. compatible = "nvidia,tegra20-sdhci";
  150. reg = <0xc8000200 0x200>;
  151. interrupts = < 0 15 0x04 >;
  152. };
  153. sdhci@c8000400 {
  154. compatible = "nvidia,tegra20-sdhci";
  155. reg = <0xc8000400 0x200>;
  156. interrupts = < 0 19 0x04 >;
  157. };
  158. sdhci@c8000600 {
  159. compatible = "nvidia,tegra20-sdhci";
  160. reg = <0xc8000600 0x200>;
  161. interrupts = < 0 31 0x04 >;
  162. };
  163. usb@c5000000 {
  164. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  165. reg = <0xc5000000 0x4000>;
  166. interrupts = < 0 20 0x04 >;
  167. phy_type = "utmi";
  168. nvidia,has-legacy-mode;
  169. };
  170. usb@c5004000 {
  171. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  172. reg = <0xc5004000 0x4000>;
  173. interrupts = < 0 21 0x04 >;
  174. phy_type = "ulpi";
  175. };
  176. usb@c5008000 {
  177. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  178. reg = <0xc5008000 0x4000>;
  179. interrupts = < 0 97 0x04 >;
  180. phy_type = "utmi";
  181. };
  182. };