omap3.dtsi 2.3 KB

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  1. /*
  2. * Device Tree Source for OMAP3 SoC
  3. *
  4. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. compatible = "ti,omap3430", "ti,omap3";
  13. aliases {
  14. serial0 = &uart1;
  15. serial1 = &uart2;
  16. serial2 = &uart3;
  17. serial3 = &uart4;
  18. };
  19. cpus {
  20. cpu@0 {
  21. compatible = "arm,cortex-a8";
  22. };
  23. };
  24. /*
  25. * The soc node represents the soc top level view. It is uses for IPs
  26. * that are not memory mapped in the MPU view or for the MPU itself.
  27. */
  28. soc {
  29. compatible = "ti,omap-infra";
  30. mpu {
  31. compatible = "ti,omap3-mpu";
  32. ti,hwmods = "mpu";
  33. };
  34. iva {
  35. compatible = "ti,iva2.2";
  36. ti,hwmods = "iva";
  37. dsp {
  38. compatible = "ti,omap3-c64";
  39. };
  40. };
  41. };
  42. /*
  43. * XXX: Use a flat representation of the OMAP3 interconnect.
  44. * The real OMAP interconnect network is quite complex.
  45. * Since that will not bring real advantage to represent that in DT for
  46. * the moment, just use a fake OCP bus entry to represent the whole bus
  47. * hierarchy.
  48. */
  49. ocp {
  50. compatible = "simple-bus";
  51. #address-cells = <1>;
  52. #size-cells = <1>;
  53. ranges;
  54. ti,hwmods = "l3_main";
  55. intc: interrupt-controller@48200000 {
  56. compatible = "ti,omap2-intc";
  57. interrupt-controller;
  58. #interrupt-cells = <1>;
  59. ti,intc-size = <96>;
  60. reg = <0x48200000 0x1000>;
  61. };
  62. uart1: serial@4806a000 {
  63. compatible = "ti,omap3-uart";
  64. ti,hwmods = "uart1";
  65. clock-frequency = <48000000>;
  66. };
  67. uart2: serial@4806c000 {
  68. compatible = "ti,omap3-uart";
  69. ti,hwmods = "uart2";
  70. clock-frequency = <48000000>;
  71. };
  72. uart3: serial@49020000 {
  73. compatible = "ti,omap3-uart";
  74. ti,hwmods = "uart3";
  75. clock-frequency = <48000000>;
  76. };
  77. uart4: serial@49042000 {
  78. compatible = "ti,omap3-uart";
  79. ti,hwmods = "uart4";
  80. clock-frequency = <48000000>;
  81. };
  82. i2c1: i2c@48070000 {
  83. compatible = "ti,omap3-i2c";
  84. #address-cells = <1>;
  85. #size-cells = <0>;
  86. ti,hwmods = "i2c1";
  87. };
  88. i2c2: i2c@48072000 {
  89. compatible = "ti,omap3-i2c";
  90. #address-cells = <1>;
  91. #size-cells = <0>;
  92. ti,hwmods = "i2c2";
  93. };
  94. i2c3: i2c@48060000 {
  95. compatible = "ti,omap3-i2c";
  96. #address-cells = <1>;
  97. #size-cells = <0>;
  98. ti,hwmods = "i2c3";
  99. };
  100. };
  101. };