msmkrypton.dtsi 5.1 KB

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  1. /* Copyright (c) 2013, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. /include/ "skeleton.dtsi"
  13. / {
  14. model = "Qualcomm MSM KRYPTON";
  15. compatible = "qcom,msmkrypton";
  16. interrupt-parent = <&intc>;
  17. aliases {
  18. spi6 = &spi_6;
  19. };
  20. soc: soc { };
  21. };
  22. /include/ "msmkrypton-smp2p.dtsi"
  23. &soc {
  24. #address-cells = <1>;
  25. #size-cells = <1>;
  26. ranges;
  27. intc: interrupt-controller@f9000000 {
  28. compatible = "qcom,msm-qgic2";
  29. interrupt-controller;
  30. #interrupt-cells = <3>;
  31. reg = <0xf9000000 0x1000>,
  32. <0xf9002000 0x1000>;
  33. };
  34. msmgpio: gpio@fd510000 {
  35. compatible = "qcom,msm-gpio";
  36. gpio-controller;
  37. #gpio-cells = <2>;
  38. interrupt-controller;
  39. #interrupt-cells = <2>;
  40. reg = <0xfd510000 0x4000>;
  41. ngpio = <89>;
  42. interrupts = <0 208 0>;
  43. qcom,direct-connect-irqs = <8>;
  44. };
  45. qcom,msm-imem@fe805000 {
  46. compatible = "qcom,msm-imem";
  47. reg = <0xfe807800 0x1000>; /* Address and size of IMEM */
  48. };
  49. qcom,msm-mem-hole {
  50. compatible = "qcom,msm-mem-hole";
  51. qcom,memblock-remove = <0x02000000 0x06000000>; /* Address and Size of Hole */
  52. };
  53. timer@f9020000 {
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56. ranges;
  57. compatible = "arm,armv7-timer-mem";
  58. reg = <0xf9020000 0x1000>;
  59. clock-frequency = <19200000>;
  60. frame@f9021000 {
  61. frame-number = <0>;
  62. interrupts = <0 7 0x4>,
  63. <0 6 0x4>;
  64. reg = <0xf9021000 0x1000>,
  65. <0xf9022000 0x1000>;
  66. };
  67. frame@f9023000 {
  68. frame-number = <1>;
  69. interrupts = <0 8 0x4>;
  70. reg = <0xf9023000 0x1000>;
  71. status = "disabled";
  72. };
  73. frame@f9024000 {
  74. frame-number = <2>;
  75. interrupts = <0 9 0x4>;
  76. reg = <0xf9024000 0x1000>;
  77. status = "disabled";
  78. };
  79. frame@f9025000 {
  80. frame-number = <3>;
  81. interrupts = <0 10 0x4>;
  82. reg = <0xf9025000 0x1000>;
  83. status = "disabled";
  84. };
  85. frame@f9026000 {
  86. frame-number = <4>;
  87. interrupts = <0 11 0x4>;
  88. reg = <0xf9026000 0x1000>;
  89. status = "disabled";
  90. };
  91. frame@f9027000 {
  92. frame-number = <5>;
  93. interrupts = <0 12 0x4>;
  94. reg = <0xf9027000 0x1000>;
  95. status = "disabled";
  96. };
  97. frame@f9028000 {
  98. frame-number = <6>;
  99. interrupts = <0 13 0x4>;
  100. reg = <0xf9028000 0x1000>;
  101. status = "disabled";
  102. };
  103. frame@f9029000 {
  104. frame-number = <7>;
  105. interrupts = <0 14 0x4>;
  106. reg = <0xf9029000 0x1000>;
  107. status = "disabled";
  108. };
  109. };
  110. uartdm3: serial@f991f000 {
  111. compatible = "qcom,msm-lsuart-v14";
  112. reg = <0xf991f000 0x1000>;
  113. interrupts = <0 109 0>;
  114. status = "disabled";
  115. };
  116. qcom,sps@f9980000 {
  117. compatible = "qcom,msm_sps";
  118. reg = <0xf9984000 0x15000>,
  119. <0xf9999000 0xb000>,
  120. <0xfe803000 0xd000>,
  121. <0xfe805000 0x1000>;
  122. interrupts = <0 94 0>;
  123. };
  124. spi_6: spi@f9928000 { /* BLSP1 QUP6 */
  125. compatible = "qcom,spi-qup-v2";
  126. #address-cells = <1>;
  127. #size-cells = <0>;
  128. reg-names = "spi_physical", "spi_bam_physical";
  129. reg = <0xf9928000 0x1000>,
  130. <0xf9904000 0x19000>;
  131. interrupt-names = "spi_irq", "spi_bam_irq";
  132. interrupts = <0 100 0>, <0 238 0>;
  133. spi-max-frequency = <19200000>;
  134. qcom,gpio-mosi = <&msmgpio 20 0>;
  135. qcom,gpio-miso = <&msmgpio 21 0>;
  136. qcom,gpio-clk = <&msmgpio 23 0>;
  137. qcom,gpio-cs0 = <&msmgpio 22 0>;
  138. qcom,infinite-mode = <0>;
  139. qcom,use-bam;
  140. qcom,ver-reg-exists;
  141. qcom,bam-consumer-pipe-index = <22>;
  142. qcom,bam-producer-pipe-index = <23>;
  143. qcom,master-id = <86>;
  144. };
  145. qcom,ipc-spinlock@fd484000 {
  146. compatible = "qcom,ipc-spinlock-sfpb";
  147. reg = <0xfd484000 0x400>;
  148. qcom,num-locks = <8>;
  149. };
  150. qcom,smem@2200000 {
  151. compatible = "qcom,smem";
  152. reg = <0x2200000 0x100000>,
  153. <0xf9011000 0x1000>,
  154. <0xfc428000 0x4000>;
  155. reg-names = "smem", "irq-reg-base", "aux-mem1";
  156. qcom,smd-modem {
  157. compatible = "qcom,smd";
  158. qcom,smd-edge = <0>;
  159. qcom,smd-irq-offset = <0x8>;
  160. qcom,smd-irq-bitmask = <0x1000>;
  161. qcom,pil-string = "modem";
  162. interrupts = <0 25 1>;
  163. };
  164. qcom,smsm-modem {
  165. compatible = "qcom,smsm";
  166. qcom,smsm-edge = <0>;
  167. qcom,smsm-irq-offset = <0x8>;
  168. qcom,smsm-irq-bitmask = <0x2000>;
  169. interrupts = <0 26 1>;
  170. };
  171. qcom,smd-adsp {
  172. compatible = "qcom,smd";
  173. qcom,smd-edge = <1>;
  174. qcom,smd-irq-offset = <0x8>;
  175. qcom,smd-irq-bitmask = <0x100>;
  176. qcom,pil-string = "adsp";
  177. interrupts = <0 156 1>;
  178. };
  179. qcom,smsm-adsp {
  180. compatible = "qcom,smsm";
  181. qcom,smsm-edge = <1>;
  182. qcom,smsm-irq-offset = <0x8>;
  183. qcom,smsm-irq-bitmask = <0x200>;
  184. interrupts = <0 157 1>;
  185. };
  186. qcom,smd-rpm {
  187. compatible = "qcom,smd";
  188. qcom,smd-edge = <15>;
  189. qcom,smd-irq-offset = <0x8>;
  190. qcom,smd-irq-bitmask = <0x1>;
  191. interrupts = <0 168 1>;
  192. qcom,irq-no-suspend;
  193. };
  194. };
  195. rpm_bus: qcom,rpm-smd {
  196. compatible = "qcom,rpm-smd";
  197. rpm-channel-name = "rpm_requests";
  198. rpm-channel-type = <15>; /* SMD_APPS_RPM */
  199. rpm-standalone = <1>;
  200. };
  201. };