msm9625.dtsi 26 KB

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  1. /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. /include/ "skeleton.dtsi"
  13. / {
  14. model = "Qualcomm MSM 9625";
  15. compatible = "qcom,msm9625";
  16. interrupt-parent = <&intc>;
  17. aliases {
  18. spi0 = &spi_0;
  19. };
  20. soc: soc { };
  21. };
  22. /include/ "msm9625-ion.dtsi"
  23. /include/ "msm9625-pm.dtsi"
  24. /include/ "msm9625-coresight.dtsi"
  25. /include/ "msm9625-smp2p.dtsi"
  26. &soc {
  27. #address-cells = <1>;
  28. #size-cells = <1>;
  29. ranges;
  30. intc: interrupt-controller@F9000000 {
  31. compatible = "qcom,msm-qgic2";
  32. interrupt-controller;
  33. #interrupt-cells = <3>;
  34. reg = <0xF9000000 0x1000>,
  35. <0xF9002000 0x1000>;
  36. };
  37. l2: cache-controller@f9040000 {
  38. compatible = "arm,pl310-cache";
  39. reg = <0xf9040000 0x1000>;
  40. cache-unified;
  41. cache-level = <2>;
  42. };
  43. msmgpio: gpio@fd510000 {
  44. compatible = "qcom,msm-gpio";
  45. gpio-controller;
  46. #gpio-cells = <2>;
  47. interrupt-controller;
  48. #interrupt-cells = <2>;
  49. reg = <0xfd510000 0x4000>;
  50. ngpio = <76>;
  51. interrupts = <0 208 0>;
  52. qcom,direct-connect-irqs = <8>;
  53. };
  54. qcom,mpm2-sleep-counter@fc4a3000 {
  55. compatible = "qcom,mpm2-sleep-counter";
  56. reg = <0xfc4a3000 0x1000>;
  57. clock-frequency = <32768>;
  58. };
  59. timer@f9020000 {
  60. #address-cells = <1>;
  61. #size-cells = <1>;
  62. ranges;
  63. compatible = "arm,armv7-timer-mem";
  64. reg = <0xf9020000 0x1000>;
  65. clock-frequency = <19200000>;
  66. frame@f9021000 {
  67. frame-number = <0>;
  68. interrupts = <0 7 0x4>,
  69. <0 6 0x4>;
  70. reg = <0xf9021000 0x1000>,
  71. <0xf9022000 0x1000>;
  72. };
  73. frame@f9023000 {
  74. frame-number = <1>;
  75. interrupts = <0 8 0x4>;
  76. reg = <0xf9023000 0x1000>;
  77. status = "disabled";
  78. };
  79. frame@f9024000 {
  80. frame-number = <2>;
  81. interrupts = <0 9 0x4>;
  82. reg = <0xf9024000 0x1000>;
  83. status = "disabled";
  84. };
  85. frame@f9025000 {
  86. frame-number = <3>;
  87. interrupts = <0 10 0x4>;
  88. reg = <0xf9025000 0x1000>;
  89. status = "disabled";
  90. };
  91. frame@f9026000 {
  92. frame-number = <4>;
  93. interrupts = <0 11 0x4>;
  94. reg = <0xf9026000 0x1000>;
  95. status = "disabled";
  96. };
  97. frame@f9027000 {
  98. frame-number = <5>;
  99. interrupts = <0 12 0x4>;
  100. reg = <0xf9027000 0x1000>;
  101. status = "disabled";
  102. };
  103. frame@f9028000 {
  104. frame-number = <6>;
  105. interrupts = <0 13 0x4>;
  106. reg = <0xf9028000 0x1000>;
  107. status = "disabled";
  108. };
  109. frame@f9029000 {
  110. frame-number = <7>;
  111. interrupts = <0 14 0x4>;
  112. reg = <0xf9029000 0x1000>;
  113. status = "disabled";
  114. };
  115. };
  116. qcom,sps@f9980000 {
  117. compatible = "qcom,msm_sps";
  118. reg = <0xf9984000 0x15000>,
  119. <0xf9999000 0xb000>,
  120. <0xfe803000 0x4800>;
  121. interrupts = <0 94 0>;
  122. qcom,device-type = <2>;
  123. };
  124. serial@f991f000 {
  125. compatible = "qcom,msm-lsuart-v14";
  126. reg = <0xf991f000 0x1000>;
  127. interrupts = <0 109 0>;
  128. };
  129. hsusb_otg: usb@f9a55000 {
  130. compatible = "qcom,hsusb-otg";
  131. reg = <0xf9a55000 0x400>;
  132. interrupts = <0 134 0 0 140 0>;
  133. interrupt-names = "core_irq", "async_irq";
  134. HSUSB_VDDCX-supply = <&pm8019_l12>;
  135. HSUSB_1p8-supply = <&pm8019_l2>;
  136. HSUSB_3p3-supply = <&pm8019_l4>;
  137. vbus_otg-supply = <&usb_vbus>;
  138. qcom,hsusb-otg-phy-type = <2>;
  139. qcom,hsusb-otg-mode = <3>;
  140. qcom,hsusb-otg-otg-control = <1>;
  141. qcom,hsusb-otg-disable-reset;
  142. qcom,hsusb-otg-lpm-on-dev-suspend;
  143. qcom,hsusb-otg-clk-always-on-workaround;
  144. qcom,hsusb-otg-delay-lpm-hndshk-on-disconnect;
  145. qcom,hsusb-otg-delay-lpm;
  146. qcom,msm-bus,name = "usb2";
  147. qcom,msm-bus,num-cases = <2>;
  148. qcom,msm-bus,num-paths = <1>;
  149. qcom,msm-bus,vectors-KBps =
  150. <87 512 0 0>,
  151. <87 512 40000 640000>;
  152. qcom,hsusb-log2-itc = <4>;
  153. };
  154. hsic_host: hsic@f9a15000 {
  155. compatible = "qcom,hsic-host";
  156. reg = <0xf9a15000 0x400>;
  157. interrupts = <0 136 0>, <0 148 0>;
  158. interrupt-names = "core_irq", "async_irq";
  159. HSIC_VDDCX-supply = <&pm8019_l12>;
  160. HSIC_GDSC-supply = <&gdsc_usb_hsic>;
  161. qcom,msm-bus,name = "hsic";
  162. qcom,msm-bus,num-cases = <2>;
  163. qcom,msm-bus,num-paths = <1>;
  164. qcom,msm-bus,vectors-KBps =
  165. <85 512 0 0>,
  166. <85 512 40000 640000>;
  167. qcom,pool-64-bit-align;
  168. qcom,enable-hbm;
  169. hsic,consider-ipa-handshake;
  170. hsic,log2-itc = <3>;
  171. qcom,ahb-async-bridge-bypass;
  172. hsic,disable-cerr;
  173. };
  174. qcom,usbbam@f9a44000 {
  175. compatible = "qcom,usb-bam-msm";
  176. reg = <0xf9a44000 0x11000>,
  177. <0xf9a04000 0x11000>;
  178. reg-names = "hsusb", "hsic";
  179. interrupts = <0 135 0 0 255 0>;
  180. interrupt-names = "hsusb", "hsic";
  181. qcom,usb-bam-num-pipes = <16>;
  182. qcom,ignore-core-reset-ack;
  183. qcom,disable-clk-gating;
  184. qcom,pipe0 {
  185. label = "hsusb-ipa-out-0";
  186. qcom,usb-bam-mem-type = <2>;
  187. qcom,bam-type = <1>;
  188. qcom,dir = <0>;
  189. qcom,pipe-num = <0>;
  190. qcom,peer-bam = <2>;
  191. qcom,src-bam-physical-address = <0xf9a44000>;
  192. qcom,src-bam-pipe-index = <1>;
  193. qcom,data-fifo-size = <0x8000>;
  194. qcom,descriptor-fifo-size = <0x2000>;
  195. qcom,reset-bam-on-connect;
  196. };
  197. qcom,pipe1 {
  198. label = "hsusb-ipa-in-0";
  199. qcom,usb-bam-mem-type = <2>;
  200. qcom,bam-type = <1>;
  201. qcom,dir = <1>;
  202. qcom,pipe-num = <0>;
  203. qcom,peer-bam = <2>;
  204. qcom,dst-bam-physical-address = <0xf9a44000>;
  205. qcom,dst-bam-pipe-index = <0>;
  206. qcom,data-fifo-size = <0x8000>;
  207. qcom,descriptor-fifo-size = <0x2000>;
  208. qcom,reset-bam-on-connect;
  209. };
  210. qcom,pipe2 {
  211. label = "hsusb-qdss-in-0";
  212. qcom,usb-bam-mem-type = <0>;
  213. qcom,bam-type = <1>;
  214. qcom,dir = <1>;
  215. qcom,pipe-num = <0>;
  216. qcom,peer-bam = <1>;
  217. qcom,src-bam-physical-address = <0xfc37c000>;
  218. qcom,src-bam-pipe-index = <0>;
  219. qcom,dst-bam-physical-address = <0xf9a44000>;
  220. qcom,dst-bam-pipe-index = <2>;
  221. qcom,data-fifo-offset = <0x4100>;
  222. qcom,data-fifo-size = <0x700>;
  223. qcom,descriptor-fifo-offset = <0x4000>;
  224. qcom,descriptor-fifo-size = <0x100>;
  225. };
  226. qcom,pipe3 {
  227. label = "hsic-ipa-in-0";
  228. qcom,usb-bam-mem-type = <2>;
  229. qcom,bam-type = <2>;
  230. qcom,dir = <1>;
  231. qcom,pipe-num = <0>;
  232. qcom,peer-bam = <2>;
  233. qcom,dst-bam-physical-address = <0xf9a04000>;
  234. qcom,dst-bam-pipe-index = <3>;
  235. qcom,data-fifo-size = <0xF800>;
  236. qcom,descriptor-fifo-size = <0x3A58>;
  237. qcom,reset-bam-on-connect;
  238. };
  239. qcom,pipe4 {
  240. label = "hsic-ipa-in-1";
  241. qcom,bam-type = <2>;
  242. qcom,dir = <1>;
  243. qcom,pipe-num = <1>;
  244. qcom,peer-bam = <2>;
  245. qcom,usb-bam-mem-type = <2>;
  246. qcom,dst-bam-physical-address = <0xf9a04000>;
  247. qcom,dst-bam-pipe-index = <4>;
  248. qcom,data-fifo-size = <0xF800>;
  249. qcom,descriptor-fifo-size = <0x3A58>;
  250. qcom,reset-bam-on-connect;
  251. };
  252. qcom,pipe5 {
  253. label = "hsic-ipa-in-2";
  254. qcom,usb-bam-mem-type = <2>;
  255. qcom,bam-type = <2>;
  256. qcom,dir = <1>;
  257. qcom,pipe-num = <2>;
  258. qcom,peer-bam = <2>;
  259. qcom,dst-bam-physical-address = <0xf9a04000>;
  260. qcom,dst-bam-pipe-index = <5>;
  261. qcom,data-fifo-size = <0xF800>;
  262. qcom,descriptor-fifo-size = <0x3A58>;
  263. qcom,reset-bam-on-connect;
  264. };
  265. qcom,pipe6 {
  266. label = "hsic-ipa-in-3";
  267. qcom,usb-bam-mem-type = <2>;
  268. qcom,bam-type = <2>;
  269. qcom,dir = <1>;
  270. qcom,pipe-num = <3>;
  271. qcom,peer-bam = <2>;
  272. qcom,dst-bam-physical-address = <0xf9a04000>;
  273. qcom,dst-bam-pipe-index = <6>;
  274. qcom,data-fifo-size = <0xF800>;
  275. qcom,descriptor-fifo-size = <0x3A58>;
  276. qcom,reset-bam-on-connect;
  277. };
  278. qcom,pipe7 {
  279. label = "hsic-ipa-out-0";
  280. qcom,usb-bam-mem-type = <2>;
  281. qcom,bam-type = <2>;
  282. qcom,dir = <0>;
  283. qcom,pipe-num = <0>;
  284. qcom,peer-bam = <2>;
  285. qcom,src-bam-physical-address = <0xf9a04000>;
  286. qcom,src-bam-pipe-index = <7>;
  287. qcom,data-fifo-size = <0xDFE>;
  288. qcom,descriptor-fifo-size = <0xB30>;
  289. qcom,reset-bam-on-connect;
  290. };
  291. };
  292. qcom,nand@f9ac0000 {
  293. compatible = "qcom,msm-nand";
  294. reg = <0xf9ac0000 0x1000>,
  295. <0xf9ac4000 0x8000>;
  296. reg-names = "nand_phys",
  297. "bam_phys";
  298. interrupts = <0 247 0>;
  299. interrupt-names = "bam_irq";
  300. };
  301. spi_0: spi@f9924000 { /* BLSP1 QUP2 */
  302. compatible = "qcom,spi-qup-v2";
  303. #address-cells = <1>;
  304. #size-cells = <0>;
  305. reg-names = "spi_physical", "spi_bam_physical";
  306. reg = <0xf9924000 0x1000>,
  307. <0xf9904000 0x11000>;
  308. interrupt-names = "spi_irq", "spi_bam_irq";
  309. interrupts = <0 96 0>, <0 238 0>;
  310. spi-max-frequency = <19200000>;
  311. qcom,gpio-mosi = <&msmgpio 4 0>;
  312. qcom,gpio-miso = <&msmgpio 5 0>;
  313. qcom,gpio-clk = <&msmgpio 7 0>;
  314. qcom,gpio-cs0 = <&msmgpio 6 0>;
  315. qcom,infinite-mode = <0>;
  316. qcom,ver-reg-exists;
  317. qcom,bam-consumer-pipe-index = <14>;
  318. qcom,bam-producer-pipe-index = <15>;
  319. qcom,master-id = <86>;
  320. ethernet-switch@0 {
  321. compatible = "simtec,ks8851";
  322. reg = <0>;
  323. interrupt-parent = <&msmgpio>;
  324. interrupts = <75 0>;
  325. spi-max-frequency = <4800000>;
  326. };
  327. };
  328. qcom,wdt@f9017000 {
  329. compatible = "qcom,msm-watchdog";
  330. reg = <0xf9017000 0x1000>;
  331. interrupts = <1 2 0>, <1 1 0>;
  332. qcom,bark-time = <11000>;
  333. qcom,pet-time = <10000>;
  334. };
  335. rpm_bus: qcom,rpm-smd {
  336. compatible = "qcom,rpm-smd";
  337. rpm-channel-name = "rpm_requests";
  338. rpm-channel-type = <15>; /* SMD_APPS_RPM */
  339. };
  340. spmi_bus: qcom,spmi@fc4c0000 {
  341. cell-index = <0>;
  342. compatible = "qcom,spmi-pmic-arb";
  343. reg-names = "core", "intr", "cnfg";
  344. reg = <0xfc4cf000 0x1000>,
  345. <0Xfc4cb000 0x1000>,
  346. <0Xfc4ca000 0x1000>;
  347. /* 190,ee0_krait_hlos_spmi_periph_irq */
  348. /* 187,channel_0_krait_hlos_trans_done_irq */
  349. interrupts = <0 190 0 0 187 0>;
  350. qcom,pmic-arb-ee = <0>;
  351. qcom,pmic-arb-channel = <0>;
  352. };
  353. i2c@f9925000 {
  354. cell-index = <3>;
  355. compatible = "qcom,i2c-qup";
  356. reg = <0xf9925000 0x1000>;
  357. #address-cells = <1>;
  358. #size-cells = <0>;
  359. reg-names = "qup_phys_addr";
  360. interrupts = <0 97 0>;
  361. interrupt-names = "qup_err_intr";
  362. qcom,i2c-bus-freq = <100000>;
  363. qcom,i2c-src-freq = <24000000>;
  364. };
  365. sdcc2: qcom,sdcc@f98a4000 {
  366. cell-index = <2>; /* SDC2 SD card slot */
  367. compatible = "qcom,msm-sdcc";
  368. reg = <0xf98a4000 0x800>,
  369. <0xf98a4800 0x100>,
  370. <0xf9884000 0x7000>;
  371. reg-names = "core_mem", "dml_mem", "bam_mem";
  372. vdd-supply = <&ext_2p95v>;
  373. vdd-io-supply = <&pm8019_l13>;
  374. qcom,vdd-io-always-on;
  375. qcom,vdd-io-lpm-sup;
  376. qcom,vdd-io-voltage-level = <1800000 2950000>;
  377. qcom,vdd-io-current-level = <6 22000>;
  378. qcom,pad-pull-on = <0x0 0x3 0x3>;
  379. qcom,pad-pull-off = <0x0 0x3 0x3>;
  380. qcom,pad-drv-on = <0x4 0x4 0x4>;
  381. qcom,pad-drv-off = <0x0 0x0 0x0>;
  382. qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
  383. qcom,sup-voltages = <2950 2950>;
  384. qcom,bus-width = <4>;
  385. qcom,xpc;
  386. qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
  387. qcom,current-limit = <800>;
  388. interrupt-parent = <&sdcc2>;
  389. #address-cells = <0>;
  390. interrupts = <0 1 2>;
  391. #interrupt-cells = <1>;
  392. interrupt-map-mask = <0xffffffff>;
  393. interrupt-map = <0 &intc 0 125 0
  394. 1 &intc 0 220 0
  395. 2 &msmgpio 66 0x3>;
  396. interrupt-names = "core_irq", "bam_irq", "status_irq";
  397. cd-gpios = <&msmgpio 66 0>;
  398. };
  399. sdcc3: qcom,sdcc@f9864000 {
  400. cell-index = <3>; /* SDC3 SDIO slot */
  401. compatible = "qcom,msm-sdcc";
  402. reg = <0xf9864000 0x800>,
  403. <0xf9864800 0x100>,
  404. <0xf9844000 0x7000>;
  405. reg-names = "core_mem", "dml_mem", "bam_mem";
  406. interrupts = <0 127 0>, <0 223 0>;
  407. interrupt-names = "core_irq", "bam_irq";
  408. gpios = <&msmgpio 25 0>,
  409. <&msmgpio 24 0>,
  410. <&msmgpio 16 0>,
  411. <&msmgpio 17 0>,
  412. <&msmgpio 18 0>,
  413. <&msmgpio 19 0>;
  414. qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
  415. qcom,clk-rates = <400000 25000000 50000000 100000000>;
  416. qcom,sup-voltages = <2950 2950>;
  417. qcom,bus-width = <4>;
  418. qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
  419. };
  420. ipa_hw: qcom,ipa@fd4c0000 {
  421. compatible = "qcom,ipa";
  422. reg = <0xfd4c0000 0x26000>,
  423. <0xfd4c4000 0x14818>,
  424. <0xfc834000 0x7000>;
  425. reg-names = "ipa-base", "bam-base", "a2-bam-base";
  426. interrupts = <0 252 0>,
  427. <0 253 0>,
  428. <0 29 1>;
  429. interrupt-names = "ipa-irq", "bam-irq", "a2-bam-irq";
  430. qcom,pipe1 {
  431. label = "a2-to-ipa";
  432. qcom,src-bam-physical-address = <0xfc834000>;
  433. qcom,ipa-bam-mem-type = <0>;
  434. qcom,src-bam-pipe-index = <1>;
  435. qcom,dst-bam-physical-address = <0xfd4c0000>;
  436. qcom,dst-bam-pipe-index = <6>;
  437. qcom,data-fifo-offset = <0x1000>;
  438. qcom,data-fifo-size = <0xd00>;
  439. qcom,descriptor-fifo-offset = <0x1d00>;
  440. qcom,descriptor-fifo-size = <0x300>;
  441. };
  442. qcom,pipe2 {
  443. label = "ipa-to-a2";
  444. qcom,src-bam-physical-address = <0xfd4c0000>;
  445. qcom,ipa-bam-mem-type = <0>;
  446. qcom,src-bam-pipe-index = <7>;
  447. qcom,dst-bam-physical-address = <0xfc834000>;
  448. qcom,dst-bam-pipe-index = <0>;
  449. qcom,data-fifo-offset = <0x00>;
  450. qcom,data-fifo-size = <0xd00>;
  451. qcom,descriptor-fifo-offset = <0xd00>;
  452. qcom,descriptor-fifo-size = <0x300>;
  453. };
  454. };
  455. qcom,acpuclk@f9010000 {
  456. compatible = "qcom,acpuclk-9625";
  457. reg = <0xf9010008 0x10>,
  458. <0xf9008004 0x4>;
  459. reg-names = "rcg_base", "pwr_base";
  460. a5_cpu-supply = <&pm8019_l10_corner_ao>;
  461. a5_mem-supply = <&pm8019_l12_ao>;
  462. };
  463. gdsc_usb_hsic: qcom,gdsc@fc400404 {
  464. compatible = "qcom,gdsc";
  465. reg = <0xfc400404 0x4>;
  466. regulator-name = "gdsc_usb_hsic";
  467. };
  468. tsens@fc4a8000 {
  469. compatible = "qcom,msm-tsens";
  470. reg = <0xfc4a8000 0x2000>,
  471. <0xfc4bc000 0x1000>;
  472. reg-names = "tsens_physical", "tsens_eeprom_physical";
  473. interrupts = <0 184 0>;
  474. qcom,sensors = <5>;
  475. qcom,slope = <3200 3200 3200 3200 3200>;
  476. qcom,calib-mode = "fuse_map1";
  477. };
  478. qcom,msm-thermal {
  479. compatible = "qcom,msm-thermal";
  480. qcom,sensor-id = <0>;
  481. qcom,poll-ms = <250>;
  482. qcom,limit-temp = <60>;
  483. qcom,temp-hysteresis = <10>;
  484. qcom,freq-step = <2>;
  485. qcom,freq-control-mask = <0x0>;
  486. qcom,vdd-restriction-temp = <5>;
  487. qcom,vdd-restriction-temp-hysteresis = <10>;
  488. vdd-dig-supply = <&pm8019_l10_floor_corner>;
  489. qcom,vdd-dig-rstr{
  490. qcom,vdd-rstr-reg = "vdd-dig";
  491. qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */
  492. qcom,min-level = <1>; /* No Request */
  493. };
  494. };
  495. qcom,msm-rng@f9bff000 {
  496. compatible = "qcom,msm-rng";
  497. reg = <0xf9bff000 0x200>;
  498. qcom,msm-rng-iface-clk;
  499. };
  500. wcd9xxx_intc: wcd9xxx-irq {
  501. compatible = "qcom,wcd9xxx-irq";
  502. interrupt-controller;
  503. #interrupt-cells = <1>;
  504. interrupt-parent = <&msmgpio>;
  505. interrupts = <20 0>;
  506. interrupt-names = "cdc-int";
  507. };
  508. i2c@f9925000 {
  509. cell-index = <3>;
  510. compatible = "qcom,i2c-qup";
  511. reg = <0xf9925000 0x1000>;
  512. #address-cells = <1>;
  513. #size-cells = <0>;
  514. reg-names = "qup_phys_addr";
  515. interrupts = <0 97 0>;
  516. interrupt-names = "qup_err_intr";
  517. qcom,i2c-bus-freq = <100000>;
  518. qcom,i2c-src-freq = <24000000>;
  519. wcd9xxx_codec@0d{
  520. compatible = "qcom,wcd9xxx-i2c";
  521. reg = <0x0d>;
  522. qcom,cdc-reset-gpio = <&msmgpio 22 0>;
  523. interrupt-parent = <&wcd9xxx_intc>;
  524. interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28>;
  525. cdc-vdd-buck-supply = <&pm8019_l11>;
  526. qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
  527. qcom,cdc-vdd-buck-current = <25000>;
  528. cdc-vdd-tx-h-supply = <&pm8019_l11>;
  529. qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
  530. qcom,cdc-vdd-tx-h-current = <25000>;
  531. cdc-vdd-rx-h-supply = <&pm8019_l11>;
  532. qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
  533. qcom,cdc-vdd-rx-h-current = <25000>;
  534. cdc-vddpx-1-supply = <&pm8019_l11>;
  535. qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
  536. qcom,cdc-vddpx-1-current = <10000>;
  537. cdc-vdd-a-1p2v-supply = <&pm8019_l9>;
  538. qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>;
  539. qcom,cdc-vdd-a-1p2v-current = <10000>;
  540. cdc-vddcx-1-supply = <&pm8019_l9>;
  541. qcom,cdc-vddcx-1-voltage = <1200000 1200000>;
  542. qcom,cdc-vddcx-1-current = <10000>;
  543. cdc-vddcx-2-supply = <&pm8019_l9>;
  544. qcom,cdc-vddcx-2-voltage = <1200000 1200000>;
  545. qcom,cdc-vddcx-2-current = <10000>;
  546. qcom,cdc-static-supplies = "cdc-vdd-buck",
  547. "cdc-vdd-tx-h",
  548. "cdc-vdd-rx-h",
  549. "cdc-vddpx-1",
  550. "cdc-vdd-a-1p2v",
  551. "cdc-vddcx-1",
  552. "cdc-vddcx-2";
  553. qcom,cdc-micbias-ldoh-v = <0x3>;
  554. qcom,cdc-micbias-cfilt1-mv = <1800>;
  555. qcom,cdc-micbias-cfilt2-mv = <2700>;
  556. qcom,cdc-micbias-cfilt3-mv = <1800>;
  557. qcom,cdc-micbias1-cfilt-sel = <0x0>;
  558. qcom,cdc-micbias2-cfilt-sel = <0x1>;
  559. qcom,cdc-micbias3-cfilt-sel = <0x2>;
  560. qcom,cdc-micbias4-cfilt-sel = <0x2>;
  561. qcom,cdc-mclk-clk-rate = <12288000>;
  562. };
  563. wcd9xxx_codec@77{
  564. compatible = "qcom,wcd9xxx-i2c";
  565. reg = <0x77>;
  566. };
  567. wcd9xxx_codec@66{
  568. compatible = "qcom,wcd9xxx-i2c";
  569. reg = <0x66>;
  570. };
  571. wcd9xxx_codec@55{
  572. compatible = "qcom,wcd9xxx-i2c";
  573. reg = <0x55>;
  574. };
  575. };
  576. sound {
  577. compatible = "qcom,mdm9625-audio-taiko";
  578. qcom,model = "mdm9625-taiko-i2s-snd-card";
  579. qcom,audio-routing =
  580. "RX_BIAS", "MCLK",
  581. "LDO_H", "MCLK",
  582. "Ext Spk Bottom Pos", "LINEOUT1",
  583. "Ext Spk Bottom Neg", "LINEOUT3",
  584. "Ext Spk Top Pos", "LINEOUT2",
  585. "Ext Spk Top Neg", "LINEOUT4",
  586. "AMIC1", "MIC BIAS1 External",
  587. "MIC BIAS1 External", "Handset Mic",
  588. "AMIC2", "MIC BIAS2 External",
  589. "MIC BIAS2 External", "Headset Mic",
  590. "AMIC3", "MIC BIAS3 Internal1",
  591. "MIC BIAS3 Internal1", "ANCRight Headset Mic",
  592. "AMIC4", "MIC BIAS1 Internal2",
  593. "MIC BIAS1 Internal2", "ANCLeft Headset Mic",
  594. "DMIC1", "MIC BIAS1 External",
  595. "MIC BIAS1 External", "Digital Mic1",
  596. "DMIC2", "MIC BIAS1 External",
  597. "MIC BIAS1 External", "Digital Mic2",
  598. "DMIC3", "MIC BIAS3 External",
  599. "MIC BIAS3 External", "Digital Mic3",
  600. "DMIC4", "MIC BIAS3 External",
  601. "MIC BIAS3 External", "Digital Mic4",
  602. "DMIC5", "MIC BIAS4 External",
  603. "MIC BIAS4 External", "Digital Mic5",
  604. "DMIC6", "MIC BIAS4 External",
  605. "MIC BIAS4 External", "Digital Mic6";
  606. qcom,taiko-mclk-clk-freq = <12288000>;
  607. prim-i2s-gpio-ws = <&msmgpio 12 0>;
  608. prim-i2s-gpio-din = <&msmgpio 13 0>;
  609. prim-i2s-gpio-dout = <&msmgpio 14 0>;
  610. prim-i2s-gpio-sclk = <&msmgpio 15 0>;
  611. prim-i2s-gpio-mclk = <&msmgpio 71 0>;
  612. };
  613. qcom,msm-adsp-loader {
  614. compatible = "qcom,adsp-loader";
  615. qcom,adsp-state = <2>;
  616. };
  617. qti,msm-pcm {
  618. compatible = "qti,msm-pcm-dsp";
  619. qti,msm-pcm-dsp-id = <0>;
  620. };
  621. qcom,msm-pcm-routing {
  622. compatible = "qcom,msm-pcm-routing";
  623. };
  624. qcom,msm-compr-dsp {
  625. compatible = "qcom,msm-compr-dsp";
  626. };
  627. qcom,msm-voip-dsp {
  628. compatible = "qcom,msm-voip-dsp";
  629. };
  630. qcom,msm-pcm-voice {
  631. compatible = "qcom,msm-pcm-voice";
  632. };
  633. qcom,msm-stub-codec {
  634. compatible = "qcom,msm-stub-codec";
  635. };
  636. qcom,msm-dai-fe {
  637. compatible = "qcom,msm-dai-fe";
  638. };
  639. qcom,msm-pcm-afe {
  640. compatible = "qcom,msm-pcm-afe";
  641. };
  642. qcom,msm-pcm-hostless {
  643. compatible = "qcom,msm-pcm-hostless";
  644. };
  645. qcom,msm-dai-q6 {
  646. compatible = "qcom,msm-dai-q6";
  647. qcom,msm-dai-q6-be-afe-pcm-rx {
  648. compatible = "qcom,msm-dai-q6-dev";
  649. qcom,msm-dai-q6-dev-id = <224>;
  650. };
  651. qcom,msm-dai-q6-be-afe-pcm-tx {
  652. compatible = "qcom,msm-dai-q6-dev";
  653. qcom,msm-dai-q6-dev-id = <225>;
  654. };
  655. qcom,msm-dai-q6-afe-proxy-rx {
  656. compatible = "qcom,msm-dai-q6-dev";
  657. qcom,msm-dai-q6-dev-id = <241>;
  658. };
  659. qcom,msm-dai-q6-afe-proxy-tx {
  660. compatible = "qcom,msm-dai-q6-dev";
  661. qcom,msm-dai-q6-dev-id = <240>;
  662. };
  663. qcom,msm-dai-q6-incall-record-rx {
  664. compatible = "qcom,msm-dai-q6-dev";
  665. qcom,msm-dai-q6-dev-id = <32771>;
  666. };
  667. qcom,msm-dai-q6-incall-record-tx {
  668. compatible = "qcom,msm-dai-q6-dev";
  669. qcom,msm-dai-q6-dev-id = <32772>;
  670. };
  671. qcom,msm-dai-q6-incall-music-rx {
  672. compatible = "qcom,msm-dai-q6-dev";
  673. qcom,msm-dai-q6-dev-id = <32773>;
  674. };
  675. };
  676. qcom,msm-pcm-dtmf {
  677. compatible = "qcom,msm-pcm-dtmf";
  678. };
  679. qcom,msm-dai-stub {
  680. compatible = "qcom,msm-dai-stub";
  681. };
  682. qcom,msm-stub-codec {
  683. compatible = "qcom,msm-stub-codec";
  684. };
  685. qcom,msm-pri-auxpcm {
  686. compatible = "qcom,msm-auxpcm-dev";
  687. qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
  688. qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
  689. qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
  690. qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
  691. qcom,msm-cpudai-auxpcm-slot = <1>, <1>;
  692. qcom,msm-cpudai-auxpcm-data = <0>, <0>;
  693. qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
  694. qcom,msm-auxpcm-interface = "primary";
  695. };
  696. qcom,msm-dai-mi2s {
  697. compatible = "qcom,msm-dai-mi2s";
  698. qcom,msm-dai-q6-mi2s-prim {
  699. compatible = "qcom,msm-dai-q6-mi2s";
  700. qcom,msm-dai-q6-mi2s-dev-id = <0>;
  701. qcom,msm-mi2s-rx-lines = <2>;
  702. qcom,msm-mi2s-tx-lines = <1>;
  703. };
  704. };
  705. qcom,msm-dai-q6 {
  706. compatible = "qcom,msm-dai-q6";
  707. };
  708. qcom,mss {
  709. compatible = "qcom,pil-q6v5-mss";
  710. interrupts = <0 24 1>;
  711. qcom,is-not-loadable;
  712. /* GPIO inputs from mss */
  713. qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
  714. qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
  715. qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
  716. qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
  717. /* GPIO output to mss */
  718. qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
  719. };
  720. qcom,smem@0 {
  721. compatible = "qcom,smem";
  722. reg = <0x0 0x100000>,
  723. <0xf9011000 0x1000>,
  724. <0xfc428000 0x4000>;
  725. reg-names = "smem", "irq-reg-base", "aux-mem1";
  726. qcom,smd-modem {
  727. compatible = "qcom,smd";
  728. qcom,smd-edge = <0>;
  729. qcom,smd-irq-offset = <0x8>;
  730. qcom,smd-irq-bitmask = <0x1000>;
  731. qcom,pil-string = "modem";
  732. interrupts = <0 25 1>;
  733. };
  734. qcom,smsm-modem {
  735. compatible = "qcom,smsm";
  736. qcom,smsm-edge = <0>;
  737. qcom,smsm-irq-offset = <0x8>;
  738. qcom,smsm-irq-bitmask = <0x2000>;
  739. interrupts = <0 26 1>;
  740. };
  741. qcom,smd-adsp {
  742. compatible = "qcom,smd";
  743. qcom,smd-edge = <1>;
  744. qcom,smd-irq-offset = <0x8>;
  745. qcom,smd-irq-bitmask = <0x100>;
  746. qcom,pil-string = "adsp";
  747. interrupts = <0 156 1>;
  748. };
  749. qcom,smsm-adsp {
  750. compatible = "qcom,smsm";
  751. qcom,smsm-edge = <1>;
  752. qcom,smsm-irq-offset = <0x8>;
  753. qcom,smsm-irq-bitmask = <0x200>;
  754. interrupts = <0 157 1>;
  755. };
  756. qcom,smd-rpm {
  757. compatible = "qcom,smd";
  758. qcom,smd-edge = <15>;
  759. qcom,smd-irq-offset = <0x8>;
  760. qcom,smd-irq-bitmask = <0x1>;
  761. interrupts = <0 168 1>;
  762. qcom,irq-no-suspend;
  763. };
  764. };
  765. qcom,qcedev@fd400000 {
  766. compatible = "qcom,qcedev";
  767. reg = <0xfd400000 0x20000>,
  768. <0xfd404000 0x8000>;
  769. reg-names = "crypto-base","crypto-bam-base";
  770. interrupts = <0 207 0>;
  771. qcom,bam-pipe-pair = <1>;
  772. };
  773. qcom,qcrypto@fd440000 {
  774. compatible = "qcom,qcrypto";
  775. reg = <0xfd400000 0x20000>,
  776. <0xfd404000 0x8000>;
  777. reg-names = "crypto-base","crypto-bam-base";
  778. interrupts = <0 207 0>;
  779. qcom,bam-pipe-pair = <2>;
  780. };
  781. jtag_fuse: jtagfuse@fc4be024 {
  782. compatible = "qcom,jtag-fuse";
  783. reg = <0xfc4be024 0x8>;
  784. reg-names = "fuse-base";
  785. };
  786. jtag_mm: jtagmm@fc332000 {
  787. compatible = "qcom,jtag-mm";
  788. reg = <0xfc332000 0x1000>,
  789. <0xfc330000 0x1000>;
  790. reg-names = "etm-base","debug-base";
  791. };
  792. qcom,msm-rtb {
  793. compatible = "qcom,msm-rtb";
  794. qcom,memory-reservation-type = "EBI1";
  795. qcom,memory-reservation-size = <0x1000>; /* 4K EBI1 buffer */
  796. };
  797. qcom,msm-mem-hole {
  798. compatible = "qcom,msm-mem-hole";
  799. qcom,memblock-remove = <0x1f00000 0x5700000>; /* Address and Size of Hole */
  800. };
  801. sfpb_spinlock: qcom,ipc-spinlock@fd484000 {
  802. compatible = "qcom,ipc-spinlock-sfpb";
  803. reg = <0xfd484000 0x400>;
  804. qcom,num-locks = <8>;
  805. };
  806. ldrex_spinlock: qcom,ipc-spinlock@fa00000 {
  807. compatible = "qcom,ipc-spinlock-ldrex";
  808. reg = <0xfa00000 0x200000>;
  809. status = "disable";
  810. };
  811. cpu-pmu {
  812. compatible = "arm,cortex-a5-pmu";
  813. qcom,irq-is-percpu;
  814. interrupts = <1 7 0x00>;
  815. };
  816. l2-pmu {
  817. compatible = "qcom,l2-pmu";
  818. interrupts = <0 1 0>;
  819. };
  820. };
  821. /include/ "msm-pm8019-rpm-regulator.dtsi"
  822. /include/ "msm-pm8019.dtsi"
  823. /include/ "msm9625-regulator.dtsi"
  824. &pm8019_vadc {
  825. chan@31 {
  826. label = "batt_id_therm";
  827. reg = <0x31>;
  828. qcom,decimation = <0>;
  829. qcom,pre-div-channel-scaling = <0>;
  830. qcom,calibration-type = "ratiometric";
  831. qcom,scale-function = <0>;
  832. qcom,hw-settle-time = <2>;
  833. qcom,fast-avg-setup = <0>;
  834. };
  835. chan@33 {
  836. label = "pa_therm0";
  837. reg = <0x33>;
  838. qcom,decimation = <0>;
  839. qcom,pre-div-channel-scaling = <0>;
  840. qcom,calibration-type = "ratiometric";
  841. qcom,scale-function = <2>;
  842. qcom,hw-settle-time = <2>;
  843. qcom,fast-avg-setup = <0>;
  844. };
  845. chan@34 {
  846. label = "pa_therm1";
  847. reg = <0x34>;
  848. qcom,decimation = <0>;
  849. qcom,pre-div-channel-scaling = <0>;
  850. qcom,calibration-type = "ratiometric";
  851. qcom,scale-function = <2>;
  852. qcom,hw-settle-time = <2>;
  853. qcom,fast-avg-setup = <0>;
  854. };
  855. chan@32 {
  856. label = "xo_therm";
  857. reg = <0x32>;
  858. qcom,decimation = <0>;
  859. qcom,pre-div-channel-scaling = <0>;
  860. qcom,calibration-type = "ratiometric";
  861. qcom,scale-function = <4>;
  862. qcom,hw-settle-time = <2>;
  863. qcom,fast-avg-setup = <0>;
  864. };
  865. chan@3c {
  866. label = "xo_therm_amux";
  867. reg = <0x3c>;
  868. qcom,decimation = <0>;
  869. qcom,pre-div-channel-scaling = <0>;
  870. qcom,calibration-type = "ratiometric";
  871. qcom,scale-function = <4>;
  872. qcom,hw-settle-time = <2>;
  873. qcom,fast-avg-setup = <0>;
  874. };
  875. chan@13 {
  876. label = "case_therm";
  877. reg = <0x13>;
  878. qcom,decimation = <0>;
  879. qcom,pre-div-channel-scaling = <0>;
  880. qcom,calibration-type = "ratiometric";
  881. qcom,scale-function = <2>;
  882. qcom,hw-settle-time = <2>;
  883. qcom,fast-avg-setup = <0>;
  884. };
  885. chan@15 {
  886. label = "ambient_therm";
  887. reg = <0x15>;
  888. qcom,decimation = <0>;
  889. qcom,pre-div-channel-scaling = <0>;
  890. qcom,calibration-type = "ratiometric";
  891. qcom,scale-function = <2>;
  892. qcom,hw-settle-time = <2>;
  893. qcom,fast-avg-setup = <0>;
  894. };
  895. };
  896. &pm8019_adc_tm {
  897. /* Channel Node */
  898. chan@33 {
  899. label = "pa_therm0";
  900. reg = <0x33>;
  901. qcom,decimation = <0>;
  902. qcom,pre-div-channel-scaling = <0>;
  903. qcom,calibration-type = "ratiometric";
  904. qcom,scale-function = <2>;
  905. qcom,hw-settle-time = <2>;
  906. qcom,fast-avg-setup = <0>;
  907. qcom,btm-channel-number = <0x48>;
  908. qcom,thermal-node;
  909. };
  910. chan@34 {
  911. label = "pa_therm1";
  912. reg = <0x34>;
  913. qcom,decimation = <0>;
  914. qcom,pre-div-channel-scaling = <0>;
  915. qcom,calibration-type = "ratiometric";
  916. qcom,scale-function = <2>;
  917. qcom,hw-settle-time = <2>;
  918. qcom,fast-avg-setup = <0>;
  919. qcom,btm-channel-number = <0x68>;
  920. qcom,thermal-node;
  921. };
  922. };