msm8974-v1-pm.dtsi 9.4 KB

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  1. /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. &soc {
  13. qcom,spm@f9089000 {
  14. compatible = "qcom,spm-v2";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. reg = <0xf9089000 0x1000>;
  18. qcom,core-id = <0>;
  19. qcom,saw2-ver-reg = <0xfd0>;
  20. qcom,saw2-cfg = <0x01>;
  21. qcom,saw2-avs-ctl = <0>;
  22. qcom,saw2-avs-hysteresis = <0>;
  23. qcom,saw2-avs-limit = <0>;
  24. qcom,saw2-avs-dly= <0>;
  25. qcom,saw2-spm-dly= <0x20000400>;
  26. qcom,saw2-spm-ctl = <0x1>;
  27. qcom,saw2-spm-cmd-wfi = [03 0b 0f];
  28. qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0
  29. 0b 00 42 1b 0f];
  30. qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82
  31. 10 0b 30 06 26 30 0f];
  32. qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82
  33. 10 0b 30 06 26 30 0f];
  34. };
  35. qcom,spm@f9099000 {
  36. compatible = "qcom,spm-v2";
  37. #address-cells = <1>;
  38. #size-cells = <1>;
  39. reg = <0xf9099000 0x1000>;
  40. qcom,core-id = <1>;
  41. qcom,saw2-ver-reg = <0xfd0>;
  42. qcom,saw2-cfg = <0x01>;
  43. qcom,saw2-avs-ctl = <0>;
  44. qcom,saw2-avs-hysteresis = <0>;
  45. qcom,saw2-avs-limit = <0>;
  46. qcom,saw2-avs-dly= <0>;
  47. qcom,saw2-spm-dly= <0x20000400>;
  48. qcom,saw2-spm-ctl = <0x1>;
  49. qcom,saw2-spm-cmd-wfi = [03 0b 0f];
  50. qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0
  51. 0b 00 42 1b 0f];
  52. qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82
  53. 10 0b 30 06 26 30 0f];
  54. qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82
  55. 10 0b 30 06 26 30 0f];
  56. };
  57. qcom,spm@f90a9000 {
  58. compatible = "qcom,spm-v2";
  59. #address-cells = <1>;
  60. #size-cells = <1>;
  61. reg = <0xf90a9000 0x1000>;
  62. qcom,core-id = <2>;
  63. qcom,saw2-ver-reg = <0xfd0>;
  64. qcom,saw2-cfg = <0x01>;
  65. qcom,saw2-avs-ctl = <0>;
  66. qcom,saw2-avs-hysteresis = <0>;
  67. qcom,saw2-avs-limit = <0>;
  68. qcom,saw2-avs-dly= <0>;
  69. qcom,saw2-spm-dly= <0x20000400>;
  70. qcom,saw2-spm-ctl = <0x1>;
  71. qcom,saw2-spm-cmd-wfi = [03 0b 0f];
  72. qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0
  73. 0b 00 42 1b 0f];
  74. qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82
  75. 10 0b 30 06 26 30 0f];
  76. qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82
  77. 10 0b 30 06 26 30 0f];
  78. };
  79. qcom,spm@f90b9000 {
  80. compatible = "qcom,spm-v2";
  81. #address-cells = <1>;
  82. #size-cells = <1>;
  83. reg = <0xf90b9000 0x1000>;
  84. qcom,core-id = <3>;
  85. qcom,saw2-ver-reg = <0xfd0>;
  86. qcom,saw2-cfg = <0x01>;
  87. qcom,saw2-avs-ctl = <0>;
  88. qcom,saw2-avs-hysteresis = <0>;
  89. qcom,saw2-avs-limit = <0>;
  90. qcom,saw2-avs-dly= <0>;
  91. qcom,saw2-spm-dly= <0x20000400>;
  92. qcom,saw2-spm-ctl = <0x1>;
  93. qcom,saw2-spm-cmd-wfi = [03 0b 0f];
  94. qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0
  95. 0b 00 42 1b 0f];
  96. qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82
  97. 10 0b 30 06 26 30 0f];
  98. qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82
  99. 10 0b 30 06 26 30 0f];
  100. };
  101. qcom,spm@f9012000 {
  102. compatible = "qcom,spm-v2";
  103. #address-cells = <1>;
  104. #size-cells = <1>;
  105. reg = <0xf9012000 0x1000>;
  106. qcom,core-id = <0xffff>; /* L2/APCS SAW */
  107. qcom,saw2-ver-reg = <0xfd0>;
  108. qcom,saw2-cfg = <0x14>;
  109. qcom,saw2-avs-ctl = <0>;
  110. qcom,saw2-avs-hysteresis = <0>;
  111. qcom,saw2-avs-limit = <0>;
  112. qcom,saw2-avs-dly= <0>;
  113. qcom,saw2-spm-dly= <0x20000400>;
  114. qcom,saw2-spm-ctl = <0x1>;
  115. qcom,saw2-pmic-data0 = <0x02030080>;
  116. qcom,saw2-pmic-data1 = <0x00030000>;
  117. qcom,vctl-timeout-us = <50>;
  118. qcom,vctl-port = <0x0>;
  119. qcom,phase-port = <0x1>;
  120. qcom,pfm-port = <0x2>;
  121. qcom,saw2-spm-cmd-ret = [1f 00 20 03 22 00 0f];
  122. qcom,saw2-spm-cmd-gdhs = [00 20 32 42 03 44 22 50 02 32 50 0f];
  123. qcom,saw2-spm-cmd-pc = [00 10 32 b0 11 42 07 01 b0 12 44
  124. 50 02 32 50 0f];
  125. qcom,L2-spm-is-apcs-master;
  126. };
  127. lpm_levels: qcom,lpm-levels {
  128. compatible = "qcom,lpm-levels";
  129. qcom,default-l2-state = "l2_cache_retention";
  130. #address-cells = <1>;
  131. #size-cells = <0>;
  132. qcom,lpm-level@0 {
  133. reg = <0x0>;
  134. qcom,mode = "wfi";
  135. qcom,l2 = "l2_cache_active";
  136. qcom,latency-us = <1>;
  137. qcom,ss-power = <784>;
  138. qcom,energy-overhead = <190000>;
  139. qcom,time-overhead = <100>;
  140. };
  141. qcom,lpm-level@1 {
  142. reg = <0x1>;
  143. qcom,mode = "retention";
  144. qcom,l2 = "l2_cache_active";
  145. qcom,latency-us = <75>;
  146. qcom,ss-power = <735>;
  147. qcom,energy-overhead = <77341>;
  148. qcom,time-overhead = <105>;
  149. };
  150. qcom,lpm-level@2 {
  151. reg = <0x2>;
  152. qcom,mode = "standalone_pc";
  153. qcom,l2 = "l2_cache_active";
  154. qcom,latency-us = <95>;
  155. qcom,ss-power = <725>;
  156. qcom,energy-overhead = <99500>;
  157. qcom,time-overhead = <130>;
  158. };
  159. qcom,lpm-level@3 {
  160. reg = <0x3>;
  161. qcom,mode = "pc";
  162. qcom,l2 = "l2_cache_gdhs";
  163. qcom,latency-us = <20000>;
  164. qcom,ss-power = <138>;
  165. qcom,energy-overhead = <1208400>;
  166. qcom,time-overhead = <3200>;
  167. };
  168. qcom,lpm-level@4 {
  169. reg = <0x4>;
  170. qcom,mode = "pc";
  171. qcom,l2 = "l2_cache_pc";
  172. qcom,latency-us = <30000>;
  173. qcom,ss-power = <110>;
  174. qcom,energy-overhead = <1250300>;
  175. qcom,time-overhead = <3500>;
  176. };
  177. };
  178. qcom,pm-boot {
  179. compatible = "qcom,pm-boot";
  180. qcom,mode = "tz";
  181. };
  182. qcom,mpm@fc4281d0 {
  183. compatible = "qcom,mpm-v2";
  184. reg = <0xfc4281d0 0x1000>, /* MSM_RPM_MPM_BASE 4K */
  185. <0xf9011008 0x4>; /* MSM_APCS_GCC_BASE 4K */
  186. reg-names = "vmpm", "ipc";
  187. interrupts = <0 171 1>;
  188. qcom,ipc-bit-offset = <1>;
  189. qcom,gic-parent = <&intc>;
  190. qcom,gic-map = <2 216>, /* tsens_upper_lower_int */
  191. <47 165>, /* usb30_hs_phy_irq */
  192. <50 172>, /* usb1_hs_async_wakeup_irq */
  193. <53 104>, /* mdss_irq */
  194. <62 222>, /* ee0_krait_hlos_spmi_periph_irq */
  195. <0xff 34>, /* APCC_qgicL2ErrorIrptReq */
  196. <0xff 35>, /* WDT_barkInt */
  197. <0xff 40>, /* qtimer_phy_irq */
  198. <0xff 57>, /* mss_to_apps_irq(0) */
  199. <0xff 58>, /* mss_to_apps_irq(1) */
  200. <0xff 59>, /* mss_to_apps_irq(2) */
  201. <0xff 60>, /* mss_to_apps_irq(3) */
  202. <0xff 74>, /* osmmu_CIrpt[1] */
  203. <0xff 75>, /* osmmu_CIrpt[0] */
  204. <0xff 77>, /* osmmu_CIrpt[0] */
  205. <0xff 78>, /* osmmu_CIrpt[0] */
  206. <0xff 79>, /* osmmu_CIrpt[0] */
  207. <0xff 94>, /* osmmu_CIrpt[0] */
  208. <0xff 99>, /* msm_iommu_pmon_nonsecure_irq */
  209. <0xff 102>, /* osmmu_CIrpt[1] */
  210. <0xff 109>, /* ocmem_dm_nonsec_irq */
  211. <0xff 126>, /* bam_irq[0] */
  212. <0xff 155>, /* sdcc_irq[0] */
  213. <0xff 163>, /* usb30_ee1_irq */
  214. <0xff 170>, /* sdcc_pwr_cmd_irq */
  215. <0xff 173>, /* o_wcss_apss_smd_hi */
  216. <0xff 174>, /* o_wcss_apss_smd_med */
  217. <0xff 175>, /* o_wcss_apss_smd_low */
  218. <0xff 176>, /* o_wcss_apss_smsm_irq */
  219. <0xff 177>, /* o_wcss_apss_wlan_data_xfer_done */
  220. <0xff 178>, /* o_wcss_apss_wlan_rx_data_avail */
  221. <0xff 179>, /* o_wcss_apss_asic_intr */
  222. <0xff 188>, /* lpass_irq_out_apcs(0) */
  223. <0xff 189>, /* lpass_irq_out_apcs(1) */
  224. <0xff 190>, /* lpass_irq_out_apcs(2) */
  225. <0xff 191>, /* lpass_irq_out_apcs(3) */
  226. <0xff 192>, /* lpass_irq_out_apcs(4) */
  227. <0xff 193>, /* lpass_irq_out_apcs(5) */
  228. <0xff 194>, /* lpass_irq_out_apcs(6) */
  229. <0xff 195>, /* lpass_irq_out_apcs(7) */
  230. <0xff 196>, /* lpass_irq_out_apcs(8) */
  231. <0xff 197>, /* lpass_irq_out_apcs(9) */
  232. <0xff 198>, /* coresight-tmc-etr interrupt */
  233. <0xff 200>, /* rpm_ipc(4) */
  234. <0xff 201>, /* rpm_ipc(5) */
  235. <0xff 202>, /* rpm_ipc(6) */
  236. <0xff 203>, /* rpm_ipc(7) */
  237. <0xff 204>, /* rpm_ipc(24) */
  238. <0xff 205>, /* rpm_ipc(25) */
  239. <0xff 206>, /* rpm_ipc(26) */
  240. <0xff 207>, /* rpm_ipc(27) */
  241. <0xff 240>, /* summary_irq_kpss */
  242. <0xff 268>, /* bam_irq[1] */
  243. <0xff 270>, /* bam_irq[0] */
  244. <0xff 271>; /* bam_irq[0] */
  245. qcom,gpio-parent = <&msmgpio>;
  246. qcom,gpio-map = <3 102>,
  247. <4 1 >,
  248. <5 5 >,
  249. <6 9 >,
  250. <7 18>,
  251. <8 20>,
  252. <9 24>,
  253. <10 27>,
  254. <11 28>,
  255. <12 34>,
  256. <13 35>,
  257. <14 37>,
  258. <15 42>,
  259. <16 44>,
  260. <17 46>,
  261. <18 50>,
  262. <19 54>,
  263. <20 59>,
  264. <21 61>,
  265. <22 62>,
  266. <23 64>,
  267. <24 65>,
  268. <25 66>,
  269. <26 67>,
  270. <27 68>,
  271. <28 71>,
  272. <29 72>,
  273. <30 73>,
  274. <31 74>,
  275. <32 75>,
  276. <33 77>,
  277. <34 79>,
  278. <35 80>,
  279. <36 82>,
  280. <37 86>,
  281. <38 92>,
  282. <39 93>,
  283. <40 95>,
  284. <41 144>;
  285. };
  286. qcom,pm-8x60@fe805664 {
  287. compatible = "qcom,pm-8x60";
  288. #address-cells = <1>;
  289. #size-cells = <1>;
  290. ranges;
  291. reg = <0xfe805664 0x40>;
  292. qcom,pc-mode = "tz_l2_int";
  293. qcom,use-sync-timer;
  294. qcom,cpus-as-clocks;
  295. qcom,lpm-levels = <&lpm_levels>;
  296. };
  297. qcom,cpu-sleep-status@f9088008 {
  298. compatible = "qcom,cpu-sleep-status";
  299. reg = <0xf9088008 0x4>;
  300. qcom,cpu-alias-addr = <0x10000>;
  301. qcom,sleep-status-mask= <0x80000>;
  302. };
  303. qcom,rpm-log@fc19dc00 {
  304. compatible = "qcom,rpm-log";
  305. reg = <0xfc19dc00 0x4000>;
  306. qcom,rpm-addr-phys = <0xfc000000>;
  307. qcom,offset-version = <4>;
  308. qcom,offset-page-buffer-addr = <36>;
  309. qcom,offset-log-len = <40>;
  310. qcom,offset-log-len-mask = <44>;
  311. qcom,offset-page-indices = <56>;
  312. };
  313. qcom,rpm-stats@fc19dba0 {
  314. compatible = "qcom,rpm-stats";
  315. reg = <0xfc19dba0 0x1000>;
  316. reg-names = "phys_addr_base";
  317. qcom,sleep-stats-version = <2>;
  318. };
  319. qcom,rpm-master-stats@fc428150 {
  320. compatible = "qcom,rpm-master-stats";
  321. reg = <0xfc428150 0x3200>;
  322. qcom,masters = "APSS", "MPSS", "LPSS", "PRONTO";
  323. qcom,master-stats-version = <2>;
  324. qcom,master-offset = <2560>;
  325. };
  326. };