msm8610.dtsi 30 KB

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  1. /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. /include/ "skeleton.dtsi"
  13. / {
  14. model = "Qualcomm MSM 8610";
  15. compatible = "qcom,msm8610";
  16. interrupt-parent = <&intc>;
  17. memory {
  18. qsecom_mem: qsecom_region {
  19. linux,contiguous-region;
  20. reg = <0 0x100000>;
  21. label = "qsecom_mem";
  22. };
  23. };
  24. aliases {
  25. sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  26. sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  27. spi4 = &spi_4;
  28. };
  29. soc: soc { };
  30. };
  31. /include/ "msm8610-camera.dtsi"
  32. /include/ "msm-iommu-v0.dtsi"
  33. /include/ "msm8610-ion.dtsi"
  34. /include/ "msm8610-gpu.dtsi"
  35. /include/ "msm-gdsc.dtsi"
  36. /include/ "msm8610-coresight.dtsi"
  37. /include/ "msm8610-smp2p.dtsi"
  38. /include/ "msm8610-bus.dtsi"
  39. /include/ "msm8610-mdss.dtsi"
  40. /include/ "msm-rdbg.dtsi"
  41. &soc {
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges;
  45. intc: interrupt-controller@f9000000 {
  46. compatible = "qcom,msm-qgic2";
  47. interrupt-controller;
  48. #interrupt-cells = <3>;
  49. reg = <0xf9000000 0x1000>,
  50. <0xf9002000 0x1000>;
  51. };
  52. msmgpio: gpio@fd510000 {
  53. compatible = "qcom,msm-gpio";
  54. interrupt-controller;
  55. #interrupt-cells = <2>;
  56. reg = <0xfd510000 0x4000>;
  57. gpio-controller;
  58. #gpio-cells = <2>;
  59. ngpio = <102>;
  60. interrupts = <0 208 0>;
  61. qcom,direct-connect-irqs = <8>;
  62. };
  63. wcd9xxx_intc: wcd9xxx_irq {
  64. compatible = "qcom,wcd9xxx-irq";
  65. interrupt-controller;
  66. #interrupt-cells = <1>;
  67. interrupt-parent = <&intc>;
  68. interrupts = <0 31 0>;
  69. interrupt-names = "cdc-int";
  70. };
  71. qcom,mpm2-sleep-counter@fc4a3000 {
  72. compatible = "qcom,mpm2-sleep-counter";
  73. reg = <0xfc4a3000 0x1000>;
  74. clock-frequency = <32768>;
  75. };
  76. timer {
  77. compatible = "arm,armv7-timer";
  78. interrupts = <1 2 0 1 3 0>;
  79. clock-frequency = <19200000>;
  80. };
  81. timer@f9020000 {
  82. #address-cells = <1>;
  83. #size-cells = <1>;
  84. ranges;
  85. compatible = "arm,armv7-timer-mem";
  86. reg = <0xf9020000 0x1000>;
  87. clock-frequency = <19200000>;
  88. frame@f9021000 {
  89. frame-number = <0>;
  90. interrupts = <0 8 0x4>,
  91. <0 7 0x4>;
  92. reg = <0xf9021000 0x1000>,
  93. <0xf9022000 0x1000>;
  94. };
  95. frame@f9023000 {
  96. frame-number = <1>;
  97. interrupts = <0 9 0x4>;
  98. reg = <0xf9023000 0x1000>;
  99. status = "disabled";
  100. };
  101. frame@f9024000 {
  102. frame-number = <2>;
  103. interrupts = <0 10 0x4>;
  104. reg = <0xf9024000 0x1000>;
  105. status = "disabled";
  106. };
  107. frame@f9025000 {
  108. frame-number = <3>;
  109. interrupts = <0 11 0x4>;
  110. reg = <0xf9025000 0x1000>;
  111. status = "disabled";
  112. };
  113. frame@f9026000 {
  114. frame-number = <4>;
  115. interrupts = <0 12 0x4>;
  116. reg = <0xf9026000 0x1000>;
  117. status = "disabled";
  118. };
  119. frame@f9027000 {
  120. frame-number = <5>;
  121. interrupts = <0 13 0x4>;
  122. reg = <0xf9027000 0x1000>;
  123. status = "disabled";
  124. };
  125. frame@f9028000 {
  126. frame-number = <6>;
  127. interrupts = <0 14 0x4>;
  128. reg = <0xf9028000 0x1000>;
  129. status = "disabled";
  130. };
  131. };
  132. qcom,msm-adsp-loader {
  133. compatible = "qcom,adsp-loader";
  134. qcom,adsp-state = <0>;
  135. };
  136. qcom,msm-audio-ion {
  137. compatible = "qcom,msm-audio-ion";
  138. qcom,smmu-enabled;
  139. };
  140. qcom,msm-imem@fe805000 {
  141. compatible = "qcom,msm-imem";
  142. reg = <0xfe805000 0x1000>; /* Address and size of IMEM */
  143. };
  144. serial@f991f000 {
  145. compatible = "qcom,msm-lsuart-v14";
  146. reg = <0xf991f000 0x1000>;
  147. interrupts = <0 109 0>;
  148. status = "disabled";
  149. };
  150. serial@f991e000 {
  151. compatible = "qcom,msm-lsuart-v14";
  152. reg = <0xf991e000 0x1000>;
  153. interrupts = <0 108 0>;
  154. status = "disabled";
  155. };
  156. qcom,vidc@fdc00000 {
  157. compatible = "qcom,msm-vidc";
  158. qcom,vidc-ns-map = <0x40000000 0x40000000>;
  159. qcom,buffer-type-tz-usage-map = <0x1 0x1>,
  160. <0x7fe 0x2>;
  161. qcom,hfi = "q6";
  162. qcom,max-hw-load = <244800>; /* 1080p @ 30 * 1 */
  163. qcom,vidc-iommu-domains {
  164. qcom,domain-ns {
  165. qcom,vidc-domain-phandle = <&q6_domain_ns>;
  166. qcom,vidc-partition-buffer-types = <0xfff>;
  167. };
  168. };
  169. };
  170. qcom,usbbam@f9a44000 {
  171. compatible = "qcom,usb-bam-msm";
  172. reg = <0xf9a44000 0x11000>;
  173. reg-names = "hsusb";
  174. interrupts = <0 135 0>;
  175. interrupt-names = "hsusb";
  176. qcom,usb-bam-num-pipes = <16>;
  177. qcom,usb-bam-fifo-baseaddr = <0xfe803000>;
  178. qcom,ignore-core-reset-ack;
  179. qcom,disable-clk-gating;
  180. qcom,pipe0 {
  181. label = "hsusb-qdss-in-0";
  182. qcom,usb-bam-mem-type = <3>;
  183. qcom,bam-type = <1>;
  184. qcom,dir = <1>;
  185. qcom,pipe-num = <0>;
  186. qcom,peer-bam = <1>;
  187. qcom,src-bam-physical-address = <0xfc37c000>;
  188. qcom,src-bam-pipe-index = <0>;
  189. qcom,dst-bam-physical-address = <0xf9a44000>;
  190. qcom,dst-bam-pipe-index = <2>;
  191. qcom,data-fifo-offset = <0x0>;
  192. qcom,data-fifo-size = <0x600>;
  193. qcom,descriptor-fifo-offset = <0x600>;
  194. qcom,descriptor-fifo-size = <0x200>;
  195. };
  196. };
  197. usb@f9a55000 {
  198. compatible = "qcom,hsusb-otg";
  199. reg = <0xf9a55000 0x400>;
  200. interrupts = <0 134 0>, <0 140 0>;
  201. interrupt-names = "core_irq", "async_irq";
  202. hsusb_vdd_dig-supply = <&pm8110_s1_corner>;
  203. HSUSB_1p8-supply = <&pm8110_l10>;
  204. HSUSB_3p3-supply = <&pm8110_l20>;
  205. qcom,vdd-voltage-level = <1 5 7>;
  206. qcom,hsusb-otg-phy-init-seq =
  207. <0x44 0x80 0x68 0x81 0x24 0x82 0x13 0x83 0xffffffff>;
  208. qcom,hsusb-otg-phy-type = <2>;
  209. qcom,hsusb-otg-mode = <1>;
  210. qcom,hsusb-otg-otg-control = <2>;
  211. qcom,hsusb-otg-disable-reset;
  212. qcom,dp-manual-pullup;
  213. qcom,disable-retention-with-vdd-min;
  214. qcom,msm-bus,name = "usb2";
  215. qcom,msm-bus,num-cases = <2>;
  216. qcom,msm-bus,active-only = <0>;
  217. qcom,msm-bus,num-paths = <1>;
  218. qcom,msm-bus,vectors-KBps =
  219. <87 512 0 0>,
  220. <87 512 60000 960000>;
  221. };
  222. android_usb: android_usb@fe8050c8 {
  223. compatible = "qcom,android-usb";
  224. reg = <0xfe8050c8 0xc8>;
  225. qcom,android-usb-swfi-latency = <1>;
  226. qcom,streaming-func = "rndis";
  227. qcom,android-usb-uicc-nluns = <1>;
  228. };
  229. rmtfs_sharedmem {
  230. compatible = "qcom,sharedmem-uio";
  231. reg = <0x0dc80000 0x00180000>;
  232. reg-names = "rmtfs";
  233. };
  234. dsp_sharedmem {
  235. compatible = "qcom,sharedmem-uio";
  236. reg = <0x0dc60000 0x00020000>;
  237. reg-names = "rfsa_dsp";
  238. };
  239. mdm_sharedmem {
  240. compatible = "qcom,sharedmem-uio";
  241. reg = <0x0dc60000 0x00020000>;
  242. reg-names = "rfsa_mdm";
  243. };
  244. sdcc1: qcom,sdcc@f9824000 {
  245. cell-index = <1>; /* SDC1 eMMC slot */
  246. compatible = "qcom,msm-sdcc";
  247. reg = <0xf9824000 0x800>,
  248. <0xf9824800 0x100>,
  249. <0xf9804000 0x7000>;
  250. reg-names = "core_mem", "dml_mem", "bam_mem";
  251. interrupts = <0 123 0>, <0 137 0>;
  252. interrupt-names = "core_irq", "bam_irq";
  253. vdd-supply = <&pm8110_l17>;
  254. qcom,vdd-voltage-level = <2900000 2900000>;
  255. qcom,vdd-current-level = <9000 400000>;
  256. vdd-io-supply = <&pm8110_l6>;
  257. qcom,vdd-io-always-on;
  258. qcom,vdd-io-voltage-level = <1800000 1800000>;
  259. qcom,vdd-io-current-level = <9000 60000>;
  260. qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
  261. qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
  262. qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */
  263. qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
  264. qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
  265. qcom,sup-voltages = <2900 2900>;
  266. qcom,bus-width = <8>;
  267. qcom,nonremovable;
  268. qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
  269. qcom,cpu-dma-latency-us = <701>;
  270. status = "disabled";
  271. };
  272. sdcc2: qcom,sdcc@f98a4000 {
  273. cell-index = <2>; /* SDC2 SD card slot */
  274. compatible = "qcom,msm-sdcc";
  275. reg = <0xf98a4000 0x800>,
  276. <0xf98a4800 0x100>,
  277. <0xf9884000 0x7000>;
  278. reg-names = "core_mem", "dml_mem", "bam_mem";
  279. interrupts = <0 125 0>, <0 220 0>;
  280. interrupt-names = "core_irq", "bam_irq";
  281. vdd-supply = <&pm8110_l18>;
  282. qcom,vdd-voltage-level = <2950000 2950000>;
  283. qcom,vdd-current-level = <9000 400000>;
  284. vdd-io-supply = <&pm8110_l21>;
  285. qcom,vdd-io-voltage-level = <1800000 2950000>;
  286. qcom,vdd-io-current-level = <9000 50000>;
  287. qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
  288. qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
  289. qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */
  290. qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
  291. qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
  292. qcom,sup-voltages = <2950 2950>;
  293. qcom,bus-width = <4>;
  294. qcom,xpc;
  295. qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
  296. qcom,current-limit = <800>;
  297. qcom,cpu-dma-latency-us = <701>;
  298. status = "disabled";
  299. };
  300. sdhc_1: sdhci@f9824900 {
  301. compatible = "qcom,sdhci-msm";
  302. reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
  303. reg-names = "hc_mem", "core_mem";
  304. interrupts = <0 123 0>, <0 138 0>;
  305. interrupt-names = "hc_irq", "pwr_irq";
  306. qcom,bus-width = <8>;
  307. qcom,cpu-dma-latency-us = <701>;
  308. status = "disabled";
  309. };
  310. sdhc_2: sdhci@f98a4900 {
  311. compatible = "qcom,sdhci-msm";
  312. reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
  313. reg-names = "hc_mem", "core_mem";
  314. interrupts = <0 125 0>, <0 221 0>;
  315. interrupt-names = "hc_irq", "pwr_irq";
  316. qcom,bus-width = <4>;
  317. qcom,cpu-dma-latency-us = <701>;
  318. status = "disabled";
  319. };
  320. qcom,sps {
  321. compatible = "qcom,msm_sps";
  322. qcom,device-type = <3>;
  323. };
  324. qcom,smem@d900000 {
  325. compatible = "qcom,smem";
  326. reg = <0xd900000 0x100000>,
  327. <0xf9011000 0x1000>,
  328. <0xfc428000 0x4000>;
  329. reg-names = "smem", "irq-reg-base", "aux-mem1";
  330. qcom,smd-modem {
  331. compatible = "qcom,smd";
  332. qcom,smd-edge = <0>;
  333. qcom,smd-irq-offset = <0x8>;
  334. qcom,smd-irq-bitmask = <0x1000>;
  335. qcom,pil-string = "modem";
  336. interrupts = <0 25 1>;
  337. };
  338. qcom,smsm-modem {
  339. compatible = "qcom,smsm";
  340. qcom,smsm-edge = <0>;
  341. qcom,smsm-irq-offset = <0x8>;
  342. qcom,smsm-irq-bitmask = <0x2000>;
  343. interrupts = <0 26 1>;
  344. };
  345. qcom,smd-adsp {
  346. compatible = "qcom,smd";
  347. qcom,smd-edge = <1>;
  348. qcom,smd-irq-offset = <0x8>;
  349. qcom,smd-irq-bitmask = <0x100>;
  350. qcom,pil-string = "adsp";
  351. interrupts = <0 156 1>;
  352. };
  353. qcom,smsm-adsp {
  354. compatible = "qcom,smsm";
  355. qcom,smsm-edge = <1>;
  356. qcom,smsm-irq-offset = <0x8>;
  357. qcom,smsm-irq-bitmask = <0x200>;
  358. interrupts = <0 157 1>;
  359. };
  360. qcom,smd-wcnss {
  361. compatible = "qcom,smd";
  362. qcom,smd-edge = <6>;
  363. qcom,smd-irq-offset = <0x8>;
  364. qcom,smd-irq-bitmask = <0x20000>;
  365. qcom,pil-string = "wcnss";
  366. interrupts = <0 142 1>;
  367. };
  368. qcom,smsm-wcnss {
  369. compatible = "qcom,smsm";
  370. qcom,smsm-edge = <6>;
  371. qcom,smsm-irq-offset = <0x8>;
  372. qcom,smsm-irq-bitmask = <0x80000>;
  373. interrupts = <0 144 1>;
  374. };
  375. qcom,smd-rpm {
  376. compatible = "qcom,smd";
  377. qcom,smd-edge = <15>;
  378. qcom,smd-irq-offset = <0x8>;
  379. qcom,smd-irq-bitmask = <0x1>;
  380. interrupts = <0 168 1>;
  381. qcom,irq-no-suspend;
  382. };
  383. };
  384. rpm_bus: qcom,rpm-smd {
  385. compatible = "qcom,rpm-smd";
  386. rpm-channel-name = "rpm_requests";
  387. rpm-channel-type = <15>; /* SMD_APPS_RPM */
  388. };
  389. qcom,bcl {
  390. compatible = "qcom,bcl";
  391. };
  392. qcom,msm-mem-hole {
  393. compatible = "qcom,msm-mem-hole";
  394. qcom,memblock-remove = <0x08800000 0x5600000>; /* Address and Size of Hole */
  395. };
  396. qcom,wdt@f9017000 {
  397. compatible = "qcom,msm-watchdog";
  398. reg = <0xf9017000 0x1000>;
  399. interrupts = <0 3 0>, <0 4 0>;
  400. qcom,bark-time = <11000>;
  401. qcom,pet-time = <10000>;
  402. qcom,ipi-ping;
  403. };
  404. qcom,clock-a7@f9011050 {
  405. compatible = "qcom,clock-a7-8226";
  406. reg = <0xf9011050 0x8>,
  407. <0xfc4b80b8 0x8>;
  408. reg-names = "rcg-base", "efuse";
  409. clock-names = "clk-4", "clk-5";
  410. qcom,speed0-bin-v0 =
  411. < 0 0>,
  412. < 384000000 1>,
  413. < 787200000 2>,
  414. <1190400000 3>;
  415. qcom,speed1-bin-v0 =
  416. < 0 0>,
  417. < 384000000 1>,
  418. < 787200000 2>,
  419. <1094400000 3>;
  420. qcom,speed1-bin-v2 =
  421. < 0 0>,
  422. < 384000000 1>,
  423. < 787200000 2>,
  424. <1094400000 3>;
  425. cpu-vdd-supply = <&apc_vreg_corner>;
  426. };
  427. qcom,cpubw {
  428. compatible = "qcom,cpubw";
  429. qcom,cpu-mem-ports = <1 512>;
  430. qcom,bw-tbl =
  431. < 762 /* 100 MHz */ >,
  432. < 1525 /* 200 MHz */ >,
  433. < 2540 /* 333 MHz */ >;
  434. };
  435. qcom,msm-cpufreq@0 {
  436. reg = <0 4>;
  437. compatible = "qcom,msm-cpufreq";
  438. qcom,cpufreq-table =
  439. < 300000 762 >,
  440. < 384000 762 >,
  441. < 600000 1525 >,
  442. < 787200 1525 >,
  443. < 998400 2540 >,
  444. < 1094400 2540 >,
  445. < 1190400 2540 >;
  446. };
  447. spmi_bus: qcom,spmi@fc4c0000 {
  448. cell-index = <0>;
  449. compatible = "qcom,spmi-pmic-arb";
  450. reg-names = "core", "intr", "cnfg";
  451. reg = <0xfc4cf000 0x1000>,
  452. <0Xfc4cb000 0x1000>,
  453. <0Xfc4ca000 0x1000>;
  454. /* 190,ee0_krait_hlos_spmi_periph_irq */
  455. /* 187,channel_0_krait_hlos_trans_done_irq */
  456. interrupts = <0 190 0>, <0 187 0>;
  457. qcom,pmic-arb-ee = <0>;
  458. qcom,pmic-arb-channel = <0>;
  459. };
  460. i2c@f9923000 { /* BLSP-1 QUP-1 */
  461. cell-index = <1>;
  462. compatible = "qcom,i2c-qup";
  463. #address-cells = <1>;
  464. #size-cells = <0>;
  465. reg-names = "qup_phys_addr";
  466. reg = <0xf9923000 0x1000>;
  467. interrupt-names = "qup_err_intr";
  468. interrupts = <0 95 0>;
  469. qcom,i2c-bus-freq = <100000>;
  470. qcom,i2c-src-freq = <19200000>;
  471. qcom,sda-gpio = <&msmgpio 2 0>;
  472. qcom,scl-gpio = <&msmgpio 3 0>;
  473. qcom,master-id = <86>;
  474. };
  475. i2c_cdc: i2c@f9927000 { /* BLSP1 QUP5 */
  476. cell-index = <5>;
  477. compatible = "qcom,i2c-qup";
  478. #address-cells = <1>;
  479. #size-cells = <0>;
  480. reg-names = "qup_phys_addr";
  481. reg = <0xf9927000 0x1000>;
  482. interrupt-names = "qup_err_intr";
  483. interrupts = <0 99 0>;
  484. qcom,i2c-bus-freq = <100000>;
  485. qcom,i2c-src-freq = <19200000>;
  486. qcom,master-id = <86>;
  487. };
  488. i2c: i2c@f9928000 { /* BLSP1 QUP6 */
  489. cell-index = <6>;
  490. compatible = "qcom,i2c-qup";
  491. #address-cells = <1>;
  492. #size-cells = <0>;
  493. reg-names = "qup_phys_addr";
  494. reg = <0xf9928000 0x1000>;
  495. interrupt-names = "qup_err_intr";
  496. interrupts = <0 100 0>;
  497. qcom,i2c-bus-freq = <100000>;
  498. qcom,i2c-src-freq = <19200000>;
  499. qcom,sda-gpio = <&msmgpio 16 0>;
  500. qcom,scl-gpio = <&msmgpio 17 0>;
  501. qcom,master-id = <86>;
  502. };
  503. i2c@f9924000 { /* BLSP-1 QUP-3 */
  504. cell-index = <2>;
  505. compatible = "qcom,i2c-qup";
  506. #address-cells = <1>;
  507. #size-cells = <0>;
  508. reg-names = "qup_phys_addr";
  509. reg = <0xf9924000 0x1000>;
  510. interrupt-names = "qup_err_intr";
  511. interrupts = <0 96 0>;
  512. qcom,i2c-bus-freq = <100000>;
  513. qcom,i2c-src-freq = <19200000>;
  514. qcom,sda-gpio = <&msmgpio 8 0>;
  515. qcom,scl-gpio = <&msmgpio 9 0>;
  516. qcom,master-id = <86>;
  517. };
  518. i2c@f9925000 { /* BLSP-1 QUP-3 */
  519. cell-index = <0>;
  520. compatible = "qcom,i2c-qup";
  521. #address-cells = <1>;
  522. #size-cells = <0>;
  523. reg-names = "qup_phys_addr";
  524. reg = <0xf9925000 0x1000>;
  525. interrupt-names = "qup_err_intr";
  526. interrupts = <0 97 0>;
  527. qcom,i2c-bus-freq = <100000>;
  528. qcom,i2c-src-freq = <19200000>;
  529. qcom,sda-gpio = <&msmgpio 10 0>;
  530. qcom,scl-gpio = <&msmgpio 11 0>;
  531. qcom,clk-ctl-xfer;
  532. qcom,master-id = <86>;
  533. };
  534. spi_4: spi@f9926000 { /* BLSP1 QUP4 */
  535. compatible = "qcom,spi-qup-v2";
  536. #address-cells = <1>;
  537. #size-cells = <0>;
  538. reg-names = "spi_physical", "spi_bam_physical";
  539. reg = <0xf9926000 0x1000>,
  540. <0xf9904000 0x15000>;
  541. interrupt-names = "spi_irq", "spi_bam_irq";
  542. interrupts = <0 98 0>, <0 238 0>;
  543. spi-max-frequency = <50000000>;
  544. qcom,gpio-mosi = <&msmgpio 86 0>;
  545. qcom,gpio-miso = <&msmgpio 87 0>;
  546. qcom,gpio-clk = <&msmgpio 89 0>;
  547. qcom,gpio-cs0 = <&msmgpio 88 0>;
  548. qcom,gpio-cs2 = <&msmgpio 85 0>;
  549. qcom,infinite-mode = <0>;
  550. qcom,use-bam;
  551. qcom,ver-reg-exists;
  552. qcom,bam-consumer-pipe-index = <18>;
  553. qcom,bam-producer-pipe-index = <19>;
  554. qcom,master-id = <86>;
  555. lattice,spi-usb@2 {
  556. compatible = "lattice,ice40-spi-usb";
  557. reg = <2>;
  558. spi-max-frequency = <50000000>;
  559. spi-cpol = <1>;
  560. spi-cpha = <1>;
  561. core-vcc-supply = <&pm8110_l2>;
  562. spi-vcc-supply = <&pm8110_l6>;
  563. gpio-supply = <&pm8110_l22>;
  564. lattice,reset-gpio = <&msmgpio 95 0>;
  565. lattice,slave-select-gpio = <&msmgpio 85 0>;
  566. lattice,config-done-gpio = <&msmgpio 94 0>;
  567. lattice,vcc-en-gpio = <&msmgpio 96 0>;
  568. };
  569. };
  570. qcom,pronto@fb21b000 {
  571. compatible = "qcom,pil-pronto";
  572. reg = <0xfb21b000 0x3000>,
  573. <0xfc401700 0x4>,
  574. <0xfd485300 0xc>;
  575. reg-names = "pmu_base", "clk_base", "halt_base";
  576. interrupts = <0 149 1>;
  577. vdd_pronto_pll-supply = <&pm8110_l10>;
  578. qcom,firmware-name = "wcnss";
  579. /* GPIO inputs from wcnss */
  580. qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>;
  581. qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_4_in 1 0>;
  582. qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>;
  583. /* GPIO output to wcnss */
  584. qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>;
  585. };
  586. qcom,iris-fm {
  587. compatible = "qcom,iris_fm";
  588. };
  589. sound {
  590. compatible = "qcom,msm8x10-audio-codec";
  591. qcom,model = "msm8x10-snd-card";
  592. };
  593. qti,msm-pcm {
  594. compatible = "qti,msm-pcm-dsp";
  595. qti,msm-pcm-dsp-id = <0>;
  596. };
  597. qti,msm-pcm-low-latency {
  598. compatible = "qti,msm-pcm-dsp";
  599. qti,msm-pcm-dsp-id = <1>;
  600. qti,msm-pcm-low-latency;
  601. qti,latency-level = "ultra";
  602. };
  603. qcom,msm-pcm-routing {
  604. compatible = "qcom,msm-pcm-routing";
  605. };
  606. qcom,msm-pcm-lpa {
  607. compatible = "qcom,msm-pcm-lpa";
  608. };
  609. qcom,msm-compr-dsp {
  610. compatible = "qcom,msm-compr-dsp";
  611. };
  612. qcom,msm-compress-dsp {
  613. compatible = "qcom,msm-compress-dsp";
  614. };
  615. qcom,msm-voip-dsp {
  616. compatible = "qcom,msm-voip-dsp";
  617. };
  618. qcom,msm-pcm-voice {
  619. compatible = "qcom,msm-pcm-voice";
  620. };
  621. qcom,msm-stub-codec {
  622. compatible = "qcom,msm-stub-codec";
  623. };
  624. qcom,msm-dai-fe {
  625. compatible = "qcom,msm-dai-fe";
  626. };
  627. qcom,msm-pcm-afe {
  628. compatible = "qcom,msm-pcm-afe";
  629. };
  630. qcom,msm-dai-mi2s {
  631. compatible = "qcom,msm-dai-mi2s";
  632. qcom,msm-dai-q6-mi2s-prim {
  633. compatible = "qcom,msm-dai-q6-mi2s";
  634. qcom,msm-dai-q6-mi2s-dev-id = <0>;
  635. qcom,msm-mi2s-rx-lines = <0>;
  636. qcom,msm-mi2s-tx-lines = <3>;
  637. };
  638. qcom,msm-dai-q6-mi2s-sec {
  639. compatible = "qcom,msm-dai-q6-mi2s";
  640. qcom,msm-dai-q6-mi2s-dev-id = <1>;
  641. qcom,msm-mi2s-rx-lines = <3>;
  642. qcom,msm-mi2s-tx-lines = <0>;
  643. };
  644. };
  645. qcom,msm-dai-q6 {
  646. compatible = "qcom,msm-dai-q6";
  647. qcom,msm-dai-q6-bt-sco-rx {
  648. compatible = "qcom,msm-dai-q6-dev";
  649. qcom,msm-dai-q6-dev-id = <12288>;
  650. };
  651. qcom,msm-dai-q6-bt-sco-tx {
  652. compatible = "qcom,msm-dai-q6-dev";
  653. qcom,msm-dai-q6-dev-id = <12289>;
  654. };
  655. qcom,msm-dai-q6-int-fm-rx {
  656. compatible = "qcom,msm-dai-q6-dev";
  657. qcom,msm-dai-q6-dev-id = <12292>;
  658. };
  659. qcom,msm-dai-q6-int-fm-tx {
  660. compatible = "qcom,msm-dai-q6-dev";
  661. qcom,msm-dai-q6-dev-id = <12293>;
  662. };
  663. qcom,msm-dai-q6-be-afe-pcm-rx {
  664. compatible = "qcom,msm-dai-q6-dev";
  665. qcom,msm-dai-q6-dev-id = <224>;
  666. };
  667. qcom,msm-dai-q6-be-afe-pcm-tx {
  668. compatible = "qcom,msm-dai-q6-dev";
  669. qcom,msm-dai-q6-dev-id = <225>;
  670. };
  671. qcom,msm-dai-q6-afe-proxy-rx {
  672. compatible = "qcom,msm-dai-q6-dev";
  673. qcom,msm-dai-q6-dev-id = <241>;
  674. };
  675. qcom,msm-dai-q6-afe-proxy-tx {
  676. compatible = "qcom,msm-dai-q6-dev";
  677. qcom,msm-dai-q6-dev-id = <240>;
  678. };
  679. qcom,msm-dai-q6-incall-record-rx {
  680. compatible = "qcom,msm-dai-q6-dev";
  681. qcom,msm-dai-q6-dev-id = <32771>;
  682. };
  683. qcom,msm-dai-q6-incall-record-tx {
  684. compatible = "qcom,msm-dai-q6-dev";
  685. qcom,msm-dai-q6-dev-id = <32772>;
  686. };
  687. qcom,msm-dai-q6-incall-music-rx {
  688. compatible = "qcom,msm-dai-q6-dev";
  689. qcom,msm-dai-q6-dev-id = <32773>;
  690. };
  691. qcom,msm-dai-q6-incall-music-2-rx {
  692. compatible = "qcom,msm-dai-q6-dev";
  693. qcom,msm-dai-q6-dev-id = <32770>;
  694. };
  695. };
  696. qcom,msm-pcm-hostless {
  697. compatible = "qcom,msm-pcm-hostless";
  698. };
  699. qcom,wcnss-wlan@fb000000 {
  700. compatible = "qcom,wcnss_wlan";
  701. reg = <0xfb000000 0x280000>,
  702. <0xf9011008 0x04>;
  703. reg-names = "wcnss_mmio", "wcnss_fiq";
  704. interrupts = <0 145 0>, <0 146 0>;
  705. interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
  706. qcom,pronto-vddmx-supply = <&pm8110_l3>;
  707. qcom,pronto-vddcx-supply = <&pm8110_s1>;
  708. qcom,pronto-vddpx-supply = <&pm8110_l6>;
  709. qcom,iris-vddxo-supply = <&pm8110_l10>;
  710. qcom,iris-vddrfa-supply = <&pm8110_l5>;
  711. qcom,iris-vddpa-supply = <&pm8110_l16>;
  712. qcom,iris-vdddig-supply = <&pm8110_l5>;
  713. gpios = <&msmgpio 23 0>, <&msmgpio 24 0>, <&msmgpio 25 0>, <&msmgpio 26 0>, <&msmgpio 27 0>;
  714. qcom,has-pronto-hw;
  715. qcom,wlan-rx-buff-count = <256>;
  716. qcom,has-autodetect-xo;
  717. };
  718. qcom,mss@fc880000 {
  719. compatible = "qcom,pil-q6v5-mss";
  720. reg = <0xfc880000 0x100>,
  721. <0xfd485000 0x400>,
  722. <0xfc820000 0x020>,
  723. <0xfc401680 0x004>,
  724. <0xfd485194 0x4>;
  725. reg-names = "qdsp6_base", "halt_base", "rmb_base",
  726. "restart_reg", "cxrail_bhs_reg";
  727. interrupts = <0 24 1>;
  728. vdd_cx-supply = <&pm8110_s1_corner>;
  729. vdd_mx-supply = <&pm8110_l3>;
  730. vdd_pll-supply = <&pm8110_l10>;
  731. qcom,vdd_pll = <1800000>;
  732. qcom,is-loadable;
  733. qcom,firmware-name = "mba";
  734. qcom,pil-self-auth;
  735. /* GPIO inputs from mss */
  736. qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
  737. qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
  738. qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
  739. qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
  740. /* GPIO output to mss */
  741. qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
  742. };
  743. qcom,lpass@fe200000 {
  744. compatible = "qcom,pil-q6v5-lpass";
  745. reg = <0xfe200000 0x00100>,
  746. <0xfd485100 0x00010>,
  747. <0xfc4016c0 0x00004>;
  748. reg-names = "qdsp6_base", "halt_base", "restart_reg";
  749. interrupts = <0 162 1>;
  750. vdd_cx-supply = <&pm8110_s1_corner>;
  751. qcom,firmware-name = "adsp";
  752. /* GPIO inputs from lpass */
  753. qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
  754. qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
  755. qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
  756. /* GPIO output to lpass */
  757. qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
  758. };
  759. tsens: tsens@fc4a8000 {
  760. compatible = "qcom,msm-tsens";
  761. reg = <0xfc4a8000 0x2000>,
  762. <0xfc4bc000 0x1000>;
  763. reg-names = "tsens_physical", "tsens_eeprom_physical";
  764. interrupts = <0 184 0>;
  765. qcom,sensors = <2>;
  766. qcom,slope = <2901 2846>;
  767. qcom,calib-mode = "fuse_map3";
  768. qcom,sensor-id = <0 5>;
  769. };
  770. qcom,msm-thermal {
  771. compatible = "qcom,msm-thermal";
  772. qcom,sensor-id = <5>;
  773. qcom,poll-ms = <250>;
  774. qcom,limit-temp = <60>;
  775. qcom,temp-hysteresis = <10>;
  776. qcom,freq-step = <2>;
  777. qcom,freq-control-mask = <0xf>;
  778. qcom,core-limit-temp = <80>;
  779. qcom,core-temp-hysteresis = <10>;
  780. qcom,core-control-mask = <0xe>;
  781. qcom,hotplug-temp = <110>;
  782. qcom,hotplug-temp-hysteresis = <20>;
  783. qcom,cpu-sensors = "tsens_tz_sensor5", "tsens_tz_sensor5",
  784. "tsens_tz_sensor5", "tsens_tz_sensor5";
  785. qcom,default-temp = <80>;
  786. qcom,efuse-data = <0xfc4b8000 0x1000 23 30 0x3>;
  787. qcom,efuse-temperature-map = <0x1 70>;
  788. qcom,vdd-restriction-temp = <5>;
  789. qcom,vdd-restriction-temp-hysteresis = <10>;
  790. vdd-dig-supply = <&pm8110_s1_floor_corner>;
  791. qcom,vdd-dig-rstr{
  792. qcom,vdd-rstr-reg = "vdd-dig";
  793. qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */
  794. qcom,min-level = <1>; /* No Request */
  795. };
  796. qcom,vdd-apps-rstr{
  797. qcom,vdd-rstr-reg = "vdd-apps";
  798. qcom,levels = <600000 787200 998400>;
  799. qcom,freq-req;
  800. };
  801. };
  802. qcom,ipc-spinlock@fd484000 {
  803. compatible = "qcom,ipc-spinlock-sfpb";
  804. reg = <0xfd484000 0x400>;
  805. qcom,num-locks = <8>;
  806. };
  807. qcom,bam_dmux@fc834000 {
  808. compatible = "qcom,bam_dmux";
  809. reg = <0xfc834000 0x7000>;
  810. interrupts = <0 29 1>;
  811. };
  812. qcom,qseecom@da00000 {
  813. compatible = "qcom,qseecom";
  814. reg = <0xda00000 0x100000>;
  815. reg-names = "secapp-region";
  816. qcom,disk-encrypt-pipe-pair = <2>;
  817. qcom,hlos-ce-hw-instance = <0>;
  818. qcom,qsee-ce-hw-instance = <0>;
  819. qcom,support-bus-scaling;
  820. qcom,msm-bus,name = "qseecom-noc";
  821. qcom,msm-bus,num-cases = <4>;
  822. qcom,msm-bus,active-only = <0>;
  823. qcom,msm-bus,num-paths = <1>;
  824. qcom,msm-bus,vectors-KBps =
  825. <55 512 0 0>,
  826. <55 512 0 0>,
  827. <55 512 120000 1200000>,
  828. <55 512 393600 3936000>;
  829. };
  830. qcom,msm-rng@f9bff000 {
  831. compatible = "qcom,msm-rng";
  832. reg = <0xf9bff000 0x200>;
  833. qcom,msm-rng-iface-clk;
  834. qcom,msm-bus,name = "msm-rng-noc";
  835. qcom,msm-bus,num-cases = <2>;
  836. qcom,msm-bus,num-paths = <1>;
  837. qcom,msm-bus,vectors-KBps =
  838. <54 618 0 0>,
  839. <54 618 0 800>;
  840. };
  841. qcom,msm-rtb {
  842. compatible = "qcom,msm-rtb";
  843. qcom,memory-reservation-type = "EBI1";
  844. qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */
  845. };
  846. jtag_fuse: jtagfuse@fc4be024 {
  847. compatible = "qcom,jtag-fuse";
  848. reg = <0xfc4be024 0x8>;
  849. reg-names = "fuse-base";
  850. };
  851. jtag_mm0: jtagmm@fc34c000 {
  852. compatible = "qcom,jtag-mm";
  853. reg = <0xfc34c000 0x1000>,
  854. <0xfc340000 0x1000>;
  855. reg-names = "etm-base","debug-base";
  856. };
  857. jtag_mm1: jtagmm@fc34d000 {
  858. compatible = "qcom,jtag-mm";
  859. reg = <0xfc34d000 0x1000>,
  860. <0xfc342000 0x1000>;
  861. reg-names = "etm-base","debug-base";
  862. };
  863. jtag_mm2: jtagmm@fc34e000 {
  864. compatible = "qcom,jtag-mm";
  865. reg = <0xfc34e000 0x1000>,
  866. <0xfc344000 0x1000>;
  867. reg-names = "etm-base","debug-base";
  868. };
  869. jtag_mm3: jtagmm@fc34f000 {
  870. compatible = "qcom,jtag-mm";
  871. reg = <0xfc34f000 0x1000>,
  872. <0xfc346000 0x1000>;
  873. reg-names = "etm-base","debug-base";
  874. };
  875. qcom,tz-log@fe805720 {
  876. compatible = "qcom,tz-log";
  877. reg = <0x0fe805720 0x1000>;
  878. };
  879. qcom,qcrypto@fd404000 {
  880. compatible = "qcom,qcrypto";
  881. reg = <0xfd400000 0x20000>,
  882. <0xfd404000 0x8000>;
  883. reg-names = "crypto-base","crypto-bam-base";
  884. interrupts = <0 207 0>;
  885. qcom,bam-pipe-pair = <2>;
  886. qcom,ce-hw-instance = <1>;
  887. qcom,ce-device = <0>;
  888. qcom,ce-hw-shared;
  889. qcom,msm-bus,name = "qcrypto-noc";
  890. qcom,msm-bus,num-cases = <2>;
  891. qcom,msm-bus,active-only = <0>;
  892. qcom,msm-bus,num-paths = <1>;
  893. qcom,msm-bus,vectors-KBps =
  894. <55 512 0 0>,
  895. <55 512 393600 3936000>;
  896. };
  897. qcom,qcedev@fd400000 {
  898. compatible = "qcom,qcedev";
  899. reg = <0xfd400000 0x20000>,
  900. <0xfd404000 0x8000>;
  901. reg-names = "crypto-base","crypto-bam-base";
  902. interrupts = <0 207 0>;
  903. qcom,bam-pipe-pair = <1>;
  904. qcom,ce-hw-instance = <1>;
  905. qcom,ce-device = <0>;
  906. qcom,ce-hw-shared;
  907. qcom,msm-bus,name = "qcedev-noc";
  908. qcom,msm-bus,num-cases = <2>;
  909. qcom,msm-bus,active-only = <0>;
  910. qcom,msm-bus,num-paths = <1>;
  911. qcom,msm-bus,vectors-KBps =
  912. <55 512 0 0>,
  913. <55 512 393600 3936000>;
  914. };
  915. cpu-pmu {
  916. compatible = "arm,cortex-a7-pmu";
  917. qcom,irq-is-percpu;
  918. interrupts = <1 7 0xf00>;
  919. };
  920. bimc_sharedmem {
  921. compatible = "qcom,sharedmem-uio";
  922. reg = <0xfc380000 0x00100000>;
  923. reg-names = "bimc";
  924. };
  925. };
  926. &gdsc_vfe {
  927. qcom,clock-names = "core_clk", "iface_clk", "bus_clk";
  928. status = "ok";
  929. };
  930. &gdsc_oxili_cx {
  931. qcom,clock-names = "core_clk", "iface_clk", "mem_clk";
  932. status = "ok";
  933. };
  934. &lpass_iommu {
  935. status = "ok";
  936. };
  937. &copss_iommu {
  938. status = "ok";
  939. };
  940. &mdpe_iommu {
  941. status = "ok";
  942. };
  943. &mdps_iommu {
  944. status = "ok";
  945. };
  946. &gfx_iommu {
  947. status = "ok";
  948. };
  949. &vfe_iommu {
  950. status = "ok";
  951. };
  952. /include/ "msm8610-iommu-domains.dtsi"
  953. /include/ "msm-pm8110-rpm-regulator.dtsi"
  954. /include/ "msm-pm8110.dtsi"
  955. /include/ "msm8610-regulator.dtsi"
  956. &pm8110_vadc {
  957. chan@0 {
  958. label = "usb_in";
  959. reg = <0>;
  960. qcom,decimation = <0>;
  961. qcom,pre-div-channel-scaling = <4>;
  962. qcom,calibration-type = "absolute";
  963. qcom,scale-function = <0>;
  964. qcom,hw-settle-time = <0>;
  965. qcom,fast-avg-setup = <0>;
  966. };
  967. chan@2 {
  968. label = "vchg_sns";
  969. reg = <2>;
  970. qcom,decimation = <0>;
  971. qcom,pre-div-channel-scaling = <5>;
  972. qcom,calibration-type = "absolute";
  973. qcom,scale-function = <0>;
  974. qcom,hw-settle-time = <0>;
  975. qcom,fast-avg-setup = <0>;
  976. };
  977. chan@5 {
  978. label = "vcoin";
  979. reg = <5>;
  980. qcom,decimation = <0>;
  981. qcom,pre-div-channel-scaling = <1>;
  982. qcom,calibration-type = "absolute";
  983. qcom,scale-function = <0>;
  984. qcom,hw-settle-time = <0>;
  985. qcom,fast-avg-setup = <0>;
  986. };
  987. chan@6 {
  988. label = "vbat_sns";
  989. reg = <6>;
  990. qcom,decimation = <0>;
  991. qcom,pre-div-channel-scaling = <1>;
  992. qcom,calibration-type = "absolute";
  993. qcom,scale-function = <0>;
  994. qcom,hw-settle-time = <0>;
  995. qcom,fast-avg-setup = <0>;
  996. };
  997. chan@7 {
  998. label = "vph_pwr";
  999. reg = <7>;
  1000. qcom,decimation = <0>;
  1001. qcom,pre-div-channel-scaling = <1>;
  1002. qcom,calibration-type = "absolute";
  1003. qcom,scale-function = <0>;
  1004. qcom,hw-settle-time = <0>;
  1005. qcom,fast-avg-setup = <0>;
  1006. };
  1007. chan@30 {
  1008. label = "batt_therm";
  1009. reg = <0x30>;
  1010. qcom,decimation = <0>;
  1011. qcom,pre-div-channel-scaling = <0>;
  1012. qcom,calibration-type = "ratiometric";
  1013. qcom,scale-function = <1>;
  1014. qcom,hw-settle-time = <2>;
  1015. qcom,fast-avg-setup = <0>;
  1016. };
  1017. chan@31 {
  1018. label = "batt_id";
  1019. reg = <0x31>;
  1020. qcom,decimation = <0>;
  1021. qcom,pre-div-channel-scaling = <0>;
  1022. qcom,calibration-type = "ratiometric";
  1023. qcom,scale-function = <0>;
  1024. qcom,hw-settle-time = <2>;
  1025. qcom,fast-avg-setup = <0>;
  1026. };
  1027. chan@b2 {
  1028. label = "xo_therm_pu2";
  1029. reg = <0xb2>;
  1030. qcom,decimation = <0>;
  1031. qcom,pre-div-channel-scaling = <0>;
  1032. qcom,calibration-type = "ratiometric";
  1033. qcom,scale-function = <4>;
  1034. qcom,hw-settle-time = <2>;
  1035. qcom,fast-avg-setup = <0>;
  1036. };
  1037. chan@13 {
  1038. label = "pa_therm0";
  1039. reg = <0x13>;
  1040. qcom,decimation = <0>;
  1041. qcom,pre-div-channel-scaling = <0>;
  1042. qcom,calibration-type = "ratiometric";
  1043. qcom,scale-function = <2>;
  1044. qcom,hw-settle-time = <2>;
  1045. qcom,fast-avg-setup = <0>;
  1046. };
  1047. };
  1048. &pm8110_adc_tm {
  1049. /* Channel Node */
  1050. chan@30 {
  1051. label = "batt_therm";
  1052. reg = <0x30>;
  1053. qcom,decimation = <0>;
  1054. qcom,pre-div-channel-scaling = <0>;
  1055. qcom,calibration-type = "ratiometric";
  1056. qcom,scale-function = <1>;
  1057. qcom,hw-settle-time = <2>;
  1058. qcom,fast-avg-setup = <3>;
  1059. qcom,btm-channel-number = <0x48>;
  1060. qcom,meas-interval-timer-idx = <2>;
  1061. };
  1062. chan@8 {
  1063. label = "die_temp";
  1064. reg = <8>;
  1065. qcom,decimation = <0>;
  1066. qcom,pre-div-channel-scaling = <0>;
  1067. qcom,calibration-type = "absolute";
  1068. qcom,scale-function = <3>;
  1069. qcom,hw-settle-time = <0>;
  1070. qcom,fast-avg-setup = <3>;
  1071. qcom,btm-channel-number = <0x68>;
  1072. };
  1073. chan@6 {
  1074. label = "vbat_sns";
  1075. reg = <6>;
  1076. qcom,decimation = <0>;
  1077. qcom,pre-div-channel-scaling = <1>;
  1078. qcom,calibration-type = "absolute";
  1079. qcom,scale-function = <0>;
  1080. qcom,hw-settle-time = <0>;
  1081. qcom,fast-avg-setup = <3>;
  1082. qcom,btm-channel-number = <0x70>;
  1083. };
  1084. chan@13 {
  1085. label = "pa_therm0";
  1086. reg = <0x13>;
  1087. qcom,decimation = <0>;
  1088. qcom,pre-div-channel-scaling = <0>;
  1089. qcom,calibration-type = "ratiometric";
  1090. qcom,scale-function = <2>;
  1091. qcom,hw-settle-time = <2>;
  1092. qcom,fast-avg-setup = <0>;
  1093. qcom,btm-channel-number = <0x78>;
  1094. qcom,thermal-node;
  1095. };
  1096. };