msm8226.dtsi 40 KB

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  1. /* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. /include/ "skeleton.dtsi"
  13. / {
  14. model = "Qualcomm MSM 8226";
  15. compatible = "qcom,msm8226";
  16. interrupt-parent = <&intc>;
  17. aliases {
  18. spi0 = &spi_0;
  19. sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  20. sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  21. sdhc3 = &sdhc_3; /* SDC3 SDIO slot */
  22. };
  23. firmware: firmware {
  24. android {
  25. compatible = "android,firmware";
  26. fstab {
  27. compatible = "android,fstab";
  28. system {
  29. compatible = "android,system";
  30. dev = "/dev/block/platform/msm_sdcc.1/by-name/system";
  31. type = "ext4";
  32. mnt_flags = "ro,barrier=1,discard";
  33. fsmgr_flags = "wait";
  34. status = "ok";
  35. };
  36. };
  37. };
  38. };
  39. memory {
  40. secure_mem: secure_region {
  41. linux,contiguous-region;
  42. reg = <0 0x6D00000>;
  43. label = "secure_mem";
  44. };
  45. adsp_mem: adsp_region {
  46. linux,contiguous-region;
  47. linux,memory-limit = <0x0>;
  48. reg = <0 0x2a00000>;
  49. label = "adsp_mem";
  50. };
  51. qsecom_mem: qsecom_region {
  52. linux,contiguous-region;
  53. reg = <0 0xd00000>;
  54. label = "qsecom_mem";
  55. };
  56. };
  57. soc: soc { };
  58. };
  59. /include/ "msm8226-ion.dtsi"
  60. /include/ "msm8226-camera.dtsi"
  61. /include/ "msm-gdsc.dtsi"
  62. /include/ "msm8226-iommu.dtsi"
  63. /include/ "msm8226-smp2p.dtsi"
  64. /include/ "msm8226-gpu.dtsi"
  65. /include/ "msm8226-bus.dtsi"
  66. /include/ "msm8226-mdss.dtsi"
  67. /include/ "msm8226-coresight.dtsi"
  68. /include/ "msm8226-iommu-domains.dtsi"
  69. /include/ "msm-rdbg.dtsi"
  70. &soc {
  71. #address-cells = <1>;
  72. #size-cells = <1>;
  73. ranges;
  74. intc: interrupt-controller@f9000000 {
  75. compatible = "qcom,msm-qgic2";
  76. interrupt-controller;
  77. #interrupt-cells = <3>;
  78. reg = <0xF9000000 0x1000>,
  79. <0xF9002000 0x1000>;
  80. };
  81. msmgpio: gpio@fd510000 {
  82. compatible = "qcom,msm-gpio";
  83. interrupt-controller;
  84. #interrupt-cells = <2>;
  85. reg = <0xfd510000 0x4000>;
  86. gpio-controller;
  87. #gpio-cells = <2>;
  88. ngpio = <117>;
  89. interrupts = <0 208 0>;
  90. qcom,direct-connect-irqs = <8>;
  91. };
  92. qcom,mpm2-sleep-counter@fc4a3000 {
  93. compatible = "qcom,mpm2-sleep-counter";
  94. reg = <0xfc4a3000 0x1000>;
  95. clock-frequency = <32768>;
  96. };
  97. timer {
  98. compatible = "arm,armv7-timer";
  99. interrupts = <1 2 0 1 3 0>;
  100. clock-frequency = <19200000>;
  101. };
  102. timer@f9020000 {
  103. #address-cells = <1>;
  104. #size-cells = <1>;
  105. ranges;
  106. compatible = "arm,armv7-timer-mem";
  107. reg = <0xf9020000 0x1000>;
  108. clock-frequency = <19200000>;
  109. frame@f9021000 {
  110. frame-number = <0>;
  111. interrupts = <0 8 0x4>,
  112. <0 7 0x4>;
  113. reg = <0xf9021000 0x1000>,
  114. <0xf9022000 0x1000>;
  115. };
  116. frame@f9023000 {
  117. frame-number = <1>;
  118. interrupts = <0 9 0x4>;
  119. reg = <0xf9023000 0x1000>;
  120. status = "disabled";
  121. };
  122. frame@f9024000 {
  123. frame-number = <2>;
  124. interrupts = <0 10 0x4>;
  125. reg = <0xf9024000 0x1000>;
  126. status = "disabled";
  127. };
  128. frame@f9025000 {
  129. frame-number = <3>;
  130. interrupts = <0 11 0x4>;
  131. reg = <0xf9025000 0x1000>;
  132. status = "disabled";
  133. };
  134. frame@f9026000 {
  135. frame-number = <4>;
  136. interrupts = <0 12 0x4>;
  137. reg = <0xf9026000 0x1000>;
  138. status = "disabled";
  139. };
  140. frame@f9027000 {
  141. frame-number = <5>;
  142. interrupts = <0 13 0x4>;
  143. reg = <0xf9027000 0x1000>;
  144. status = "disabled";
  145. };
  146. frame@f9028000 {
  147. frame-number = <6>;
  148. interrupts = <0 14 0x4>;
  149. reg = <0xf9028000 0x1000>;
  150. status = "disabled";
  151. };
  152. };
  153. qcom,vidc@fdc00000 {
  154. compatible = "qcom,msm-vidc";
  155. reg = <0xfdc00000 0xff000>;
  156. interrupts = <0 44 0>;
  157. vdd-supply = <&gdsc_venus>;
  158. qcom,load-freq-tbl = <352800 160000000>,
  159. <244800 133330000>,
  160. <108000 66700000>;
  161. qcom,hfi = "venus";
  162. qcom,bus-ports = <1>;
  163. qcom,reg-presets = <0xE0024 0x0>,
  164. <0x80124 0x3>,
  165. <0xE0020 0x5555556>,
  166. <0x800B0 0x10101001>,
  167. <0x800B4 0x00101010>,
  168. <0x800C0 0x1010100f>,
  169. <0x800C4 0x00101010>,
  170. <0x800D0 0x00000010>,
  171. <0x800D4 0x00000010>,
  172. <0x800D8 0x00000707>;
  173. qcom,enc-ddr-ab-ib = <0 0>,
  174. <129000 142000>,
  175. <384000 422000>,
  176. <866000 953000>;
  177. qcom,dec-ddr-ab-ib = <0 0>,
  178. <103000 134000>,
  179. <268000 348000>,
  180. <505000 657000>;
  181. qcom,buffer-type-tz-usage-table = <0x1 0x1>,
  182. <0x6 0x2>,
  183. <0x7C0 0x3>;
  184. qcom,max-hw-load = <352800>; /* 720p @ 30 + 1080p @ 30 */
  185. qcom,vidc-iommu-domains {
  186. qcom,domain-ns {
  187. qcom,vidc-domain-phandle = <&venus_domain_ns>;
  188. qcom,vidc-partition-buffer-types = <0x7ff>,
  189. <0x800>;
  190. };
  191. qcom,domain-cp {
  192. qcom,vidc-domain-phandle = <&venus_domain_cp>;
  193. qcom,vidc-partition-buffer-types = <0x6>,
  194. <0x7c1>;
  195. };
  196. };
  197. };
  198. qcom,vidc {
  199. compatible = "qcom,msm-vidc";
  200. qcom,hfi = "q6";
  201. qcom,max-hw-load = <108000>; /* 720p @ 30 * 1 */
  202. };
  203. qcom,wfd {
  204. compatible = "qcom,msm-wfd";
  205. };
  206. serial@f991f000 {
  207. compatible = "qcom,msm-lsuart-v14";
  208. reg = <0xf991f000 0x1000>;
  209. interrupts = <0 109 0>;
  210. status = "disabled";
  211. qcom,msm-bus,name = "blsp1_uart2";
  212. qcom,msm-bus,num-cases = <2>;
  213. qcom,msm-bus,num-paths = <1>;
  214. qcom,msm-bus,vectors-KBps =
  215. <86 512 0 0>,
  216. <86 512 500 800>;
  217. };
  218. qcom,msm-imem@fe805000 {
  219. compatible = "qcom,msm-imem";
  220. reg = <0xfe805000 0x1000>; /* Address and size of IMEM */
  221. };
  222. qcom,sps@f9984000 {
  223. compatible = "qcom,msm_sps";
  224. reg = <0xf9984000 0x15000>,
  225. <0xf9999000 0xb000>;
  226. interrupts = <0 94 0>;
  227. };
  228. qcom,usbbam@f9a44000 {
  229. compatible = "qcom,usb-bam-msm";
  230. reg = <0xf9a44000 0x11000>;
  231. reg-names = "hsusb";
  232. interrupts = <0 135 0>;
  233. interrupt-names = "hsusb";
  234. qcom,usb-bam-num-pipes = <16>;
  235. qcom,usb-bam-fifo-baseaddr = <0xfe803000>;
  236. qcom,ignore-core-reset-ack;
  237. qcom,disable-clk-gating;
  238. qcom,pipe0 {
  239. label = "hsusb-qdss-in-0";
  240. qcom,usb-bam-mem-type = <3>;
  241. qcom,bam-type = <1>;
  242. qcom,dir = <1>;
  243. qcom,pipe-num = <0>;
  244. qcom,peer-bam = <1>;
  245. qcom,src-bam-physical-address = <0xfc37c000>;
  246. qcom,src-bam-pipe-index = <0>;
  247. qcom,dst-bam-physical-address = <0xf9a44000>;
  248. qcom,dst-bam-pipe-index = <2>;
  249. qcom,data-fifo-offset = <0x0>;
  250. qcom,data-fifo-size = <0x600>;
  251. qcom,descriptor-fifo-offset = <0x600>;
  252. qcom,descriptor-fifo-size = <0x200>;
  253. };
  254. };
  255. usb_otg: usb@f9a55000 {
  256. compatible = "qcom,hsusb-otg";
  257. reg = <0xf9a55000 0x400>;
  258. interrupts = <0 134 0>, <0 140 0>;
  259. interrupt-names = "core_irq", "async_irq";
  260. hsusb_vdd_dig-supply = <&pm8226_s1_corner>;
  261. HSUSB_1p8-supply = <&pm8226_l10>;
  262. HSUSB_3p3-supply = <&pm8226_l20>;
  263. qcom,vdd-voltage-level = <1 5 7>;
  264. qcom,hsusb-otg-phy-init-seq =
  265. <0x44 0x80 0x68 0x81 0x24 0x82 0x13 0x83 0xffffffff>;
  266. qcom,hsusb-otg-phy-type = <2>;
  267. qcom,hsusb-otg-mode = <1>;
  268. qcom,hsusb-otg-otg-control = <2>;
  269. qcom,hsusb-otg-disable-reset;
  270. qcom,dp-manual-pullup;
  271. qcom,usbin-vadc = <&pm8226_vadc>;
  272. qcom,msm-bus,name = "usb";
  273. qcom,msm-bus,num-cases = <3>;
  274. qcom,msm-bus,num-paths = <1>;
  275. qcom,msm-bus,vectors-KBps =
  276. <87 512 0 0>,
  277. <87 512 60000 960000>,
  278. <87 512 6000 6000>;
  279. };
  280. android_usb: android_usb@fe8050c8 {
  281. compatible = "qcom,android-usb";
  282. reg = <0xfe8050c8 0xc8>;
  283. qcom,android-usb-swfi-latency = <1>;
  284. qcom,streaming-func = "rndis";
  285. qcom,android-usb-uicc-nluns = <1>;
  286. };
  287. smsc_hub: hsic_hub {
  288. status = "disabled";
  289. compatible = "qcom,hsic-smsc-hub";
  290. smsc,model-id = <0>;
  291. #address-cells = <1>;
  292. #size-cells = <1>;
  293. ranges;
  294. hsic_host: hsic@f9a00000 {
  295. compatible = "qcom,hsic-host";
  296. reg = <0xf9a00000 0x400>;
  297. #address-cells = <0>;
  298. interrupt-parent = <&hsic_host>;
  299. interrupts = <0 1 2>;
  300. #interrupt-cells = <1>;
  301. interrupt-map-mask = <0xffffffff>;
  302. interrupt-map = <0 &intc 0 136 0
  303. 1 &intc 0 148 0
  304. 2 &msmgpio 115 0x8>;
  305. interrupt-names = "core_irq", "async_irq", "wakeup";
  306. hsic_vdd_dig-supply = <&pm8226_s1_corner>;
  307. HSIC_GDSC-supply = <&gdsc_usb_hsic>;
  308. hsic,strobe-gpio = <&msmgpio 115 0x00>;
  309. hsic,data-gpio = <&msmgpio 116 0x00>;
  310. hsic,ignore-cal-pad-config;
  311. hsic,strobe-pad-offset = <0x2050>;
  312. hsic,data-pad-offset = <0x2054>;
  313. qcom,phy-susp-sof-workaround;
  314. hsic,vdd-voltage-level = <1 5 7>;
  315. qcom,msm-bus,name = "hsic";
  316. qcom,msm-bus,num-cases = <2>;
  317. qcom,msm-bus,num-paths = <1>;
  318. qcom,msm-bus,vectors-KBps =
  319. <85 512 0 0>,
  320. <85 512 40000 160000>;
  321. };
  322. };
  323. wcd9xxx_intc: wcd9xxx-irq {
  324. compatible = "qcom,wcd9xxx-irq";
  325. interrupt-controller;
  326. #interrupt-cells = <1>;
  327. interrupt-parent = <&msmgpio>;
  328. interrupts = <68 0>;
  329. interrupt-names = "cdc-int";
  330. };
  331. slim_msm: slim@fe12f000 {
  332. cell-index = <1>;
  333. compatible = "qcom,slim-ngd";
  334. reg = <0xfe12f000 0x35000>,
  335. <0xfe104000 0x20000>;
  336. reg-names = "slimbus_physical", "slimbus_bam_physical";
  337. interrupts = <0 163 0>, <0 164 0>;
  338. interrupt-names = "slimbus_irq", "slimbus_bam_irq";
  339. tapan_codec {
  340. compatible = "qcom,tapan-slim-pgd";
  341. elemental-addr = [00 01 E0 00 17 02];
  342. interrupt-parent = <&wcd9xxx_intc>;
  343. interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
  344. 17 18 19 20 21 22 23 24 25 26 27 28>;
  345. qcom,cdc-reset-gpio = <&msmgpio 72 0>;
  346. cdc-vdd-buck-supply = <&pm8226_s4>;
  347. qcom,cdc-vdd-buck-voltage = <1800000 2150000>;
  348. qcom,cdc-vdd-buck-current = <650000>;
  349. cdc-vdd-h-supply = <&pm8226_l6>;
  350. qcom,cdc-vdd-h-voltage = <1800000 1800000>;
  351. qcom,cdc-vdd-h-current = <25000>;
  352. cdc-vdd-px-supply = <&pm8226_l6>;
  353. qcom,cdc-vdd-px-voltage = <1800000 1800000>;
  354. qcom,cdc-vdd-px-current = <25000>;
  355. cdc-vdd-cx-supply = <&pm8226_l4>;
  356. qcom,cdc-vdd-cx-voltage = <1200000 1200000>;
  357. qcom,cdc-vdd-cx-current = <2000>;
  358. cdc-vdd-buckhelper-supply = <&pm8226_l25>;
  359. qcom,cdc-vdd-buckhelper-voltage = <1775000 2125000>;
  360. qcom,cdc-vdd-buckhelper-current = <10000>;
  361. qcom,cdc-static-supplies = "cdc-vdd-h",
  362. "cdc-vdd-px",
  363. "cdc-vdd-cx";
  364. qcom,cdc-cp-supplies = "cdc-vdd-buck",
  365. "cdc-vdd-buckhelper";
  366. qcom,cdc-micbias-ldoh-v = <0x3>;
  367. qcom,cdc-micbias-cfilt1-mv = <1800>;
  368. qcom,cdc-micbias-cfilt2-mv = <2700>;
  369. qcom,cdc-micbias-cfilt3-mv = <1800>;
  370. qcom,cdc-micbias1-cfilt-sel = <0x0>;
  371. qcom,cdc-micbias2-cfilt-sel = <0x1>;
  372. qcom,cdc-micbias3-cfilt-sel = <0x2>;
  373. qcom,cdc-mclk-clk-rate = <9600000>;
  374. qcom,cdc-slim-ifd = "tapan-slim-ifd";
  375. qcom,cdc-slim-ifd-elemental-addr = [00 00 E0 00 17 02];
  376. };
  377. };
  378. qcom,msm-adsp-loader {
  379. compatible = "qcom,adsp-loader";
  380. qcom,adsp-state = <0>;
  381. };
  382. sound {
  383. compatible = "qcom,msm8226-audio-tapan";
  384. qcom,model = "msm8226-tapan-snd-card";
  385. qcom,tapan-mclk-clk-freq = <9600000>;
  386. qcom,prim-auxpcm-gpio-clk = <&msmgpio 63 0>;
  387. qcom,prim-auxpcm-gpio-sync = <&msmgpio 64 0>;
  388. qcom,prim-auxpcm-gpio-din = <&msmgpio 65 0>;
  389. qcom,prim-auxpcm-gpio-dout = <&msmgpio 66 0>;
  390. qcom,prim-auxpcm-gpio-set = "prim-gpio-prim";
  391. };
  392. sound-9302 {
  393. compatible = "qcom,msm8226-audio-tapan";
  394. qcom,model = "msm8226-tapan9302-snd-card";
  395. qcom,tapan-mclk-clk-freq = <9600000>;
  396. qcom,prim-auxpcm-gpio-clk = <&msmgpio 63 0>;
  397. qcom,prim-auxpcm-gpio-sync = <&msmgpio 64 0>;
  398. qcom,prim-auxpcm-gpio-din = <&msmgpio 65 0>;
  399. qcom,prim-auxpcm-gpio-dout = <&msmgpio 66 0>;
  400. qcom,prim-auxpcm-gpio-set = "prim-gpio-prim";
  401. qcom,tapan-codec-9302;
  402. };
  403. qti,msm-pcm {
  404. compatible = "qti,msm-pcm-dsp";
  405. qti,msm-pcm-dsp-id = <0>;
  406. };
  407. qcom,msm-pcm-routing {
  408. compatible = "qcom,msm-pcm-routing";
  409. };
  410. qti,msm-pcm-low-latency {
  411. compatible = "qti,msm-pcm-dsp";
  412. qti,msm-pcm-dsp-id = <1>;
  413. qti,msm-pcm-low-latency;
  414. qti,latency-level = "regular";
  415. };
  416. qcom,msm-pcm-lpa {
  417. compatible = "qcom,msm-pcm-lpa";
  418. };
  419. qcom,msm-compr-dsp {
  420. compatible = "qcom,msm-compr-dsp";
  421. };
  422. qcom,msm-compress-dsp {
  423. compatible = "qcom,msm-compress-dsp";
  424. };
  425. qcom,msm-voip-dsp {
  426. compatible = "qcom,msm-voip-dsp";
  427. };
  428. qcom,msm-pcm-voice {
  429. compatible = "qcom,msm-pcm-voice";
  430. };
  431. qcom,msm-stub-codec {
  432. compatible = "qcom,msm-stub-codec";
  433. };
  434. qcom,msm-dai-fe {
  435. compatible = "qcom,msm-dai-fe";
  436. };
  437. qcom,msm-pcm-afe {
  438. compatible = "qcom,msm-pcm-afe";
  439. };
  440. qcom,msm-dai-q6-hdmi {
  441. compatible = "qcom,msm-dai-q6-hdmi";
  442. qcom,msm-dai-q6-dev-id = <8>;
  443. };
  444. qcom,msm-lsm-client {
  445. compatible = "qcom,msm-lsm-client";
  446. };
  447. qti,msm-pcm-loopback {
  448. compatible = "qti,msm-pcm-loopback";
  449. };
  450. qcom,msm-voice-svc {
  451. compatible = "qcom,msm-voice-svc";
  452. };
  453. qcom,msm-dai-q6 {
  454. compatible = "qcom,msm-dai-q6";
  455. qcom,msm-dai-q6-sb-0-rx {
  456. compatible = "qcom,msm-dai-q6-dev";
  457. qcom,msm-dai-q6-dev-id = <16384>;
  458. };
  459. qcom,msm-dai-q6-sb-0-tx {
  460. compatible = "qcom,msm-dai-q6-dev";
  461. qcom,msm-dai-q6-dev-id = <16385>;
  462. };
  463. qcom,msm-dai-q6-sb-1-rx {
  464. compatible = "qcom,msm-dai-q6-dev";
  465. qcom,msm-dai-q6-dev-id = <16386>;
  466. };
  467. qcom,msm-dai-q6-sb-1-tx {
  468. compatible = "qcom,msm-dai-q6-dev";
  469. qcom,msm-dai-q6-dev-id = <16387>;
  470. };
  471. qcom,msm-dai-q6-sb-3-rx {
  472. compatible = "qcom,msm-dai-q6-dev";
  473. qcom,msm-dai-q6-dev-id = <16390>;
  474. };
  475. qcom,msm-dai-q6-sb-3-tx {
  476. compatible = "qcom,msm-dai-q6-dev";
  477. qcom,msm-dai-q6-dev-id = <16391>;
  478. };
  479. qcom,msm-dai-q6-sb-4-rx {
  480. compatible = "qcom,msm-dai-q6-dev";
  481. qcom,msm-dai-q6-dev-id = <16392>;
  482. };
  483. qcom,msm-dai-q6-sb-4-tx {
  484. compatible = "qcom,msm-dai-q6-dev";
  485. qcom,msm-dai-q6-dev-id = <16393>;
  486. };
  487. qcom,msm-dai-q6-sb-5-tx {
  488. compatible = "qcom,msm-dai-q6-dev";
  489. qcom,msm-dai-q6-dev-id = <16395>;
  490. };
  491. qcom,msm-dai-q6-bt-sco-rx {
  492. compatible = "qcom,msm-dai-q6-dev";
  493. qcom,msm-dai-q6-dev-id = <12288>;
  494. };
  495. qcom,msm-dai-q6-bt-sco-tx {
  496. compatible = "qcom,msm-dai-q6-dev";
  497. qcom,msm-dai-q6-dev-id = <12289>;
  498. };
  499. qcom,msm-dai-q6-int-fm-rx {
  500. compatible = "qcom,msm-dai-q6-dev";
  501. qcom,msm-dai-q6-dev-id = <12292>;
  502. };
  503. qcom,msm-dai-q6-int-fm-tx {
  504. compatible = "qcom,msm-dai-q6-dev";
  505. qcom,msm-dai-q6-dev-id = <12293>;
  506. };
  507. qcom,msm-dai-q6-be-afe-pcm-rx {
  508. compatible = "qcom,msm-dai-q6-dev";
  509. qcom,msm-dai-q6-dev-id = <224>;
  510. };
  511. qcom,msm-dai-q6-be-afe-pcm-tx {
  512. compatible = "qcom,msm-dai-q6-dev";
  513. qcom,msm-dai-q6-dev-id = <225>;
  514. };
  515. qcom,msm-dai-q6-afe-proxy-rx {
  516. compatible = "qcom,msm-dai-q6-dev";
  517. qcom,msm-dai-q6-dev-id = <241>;
  518. };
  519. qcom,msm-dai-q6-afe-proxy-tx {
  520. compatible = "qcom,msm-dai-q6-dev";
  521. qcom,msm-dai-q6-dev-id = <240>;
  522. };
  523. qcom,msm-dai-q6-incall-record-rx {
  524. compatible = "qcom,msm-dai-q6-dev";
  525. qcom,msm-dai-q6-dev-id = <32771>;
  526. };
  527. qcom,msm-dai-q6-incall-record-tx {
  528. compatible = "qcom,msm-dai-q6-dev";
  529. qcom,msm-dai-q6-dev-id = <32772>;
  530. };
  531. qcom,msm-dai-q6-incall-music-rx {
  532. compatible = "qcom,msm-dai-q6-dev";
  533. qcom,msm-dai-q6-dev-id = <32773>;
  534. };
  535. qcom,msm-dai-q6-incall-music-2-rx {
  536. compatible = "qcom,msm-dai-q6-dev";
  537. qcom,msm-dai-q6-dev-id = <32770>;
  538. };
  539. };
  540. qcom,msm-pcm-hostless {
  541. compatible = "qcom,msm-pcm-hostless";
  542. };
  543. qcom,msm-pri-auxpcm {
  544. compatible = "qcom,msm-auxpcm-dev";
  545. qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
  546. qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
  547. qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
  548. qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
  549. qcom,msm-cpudai-auxpcm-slot = <1>, <1>;
  550. qcom,msm-cpudai-auxpcm-data = <0>, <0>;
  551. qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
  552. qcom,msm-auxpcm-interface = "primary";
  553. };
  554. qcom,avtimer@fe053000 {
  555. compatible = "qcom,avtimer";
  556. reg = <0xfe053008 0x4>,
  557. <0xfe05300c 0x4>;
  558. reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
  559. };
  560. qcom,wcnss-wlan@fb000000 {
  561. compatible = "qcom,wcnss_wlan";
  562. reg = <0xfb000000 0x280000>,
  563. <0xf9011008 0x04>;
  564. reg-names = "wcnss_mmio", "wcnss_fiq";
  565. interrupts = <0 145 0 0 146 0>;
  566. interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
  567. qcom,pronto-vddmx-supply = <&pm8226_l3>;
  568. qcom,pronto-vddcx-supply = <&pm8226_s1>;
  569. qcom,pronto-vddpx-supply = <&pm8226_l6>;
  570. qcom,iris-vddxo-supply = <&pm8226_l10>;
  571. qcom,iris-vddrfa-supply = <&pm8226_l24>;
  572. qcom,iris-vddpa-supply = <&pm8226_l16>;
  573. qcom,iris-vdddig-supply = <&pm8226_l24>;
  574. gpios = <&msmgpio 40 0>, <&msmgpio 41 0>, <&msmgpio 42 0>, <&msmgpio 43 0>, <&msmgpio 44 0>;
  575. qcom,has-pronto-hw;
  576. qcom,has-autodetect-xo;
  577. qcom,wcnss-adc_tm = <&pm8226_adc_tm>;
  578. };
  579. qcom,msm-adsp-sensors {
  580. compatible = "qcom,msm-adsp-sensors";
  581. };
  582. qcom,wdt@f9017000 {
  583. compatible = "qcom,msm-watchdog";
  584. reg = <0xf9017000 0x1000>;
  585. interrupts = <0 3 0>, <0 4 0>;
  586. qcom,bark-time = <11000>;
  587. qcom,pet-time = <10000>;
  588. qcom,ipi-ping;
  589. };
  590. qcom,smem@fa00000 {
  591. compatible = "qcom,smem";
  592. reg = <0xfa00000 0x100000>,
  593. <0xf9011000 0x1000>,
  594. <0xfc428000 0x4000>;
  595. reg-names = "smem", "irq-reg-base", "aux-mem1";
  596. qcom,smd-modem {
  597. compatible = "qcom,smd";
  598. qcom,smd-edge = <0>;
  599. qcom,smd-irq-offset = <0x8>;
  600. qcom,smd-irq-bitmask = <0x1000>;
  601. qcom,pil-string = "modem";
  602. interrupts = <0 25 1>;
  603. };
  604. qcom,smsm-modem {
  605. compatible = "qcom,smsm";
  606. qcom,smsm-edge = <0>;
  607. qcom,smsm-irq-offset = <0x8>;
  608. qcom,smsm-irq-bitmask = <0x2000>;
  609. interrupts = <0 26 1>;
  610. };
  611. qcom,smd-adsp {
  612. compatible = "qcom,smd";
  613. qcom,smd-edge = <1>;
  614. qcom,smd-irq-offset = <0x8>;
  615. qcom,smd-irq-bitmask = <0x100>;
  616. qcom,pil-string = "adsp";
  617. interrupts = <0 156 1>;
  618. };
  619. qcom,smsm-adsp {
  620. compatible = "qcom,smsm";
  621. qcom,smsm-edge = <1>;
  622. qcom,smsm-irq-offset = <0x8>;
  623. qcom,smsm-irq-bitmask = <0x200>;
  624. interrupts = <0 157 1>;
  625. };
  626. qcom,smd-wcnss {
  627. compatible = "qcom,smd";
  628. qcom,smd-edge = <6>;
  629. qcom,smd-irq-offset = <0x8>;
  630. qcom,smd-irq-bitmask = <0x20000>;
  631. qcom,pil-string = "wcnss";
  632. interrupts = <0 142 1>;
  633. };
  634. qcom,smsm-wcnss {
  635. compatible = "qcom,smsm";
  636. qcom,smsm-edge = <6>;
  637. qcom,smsm-irq-offset = <0x8>;
  638. qcom,smsm-irq-bitmask = <0x80000>;
  639. interrupts = <0 144 1>;
  640. };
  641. qcom,smd-rpm {
  642. compatible = "qcom,smd";
  643. qcom,smd-edge = <15>;
  644. qcom,smd-irq-offset = <0x8>;
  645. qcom,smd-irq-bitmask = <0x1>;
  646. interrupts = <0 168 1>;
  647. qcom,irq-no-suspend;
  648. };
  649. };
  650. rpm_bus: qcom,rpm-smd {
  651. compatible = "qcom,rpm-smd";
  652. rpm-channel-name = "rpm_requests";
  653. rpm-channel-type = <15>; /* SMD_APPS_RPM */
  654. };
  655. qcom,bcl {
  656. compatible = "qcom,bcl";
  657. };
  658. rmtfs_sharedmem {
  659. compatible = "qcom,sharedmem-uio";
  660. reg = <0x0fd80000 0x00180000>;
  661. reg-names = "rmtfs";
  662. };
  663. dsp_sharedmem {
  664. compatible = "qcom,sharedmem-uio";
  665. reg = <0x0fd60000 0x00020000>;
  666. reg-names = "rfsa_dsp";
  667. };
  668. mdm_sharedmem {
  669. compatible = "qcom,sharedmem-uio";
  670. reg = <0x0fd60000 0x00020000>;
  671. reg-names = "rfsa_mdm";
  672. };
  673. sdcc1: qcom,sdcc@f9824000 {
  674. cell-index = <1>; /* SDC1 eMMC slot */
  675. compatible = "qcom,msm-sdcc";
  676. reg = <0xf9824000 0x800>,
  677. <0xf9824800 0x100>,
  678. <0xf9804000 0x7000>;
  679. reg-names = "core_mem", "dml_mem", "bam_mem";
  680. interrupts = <0 123 0>, <0 137 0>;
  681. interrupt-names = "core_irq", "bam_irq";
  682. qcom,bus-width = <8>;
  683. qcom,cpu-dma-latency-us = <701>;
  684. qcom,msm-bus,name = "sdcc1";
  685. qcom,msm-bus,num-cases = <8>;
  686. qcom,msm-bus,num-paths = <1>;
  687. qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
  688. <78 512 1600 3200>, /* 400 KB/s*/
  689. <78 512 80000 160000>, /* 20 MB/s */
  690. <78 512 100000 200000>, /* 25 MB/s */
  691. <78 512 200000 400000>, /* 50 MB/s */
  692. <78 512 400000 800000>, /* 100 MB/s */
  693. <78 512 400000 800000>, /* 200 MB/s */
  694. <78 512 2048000 4096000>; /* Max. bandwidth */
  695. qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
  696. 100000000 200000000 4294967295>;
  697. status = "disabled";
  698. };
  699. sdhc_1: sdhci@f9824900 {
  700. compatible = "qcom,sdhci-msm";
  701. reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
  702. reg-names = "hc_mem", "core_mem";
  703. interrupts = <0 123 0>, <0 138 0>;
  704. interrupt-names = "hc_irq", "pwr_irq";
  705. qcom,bus-width = <8>;
  706. qcom,cpu-dma-latency-us = <701>;
  707. qcom,msm-bus,name = "sdhc1";
  708. qcom,msm-bus,num-cases = <8>;
  709. qcom,msm-bus,num-paths = <1>;
  710. qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
  711. <78 512 1600 3200>, /* 400 KB/s*/
  712. <78 512 80000 160000>, /* 20 MB/s */
  713. <78 512 100000 200000>, /* 25 MB/s */
  714. <78 512 200000 400000>, /* 50 MB/s */
  715. <78 512 400000 800000>, /* 100 MB/s */
  716. <78 512 400000 800000>, /* 200 MB/s */
  717. <78 512 2048000 4096000>; /* Max. bandwidth */
  718. qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
  719. 100000000 200000000 4294967295>;
  720. status = "disabled";
  721. };
  722. sdcc2: qcom,sdcc@f98a4000 {
  723. cell-index = <2>; /* SDC2 SD card slot */
  724. compatible = "qcom,msm-sdcc";
  725. reg = <0xf98a4000 0x800>,
  726. <0xf98a4800 0x100>,
  727. <0xf9884000 0x7000>;
  728. reg-names = "core_mem", "dml_mem", "bam_mem";
  729. interrupts = <0 125 0>, <0 220 0>;
  730. interrupt-names = "core_irq", "bam_irq";
  731. qcom,bus-width = <4>;
  732. qcom,cpu-dma-latency-us = <701>;
  733. qcom,msm-bus,name = "sdcc2";
  734. qcom,msm-bus,num-cases = <8>;
  735. qcom,msm-bus,num-paths = <1>;
  736. qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
  737. <81 512 1600 3200>, /* 400 KB/s*/
  738. <81 512 80000 160000>, /* 20 MB/s */
  739. <81 512 100000 200000>, /* 25 MB/s */
  740. <81 512 200000 400000>, /* 50 MB/s */
  741. <81 512 400000 800000>, /* 100 MB/s */
  742. <81 512 400000 800000>, /* 200 MB/s */
  743. <81 512 2048000 4096000>; /* Max. bandwidth */
  744. qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
  745. 100000000 200000000 4294967295>;
  746. status = "disabled";
  747. };
  748. sdhc_2: sdhci@f98a4900 {
  749. compatible = "qcom,sdhci-msm";
  750. reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
  751. reg-names = "hc_mem", "core_mem";
  752. interrupts = <0 125 0>, <0 221 0>;
  753. interrupt-names = "hc_irq", "pwr_irq";
  754. qcom,bus-width = <4>;
  755. qcom,cpu-dma-latency-us = <701>;
  756. qcom,msm-bus,name = "sdhc2";
  757. qcom,msm-bus,num-cases = <8>;
  758. qcom,msm-bus,num-paths = <1>;
  759. qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
  760. <81 512 1600 3200>, /* 400 KB/s*/
  761. <81 512 80000 160000>, /* 20 MB/s */
  762. <81 512 100000 200000>, /* 25 MB/s */
  763. <81 512 200000 400000>, /* 50 MB/s */
  764. <81 512 400000 800000>, /* 100 MB/s */
  765. <81 512 400000 800000>, /* 200 MB/s */
  766. <81 512 2048000 4096000>; /* Max. bandwidth */
  767. qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
  768. 100000000 200000000 4294967295>;
  769. status = "disabled";
  770. };
  771. sdcc3: qcom,sdcc@f9864000 {
  772. cell-index = <3>;
  773. compatible = "qcom,msm-sdcc";
  774. reg = <0xf9864000 0x800>,
  775. <0xf9864800 0x100>,
  776. <0xf9844000 0x7000>;
  777. reg-names = "core_mem", "dml_mem", "bam_mem";
  778. qcom,bus-width = <4>;
  779. qcom,cpu-dma-latency-us = <701>;
  780. gpios = <&msmgpio 44 0>, /* CLK */
  781. <&msmgpio 43 0>, /* CMD */
  782. <&msmgpio 42 0>, /* DATA0 */
  783. <&msmgpio 41 0>, /* DATA1 */
  784. <&msmgpio 40 0>, /* DATA2 */
  785. <&msmgpio 39 0>; /* DATA3 */
  786. qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
  787. qcom,clk-rates = <400000 20000000 25000000 50000000 100000000>;
  788. qcom,msm-bus,name = "sdcc3";
  789. qcom,msm-bus,num-cases = <8>;
  790. qcom,msm-bus,num-paths = <1>;
  791. qcom,msm-bus,vectors-KBps = <79 512 0 0>, /* No vote */
  792. <79 512 1600 3200>, /* 400 KB/s*/
  793. <79 512 80000 160000>, /* 20 MB/s */
  794. <79 512 100000 200000>, /* 25 MB/s */
  795. <79 512 200000 400000>, /* 50 MB/s */
  796. <79 512 400000 800000>, /* 100 MB/s */
  797. <79 512 400000 800000>, /* 200 MB/s */
  798. <79 512 2048000 4096000>; /* Max. bandwidth */
  799. qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
  800. 100000000 200000000 4294967295>;
  801. #address-cells = <0>;
  802. interrupt-parent = <&sdcc3>;
  803. interrupts = <0 1 2>;
  804. #interrupt-cells = <1>;
  805. interrupt-map-mask = <0xffffffff>;
  806. interrupt-map = <0 &intc 0 127 0
  807. 1 &intc 0 223 0
  808. 2 &msmgpio 41 0x8>;
  809. interrupt-names = "core_irq", "bam_irq", "sdiowakeup_irq";
  810. status = "disabled";
  811. };
  812. sdhc_3: sdhci@f9864900 {
  813. compatible = "qcom,sdhci-msm";
  814. reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
  815. reg-names = "hc_mem", "core_mem";
  816. qcom,bus-width = <4>;
  817. qcom,cpu-dma-latency-us = <701>;
  818. gpios = <&msmgpio 44 0>, /* CLK */
  819. <&msmgpio 43 0>, /* CMD */
  820. <&msmgpio 42 0>, /* DATA0 */
  821. <&msmgpio 41 0>, /* DATA1 */
  822. <&msmgpio 40 0>, /* DATA2 */
  823. <&msmgpio 39 0>; /* DATA3 */
  824. qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
  825. qcom,clk-rates = <400000 20000000 25000000 50000000 100000000>;
  826. qcom,msm-bus,name = "sdhc3";
  827. qcom,msm-bus,num-cases = <8>;
  828. qcom,msm-bus,num-paths = <1>;
  829. qcom,msm-bus,vectors-KBps = <79 512 0 0>, /* No vote */
  830. <79 512 1600 3200>, /* 400 KB/s*/
  831. <79 512 80000 160000>, /* 20 MB/s */
  832. <79 512 100000 200000>, /* 25 MB/s */
  833. <79 512 200000 400000>, /* 50 MB/s */
  834. <79 512 400000 800000>, /* 100 MB/s */
  835. <79 512 400000 800000>, /* 200 MB/s */
  836. <79 512 2048000 4096000>; /* Max. bandwidth */
  837. qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
  838. 100000000 200000000 4294967295>;
  839. #address-cells = <0>;
  840. interrupt-parent = <&sdhc_3>;
  841. interrupts = <0 1 2>;
  842. #interrupt-cells = <1>;
  843. interrupt-map-mask = <0xffffffff>;
  844. interrupt-map = <0 &intc 0 127 0
  845. 1 &intc 0 224 0
  846. 2 &msmgpio 41 0x8>;
  847. interrupt-names = "hc_irq", "pwr_irq", "sdiowakeup_irq";
  848. status = "disabled";
  849. };
  850. spmi_bus: qcom,spmi@fc4c0000 {
  851. cell-index = <0>;
  852. compatible = "qcom,spmi-pmic-arb";
  853. reg-names = "core", "intr", "cnfg";
  854. reg = <0xfc4cf000 0x1000>,
  855. <0Xfc4cb000 0x1000>,
  856. <0Xfc4ca000 0x1000>;
  857. /* 190,ee0_krait_hlos_spmi_periph_irq */
  858. /* 187,channel_0_krait_hlos_trans_done_irq */
  859. interrupts = <0 190 0>, <0 187 0>;
  860. qcom,pmic-arb-ee = <0>;
  861. qcom,pmic-arb-channel = <0>;
  862. };
  863. i2c@f9925000 { /* BLSP-1 QUP-3 */
  864. cell-index = <2>;
  865. compatible = "qcom,i2c-qup";
  866. reg = <0xf9925000 0x1000>;
  867. #address-cells = <1>;
  868. #size-cells = <0>;
  869. reg-names = "qup_phys_addr";
  870. interrupts = <0 97 0>;
  871. interrupt-names = "qup_err_intr";
  872. qcom,i2c-bus-freq = <400000>;
  873. qcom,i2c-src-freq = <19200000>;
  874. qcom,sda-gpio = <&msmgpio 10 0>;
  875. qcom,scl-gpio = <&msmgpio 11 0>;
  876. qcom,master-id = <86>;
  877. };
  878. i2c_0: i2c@f9926000 { /* BLSP-1 QUP-4 */
  879. cell-index = <0>;
  880. compatible = "qcom,i2c-qup";
  881. reg = <0xf9926000 0x1000>;
  882. #address-cells = <1>;
  883. #size-cells = <0>;
  884. reg-names = "qup_phys_addr";
  885. interrupts = <0 98 0>;
  886. interrupt-names = "qup_err_intr";
  887. qcom,i2c-bus-freq = <100000>;
  888. qcom,i2c-src-freq = <19200000>;
  889. qcom,master-id = <86>;
  890. };
  891. i2c@f9927000 { /* BLSP1 QUP5 */
  892. cell-index = <5>;
  893. compatible = "qcom,i2c-qup";
  894. #address-cells = <1>;
  895. #size-cells = <0>;
  896. reg-names = "qup_phys_addr";
  897. reg = <0xf9927000 0x1000>;
  898. interrupt-names = "qup_err_intr";
  899. interrupts = <0 99 0>;
  900. qcom,i2c-bus-freq = <384000>;
  901. qcom,i2c-src-freq = <19200000>;
  902. qcom,sda-gpio = <&msmgpio 18 0>;
  903. qcom,scl-gpio = <&msmgpio 19 0>;
  904. };
  905. qcom,clock-a7@f9011050 {
  906. compatible = "qcom,clock-a7-8226";
  907. reg = <0xf9011050 0x8>;
  908. reg-names = "rcg-base";
  909. clock-names = "clk-4", "clk-5";
  910. qcom,speed0-bin-v0 =
  911. < 0 0>,
  912. < 384000000 1>,
  913. < 787200000 2>,
  914. <1190400000 3>;
  915. cpu-vdd-supply = <&apc_vreg_corner>;
  916. };
  917. qcom,cpubw {
  918. compatible = "qcom,cpubw";
  919. qcom,cpu-mem-ports = <1 512>;
  920. qcom,bw-tbl =
  921. < 1525 /* 200 MHz */ >,
  922. < 2441 /* 320 MHz */ >,
  923. < 3051 /* 400 MHz */ >,
  924. < 4066 /* 533 MHz */ >;
  925. };
  926. qcom,msm-cpufreq@0 {
  927. reg = <0 4>;
  928. compatible = "qcom,msm-cpufreq";
  929. qcom,cpufreq-table =
  930. < 300000 1525 >,
  931. < 384000 1525 >,
  932. < 600000 1525 >,
  933. < 787200 1525 >,
  934. < 998400 4066 >,
  935. < 1094400 4066 >,
  936. < 1190400 4066 >,
  937. < 1305600 4066 >,
  938. < 1344000 4066 >,
  939. < 1401600 4066 >,
  940. < 1497600 4066 >,
  941. < 1593600 4066 >,
  942. < 1689600 4066 >,
  943. < 1785600 4066 >;
  944. };
  945. qcom,ocmem@fdd00000 {
  946. compatible = "qcom,msm-ocmem";
  947. reg = <0xfdd00000 0x2000>,
  948. <0xfdd02000 0x2000>,
  949. <0xfe039000 0x400>,
  950. <0xfec00000 0x20000>;
  951. reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
  952. interrupts = <0 76 0 0 77 0>;
  953. interrupt-names = "ocmem_irq", "dm_irq";
  954. qcom,ocmem-num-regions = <0x1>;
  955. qcom,ocmem-num-macros = <0x2>;
  956. qcom,resource-type = <0x706d636f>;
  957. #address-cells = <1>;
  958. #size-cells = <1>;
  959. ranges = <0x0 0xfec00000 0x20000>;
  960. partition@0 {
  961. reg = <0x0 0x20000>;
  962. qcom,ocmem-part-name = "graphics";
  963. qcom,ocmem-part-min = <0x20000>;
  964. };
  965. };
  966. qcom,venus@fdce0000 {
  967. compatible = "qcom,pil-venus";
  968. reg = <0xfdce0000 0x4000>,
  969. <0xfdc80000 0x400>;
  970. reg-names = "wrapper_base", "vbif_base";
  971. vdd-supply = <&gdsc_venus>;
  972. qcom,firmware-name = "venus";
  973. };
  974. qcom,pronto@fb21b000 {
  975. compatible = "qcom,pil-pronto";
  976. reg = <0xfb21b000 0x3000>,
  977. <0xfc401700 0x4>,
  978. <0xfd485300 0xc>;
  979. reg-names = "pmu_base", "clk_base", "halt_base";
  980. interrupts = <0 149 1>;
  981. vdd_pronto_pll-supply = <&pm8226_l8>;
  982. qcom,firmware-name = "wcnss";
  983. /* GPIO inputs from wcnss */
  984. qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>;
  985. qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_4_in 1 0>;
  986. qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>;
  987. /* GPIO output to wcnss */
  988. qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>;
  989. };
  990. qcom,iris-fm {
  991. compatible = "qcom,iris_fm";
  992. };
  993. qcom,lpass@fe200000 {
  994. compatible = "qcom,pil-q6v5-lpass";
  995. reg = <0xfe200000 0x00100>,
  996. <0xfd485100 0x00010>,
  997. <0xfc4016c0 0x00004>;
  998. reg-names = "qdsp6_base", "halt_base", "restart_reg";
  999. vdd_cx-supply = <&pm8226_s1_corner>;
  1000. interrupts = <0 162 1>;
  1001. qcom,firmware-name = "adsp";
  1002. /* GPIO inputs from lpass */
  1003. qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
  1004. qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
  1005. qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
  1006. /* GPIO output to lpass */
  1007. qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
  1008. };
  1009. qcom,mss@fc880000 {
  1010. compatible = "qcom,pil-q6v5-mss";
  1011. reg = <0xfc880000 0x100>,
  1012. <0xfd485000 0x400>,
  1013. <0xfc820000 0x020>,
  1014. <0xfc401680 0x004>,
  1015. <0xfd485194 0x4>;
  1016. reg-names = "qdsp6_base", "halt_base", "rmb_base",
  1017. "restart_reg", "cxrail_bhs_reg";
  1018. interrupts = <0 24 1>;
  1019. vdd_cx-supply = <&pm8226_s1_corner>;
  1020. vdd_mx-supply = <&pm8226_l3>;
  1021. vdd_pll-supply = <&pm8226_l8>;
  1022. qcom,vdd_pll = <1800000>;
  1023. qcom,is-loadable;
  1024. qcom,firmware-name = "mba";
  1025. qcom,pil-self-auth;
  1026. /* GPIO inputs from mss */
  1027. qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
  1028. qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
  1029. qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
  1030. qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
  1031. /* GPIO output to mss */
  1032. qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
  1033. };
  1034. memory_hole: qcom,msm-mem-hole {
  1035. compatible = "qcom,msm-mem-hole";
  1036. qcom,memblock-remove = <0x08400000 0x4000000
  1037. 0x0d200000 0x2300000
  1038. 0x0fa00000 0x500000>; /* Address and Size of Hole */
  1039. };
  1040. tsens: tsens@fc4a8000 {
  1041. compatible = "qcom,msm-tsens";
  1042. reg = <0xfc4a8000 0x2000>,
  1043. <0xfc4bc000 0x1000>;
  1044. reg-names = "tsens_physical", "tsens_eeprom_physical";
  1045. interrupts = <0 184 0>;
  1046. qcom,sensors = <4>;
  1047. qcom,slope = <2901 2846 3038 2955>;
  1048. qcom,calib-mode = "fuse_map2";
  1049. };
  1050. qcom,msm-thermal {
  1051. compatible = "qcom,msm-thermal";
  1052. qcom,sensor-id = <0>;
  1053. qcom,poll-ms = <250>;
  1054. qcom,limit-temp = <60>;
  1055. qcom,temp-hysteresis = <10>;
  1056. qcom,freq-step = <2>;
  1057. qcom,freq-control-mask = <0xf>;
  1058. qcom,core-limit-temp = <80>;
  1059. qcom,core-temp-hysteresis = <10>;
  1060. qcom,core-control-mask = <0xe>;
  1061. qcom,hotplug-temp = <110>;
  1062. qcom,hotplug-temp-hysteresis = <20>;
  1063. qcom,cpu-sensors = "tsens_tz_sensor5", "tsens_tz_sensor5",
  1064. "tsens_tz_sensor2", "tsens_tz_sensor2";
  1065. qcom,vdd-restriction-temp = <5>;
  1066. qcom,vdd-restriction-temp-hysteresis = <10>;
  1067. vdd-dig-supply = <&pm8226_s1_floor_corner>;
  1068. qcom,vdd-dig-rstr{
  1069. qcom,vdd-rstr-reg = "vdd-dig";
  1070. qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */
  1071. qcom,min-level = <1>; /* No Request */
  1072. };
  1073. qcom,vdd-apps-rstr{
  1074. qcom,vdd-rstr-reg = "vdd-apps";
  1075. qcom,levels = <600000 787200 998400>;
  1076. qcom,freq-req;
  1077. };
  1078. };
  1079. spi_0: spi@f9923000 { /* BLSP1 QUP1 */
  1080. compatible = "qcom,spi-qup-v2";
  1081. #address-cells = <1>;
  1082. #size-cells = <0>;
  1083. reg-names = "spi_physical", "spi_bam_physical";
  1084. reg = <0xf9923000 0x1000>,
  1085. <0xf9904000 0xF000>;
  1086. interrupt-names = "spi_irq", "spi_bam_irq";
  1087. interrupts = <0 95 0>, <0 238 0>;
  1088. spi-max-frequency = <19200000>;
  1089. qcom,gpio-mosi = <&msmgpio 0 0>;
  1090. qcom,gpio-miso = <&msmgpio 1 0>;
  1091. qcom,gpio-clk = <&msmgpio 3 0>;
  1092. qcom,gpio-cs0 = <&msmgpio 22 0>;
  1093. qcom,infinite-mode = <0>;
  1094. qcom,use-bam;
  1095. qcom,ver-reg-exists;
  1096. qcom,bam-consumer-pipe-index = <12>;
  1097. qcom,bam-producer-pipe-index = <13>;
  1098. qcom,master-id = <86>;
  1099. };
  1100. qcom,bam_dmux@fc834000 {
  1101. compatible = "qcom,bam_dmux";
  1102. reg = <0xfc834000 0x7000>;
  1103. interrupts = <0 29 1>;
  1104. };
  1105. qcom,msm-rtb {
  1106. compatible = "qcom,msm-rtb";
  1107. qcom,memory-reservation-type = "EBI1";
  1108. qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */
  1109. };
  1110. qcom,msm-rng@f9bff000 {
  1111. compatible = "qcom,msm-rng";
  1112. reg = <0xf9bff000 0x200>;
  1113. qcom,msm-rng-iface-clk;
  1114. qcom,msm-bus,name = "msm-rng-noc";
  1115. qcom,msm-bus,num-cases = <2>;
  1116. qcom,msm-bus,num-paths = <1>;
  1117. qcom,msm-bus,vectors-KBps =
  1118. <54 618 0 0>,
  1119. <54 618 0 800>;
  1120. };
  1121. qcom,tz-log@fe805720 {
  1122. compatible = "qcom,tz-log";
  1123. reg = <0x0fe805720 0x1000>;
  1124. };
  1125. jtag_fuse: jtagfuse@fc4be024 {
  1126. compatible = "qcom,jtag-fuse";
  1127. reg = <0xfc4be024 0x8>;
  1128. reg-names = "fuse-base";
  1129. };
  1130. jtag_mm0: jtagmm@fc33c000 {
  1131. compatible = "qcom,jtag-mm";
  1132. reg = <0xfc33c000 0x1000>,
  1133. <0xfc330000 0x1000>;
  1134. reg-names = "etm-base","debug-base";
  1135. };
  1136. jtag_mm1: jtagmm@fc33d000 {
  1137. compatible = "qcom,jtag-mm";
  1138. reg = <0xfc33d000 0x1000>,
  1139. <0xfc332000 0x1000>;
  1140. reg-names = "etm-base","debug-base";
  1141. };
  1142. jtag_mm2: jtagmm@fc33e000 {
  1143. compatible = "qcom,jtag-mm";
  1144. reg = <0xfc33e000 0x1000>,
  1145. <0xfc334000 0x1000>;
  1146. reg-names = "etm-base","debug-base";
  1147. };
  1148. jtag_mm3: jtagmm@fc33f000 {
  1149. compatible = "qcom,jtag-mm";
  1150. reg = <0xfc33f000 0x1000>,
  1151. <0xfc336000 0x1000>;
  1152. reg-names = "etm-base","debug-base";
  1153. };
  1154. qcom,ipc-spinlock@fd484000 {
  1155. compatible = "qcom,ipc-spinlock-sfpb";
  1156. reg = <0xfd484000 0x400>;
  1157. qcom,num-locks = <8>;
  1158. };
  1159. qcom,qseecom@d980000 {
  1160. compatible = "qcom,qseecom";
  1161. reg = <0xd980000 0x256000>;
  1162. reg-names = "secapp-region";
  1163. qcom,disk-encrypt-pipe-pair = <2>;
  1164. qcom,hlos-ce-hw-instance = <0>;
  1165. qcom,qsee-ce-hw-instance = <0>;
  1166. qcom,support-bus-scaling;
  1167. qcom,msm-bus,name = "qseecom-noc";
  1168. qcom,msm-bus,num-cases = <4>;
  1169. qcom,msm-bus,active-only = <0>;
  1170. qcom,msm-bus,num-paths = <1>;
  1171. qcom,support-fde;
  1172. qcom,msm-bus,vectors-KBps =
  1173. <55 512 0 0>,
  1174. <55 512 0 0>,
  1175. <55 512 120000 1200000>,
  1176. <55 512 393600 3936000>;
  1177. };
  1178. qcom,qcrypto@fd404000 {
  1179. compatible = "qcom,qcrypto";
  1180. reg = <0xfd400000 0x20000>,
  1181. <0xfd404000 0x8000>;
  1182. reg-names = "crypto-base","crypto-bam-base";
  1183. interrupts = <0 207 0>;
  1184. qcom,bam-pipe-pair = <2>;
  1185. qcom,ce-hw-instance = <0>;
  1186. qcom,ce-device = <0>;
  1187. qcom,ce-hw-shared;
  1188. qcom,msm-bus,name = "qcrypto-noc";
  1189. qcom,msm-bus,num-cases = <2>;
  1190. qcom,msm-bus,active-only = <0>;
  1191. qcom,msm-bus,num-paths = <1>;
  1192. qcom,msm-bus,vectors-KBps =
  1193. <55 512 0 0>,
  1194. <55 512 3936000 393600>;
  1195. };
  1196. qcom,qcedev@fd400000 {
  1197. compatible = "qcom,qcedev";
  1198. reg = <0xfd400000 0x20000>,
  1199. <0xfd404000 0x8000>;
  1200. reg-names = "crypto-base","crypto-bam-base";
  1201. interrupts = <0 207 0>;
  1202. qcom,bam-pipe-pair = <1>;
  1203. qcom,ce-hw-instance = <0>;
  1204. qcom,ce-device = <0>;
  1205. qcom,ce-hw-shared;
  1206. qcom,msm-bus,name = "qcedev-noc";
  1207. qcom,msm-bus,num-cases = <2>;
  1208. qcom,msm-bus,active-only = <0>;
  1209. qcom,msm-bus,num-paths = <1>;
  1210. qcom,msm-bus,vectors-KBps =
  1211. <55 512 0 0>,
  1212. <55 512 3936000 393600>;
  1213. };
  1214. cpu-pmu {
  1215. compatible = "arm,cortex-a7-pmu";
  1216. qcom,irq-is-percpu;
  1217. interrupts = <1 7 0xf00>;
  1218. };
  1219. bimc_sharedmem {
  1220. compatible = "qcom,sharedmem-uio";
  1221. reg = <0xfc380000 0x00100000>;
  1222. reg-names = "bimc";
  1223. };
  1224. };
  1225. &gdsc_venus {
  1226. qcom,clock-names = "core_clk";
  1227. status = "ok";
  1228. };
  1229. &gdsc_mdss {
  1230. qcom,clock-names = "core_clk", "lut_clk";
  1231. status = "ok";
  1232. };
  1233. &gdsc_jpeg {
  1234. qcom,clock-names = "core_clk";
  1235. status = "ok";
  1236. };
  1237. &gdsc_vfe {
  1238. qcom,clock-names = "core_clk", "csi_clk", "cpp_clk";
  1239. status = "ok";
  1240. };
  1241. &gdsc_oxili_cx {
  1242. qcom,clock-names = "core_clk";
  1243. status = "ok";
  1244. };
  1245. &gdsc_usb_hsic {
  1246. status = "ok";
  1247. };
  1248. /include/ "msm-pm8226-rpm-regulator.dtsi"
  1249. /include/ "msm-pm8226.dtsi"
  1250. /include/ "msm8226-regulator.dtsi"
  1251. &pm8226_vadc {
  1252. chan@0 {
  1253. label = "usb_in";
  1254. reg = <0>;
  1255. qcom,decimation = <0>;
  1256. qcom,pre-div-channel-scaling = <4>;
  1257. qcom,calibration-type = "absolute";
  1258. qcom,scale-function = <0>;
  1259. qcom,hw-settle-time = <0>;
  1260. qcom,fast-avg-setup = <0>;
  1261. };
  1262. chan@2 {
  1263. label = "vchg_sns";
  1264. reg = <2>;
  1265. qcom,decimation = <0>;
  1266. qcom,pre-div-channel-scaling = <3>;
  1267. qcom,calibration-type = "absolute";
  1268. qcom,scale-function = <0>;
  1269. qcom,hw-settle-time = <0>;
  1270. qcom,fast-avg-setup = <0>;
  1271. };
  1272. chan@5 {
  1273. label = "vcoin";
  1274. reg = <5>;
  1275. qcom,decimation = <0>;
  1276. qcom,pre-div-channel-scaling = <1>;
  1277. qcom,calibration-type = "absolute";
  1278. qcom,scale-function = <0>;
  1279. qcom,hw-settle-time = <0>;
  1280. qcom,fast-avg-setup = <0>;
  1281. };
  1282. chan@6 {
  1283. label = "vbat_sns";
  1284. reg = <6>;
  1285. qcom,decimation = <0>;
  1286. qcom,pre-div-channel-scaling = <1>;
  1287. qcom,calibration-type = "absolute";
  1288. qcom,scale-function = <0>;
  1289. qcom,hw-settle-time = <0>;
  1290. qcom,fast-avg-setup = <0>;
  1291. };
  1292. chan@7 {
  1293. label = "vph_pwr";
  1294. reg = <7>;
  1295. qcom,decimation = <0>;
  1296. qcom,pre-div-channel-scaling = <1>;
  1297. qcom,calibration-type = "absolute";
  1298. qcom,scale-function = <0>;
  1299. qcom,hw-settle-time = <0>;
  1300. qcom,fast-avg-setup = <0>;
  1301. };
  1302. chan@30 {
  1303. label = "batt_therm";
  1304. reg = <0x30>;
  1305. qcom,decimation = <0>;
  1306. qcom,pre-div-channel-scaling = <0>;
  1307. qcom,calibration-type = "ratiometric";
  1308. qcom,scale-function = <1>;
  1309. qcom,hw-settle-time = <2>;
  1310. qcom,fast-avg-setup = <0>;
  1311. };
  1312. chan@31 {
  1313. label = "batt_id";
  1314. reg = <0x31>;
  1315. qcom,decimation = <0>;
  1316. qcom,pre-div-channel-scaling = <0>;
  1317. qcom,calibration-type = "ratiometric";
  1318. qcom,scale-function = <0>;
  1319. qcom,hw-settle-time = <2>;
  1320. qcom,fast-avg-setup = <0>;
  1321. };
  1322. chan@b2 {
  1323. label = "xo_therm_pu2";
  1324. reg = <0xb2>;
  1325. qcom,decimation = <0>;
  1326. qcom,pre-div-channel-scaling = <0>;
  1327. qcom,calibration-type = "ratiometric";
  1328. qcom,scale-function = <4>;
  1329. qcom,hw-settle-time = <2>;
  1330. qcom,fast-avg-setup = <0>;
  1331. };
  1332. chan@39 {
  1333. label = "usb_id_nopull";
  1334. reg = <0x39>;
  1335. qcom,decimation = <0>;
  1336. qcom,pre-div-channel-scaling = <0>;
  1337. qcom,calibration-type = "ratiometric";
  1338. qcom,scale-function = <0>;
  1339. qcom,hw-settle-time = <2>;
  1340. qcom,fast-avg-setup = <0>;
  1341. };
  1342. };
  1343. &pm8226_adc_tm {
  1344. /* Channel Node */
  1345. chan@30 {
  1346. label = "batt_therm";
  1347. reg = <0x30>;
  1348. qcom,decimation = <0>;
  1349. qcom,pre-div-channel-scaling = <0>;
  1350. qcom,calibration-type = "ratiometric";
  1351. qcom,scale-function = <1>;
  1352. qcom,hw-settle-time = <2>;
  1353. qcom,fast-avg-setup = <3>;
  1354. qcom,btm-channel-number = <0x48>;
  1355. qcom,meas-interval-timer-idx = <2>;
  1356. };
  1357. chan@8 {
  1358. label = "die_temp";
  1359. reg = <8>;
  1360. qcom,decimation = <0>;
  1361. qcom,pre-div-channel-scaling = <0>;
  1362. qcom,calibration-type = "absolute";
  1363. qcom,scale-function = <3>;
  1364. qcom,hw-settle-time = <0>;
  1365. qcom,fast-avg-setup = <3>;
  1366. qcom,btm-channel-number = <0x68>;
  1367. };
  1368. chan@6 {
  1369. label = "vbat_sns";
  1370. reg = <6>;
  1371. qcom,decimation = <0>;
  1372. qcom,pre-div-channel-scaling = <1>;
  1373. qcom,calibration-type = "absolute";
  1374. qcom,scale-function = <0>;
  1375. qcom,hw-settle-time = <0>;
  1376. qcom,fast-avg-setup = <3>;
  1377. qcom,btm-channel-number = <0x70>;
  1378. };
  1379. chan@14 {
  1380. label = "pa_therm0";
  1381. reg = <0x14>;
  1382. qcom,decimation = <0>;
  1383. qcom,pre-div-channel-scaling = <0>;
  1384. qcom,calibration-type = "ratiometric";
  1385. qcom,scale-function = <2>;
  1386. qcom,hw-settle-time = <2>;
  1387. qcom,fast-avg-setup = <0>;
  1388. qcom,btm-channel-number = <0x78>;
  1389. qcom,thermal-node;
  1390. };
  1391. chan@17 {
  1392. label = "pa_therm1";
  1393. reg = <0x17>;
  1394. qcom,decimation = <0>;
  1395. qcom,pre-div-channel-scaling = <0>;
  1396. qcom,calibration-type = "ratiometric";
  1397. qcom,scale-function = <2>;
  1398. qcom,hw-settle-time = <2>;
  1399. qcom,fast-avg-setup = <0>;
  1400. qcom,btm-channel-number = <0x80>;
  1401. qcom,thermal-node;
  1402. };
  1403. };
  1404. &pm8226_chg {
  1405. status = "ok";
  1406. qcom,chgr@1000 {
  1407. status = "ok";
  1408. };
  1409. qcom,buck@1100 {
  1410. status = "ok";
  1411. };
  1412. qcom,bat-if@1200 {
  1413. status = "ok";
  1414. };
  1415. qcom,usb-chgpth@1300 {
  1416. status = "ok";
  1417. };
  1418. qcom,boost@1500 {
  1419. status = "ok";
  1420. };
  1421. qcom,chg-misc@1600 {
  1422. status = "ok";
  1423. };
  1424. };