msm8226-gpu.dtsi 4.1 KB

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  1. /* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. &soc {
  13. msm_gpu: qcom,kgsl-3d0@fdb00000 {
  14. label = "kgsl-3d0";
  15. compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
  16. reg = <0xfdb00000 0x10000
  17. 0xfdb20000 0x10000>;
  18. reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory";
  19. interrupts = <0 33 0>;
  20. interrupt-names = "kgsl_3d0_irq";
  21. qcom,id = <0>;
  22. qcom,chipid = <0x03000510>;
  23. qcom,initial-pwrlevel = <1>;
  24. qcom,idle-timeout = <8>; //<HZ/12>
  25. qcom,strtstp-sleepwake;
  26. qcom,clk-map = <0x00000016>; /* KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM_IFACE */
  27. /* Bus Scale Settings */
  28. qcom,msm-bus,name = "grp3d";
  29. qcom,msm-bus,num-cases = <4>;
  30. qcom,msm-bus,num-paths = <2>;
  31. qcom,msm-bus,vectors-KBps =
  32. <26 512 0 0>, <89 604 0 0>,
  33. <26 512 800000 1600000>, <89 604 0 3200000>,
  34. <26 512 1600000 3200000>, <89 604 0 5120000>,
  35. <26 512 2128000 4256000>, <89 604 0 6400000>;
  36. /* GDSC oxili regulators */
  37. vddcx-supply = "\0";
  38. vdd-supply = <&gdsc_oxili_cx>;
  39. /* IOMMU Data */
  40. iommu = <&kgsl_iommu>;
  41. /* CPU latency parameter */
  42. qcom,pm-qos-latency = <701>;
  43. /* Power levels */
  44. qcom,gpu-pwrlevels {
  45. #address-cells = <1>;
  46. #size-cells = <0>;
  47. compatible = "qcom,gpu-pwrlevels";
  48. qcom,gpu-pwrlevel@0 {
  49. reg = <0>;
  50. qcom,gpu-freq = <450000000>;
  51. qcom,bus-freq = <3>;
  52. qcom,io-fraction = <0>;
  53. };
  54. qcom,gpu-pwrlevel@1 {
  55. reg = <1>;
  56. qcom,gpu-freq = <320000000>;
  57. qcom,bus-freq = <2>;
  58. qcom,io-fraction = <33>;
  59. };
  60. qcom,gpu-pwrlevel@2 {
  61. reg = <2>;
  62. qcom,gpu-freq = <200000000>;
  63. qcom,bus-freq = <1>;
  64. qcom,io-fraction = <100>;
  65. };
  66. qcom,gpu-pwrlevel@3 {
  67. reg = <3>;
  68. qcom,gpu-freq = <19000000>;
  69. qcom,bus-freq = <0>;
  70. qcom,io-fraction = <0>;
  71. };
  72. };
  73. qcom,dcvs-core-info {
  74. #address-cells = <1>;
  75. #size-cells = <0>;
  76. compatible = "qcom,dcvs-core-info";
  77. qcom,num-cores = <1>;
  78. qcom,sensors = <0>;
  79. qcom,core-core-type = <1>;
  80. qcom,algo-disable-pc-threshold = <0>;
  81. qcom,algo-em-win-size-min-us = <100000>;
  82. qcom,algo-em-win-size-max-us = <300000>;
  83. qcom,algo-em-max-util-pct = <97>;
  84. qcom,algo-group-id = <95>;
  85. qcom,algo-max-freq-chg-time-us = <100000>;
  86. qcom,algo-slack-mode-dynamic = <100000>;
  87. qcom,algo-slack-weight-thresh-pct = <0>;
  88. qcom,algo-slack-time-min-us = <39000>;
  89. qcom,algo-slack-time-max-us = <39000>;
  90. qcom,algo-ss-win-size-min-us = <1000000>;
  91. qcom,algo-ss-win-size-max-us = <1000000>;
  92. qcom,algo-ss-util-pct = <95>;
  93. qcom,algo-ss-no-corr-below-freq = <0>;
  94. qcom,energy-active-coeff-a = <2492>;
  95. qcom,energy-active-coeff-b = <0>;
  96. qcom,energy-active-coeff-c = <0>;
  97. qcom,energy-leakage-coeff-a = <11>;
  98. qcom,energy-leakage-coeff-b = <157150>;
  99. qcom,energy-leakage-coeff-c = <0>;
  100. qcom,energy-leakage-coeff-d = <0>;
  101. qcom,power-current-temp = <25>;
  102. qcom,power-num-freq = <4>;
  103. qcom,dcvs-freq@0 {
  104. reg = <0>;
  105. qcom,freq = <0>;
  106. qcom,voltage = <0>;
  107. qcom,is_trans_level = <0>;
  108. qcom,active-energy-offset = <100>;
  109. qcom,leakage-energy-offset = <0>;
  110. };
  111. qcom,dcvs-freq@1 {
  112. reg = <1>;
  113. qcom,freq = <0>;
  114. qcom,voltage = <0>;
  115. qcom,is_trans_level = <0>;
  116. qcom,active-energy-offset = <100>;
  117. qcom,leakage-energy-offset = <0>;
  118. };
  119. qcom,dcvs-freq@2 {
  120. reg = <2>;
  121. qcom,freq = <0>;
  122. qcom,voltage = <0>;
  123. qcom,is_trans_level = <0>;
  124. qcom,active-energy-offset = <100>;
  125. qcom,leakage-energy-offset = <0>;
  126. };
  127. qcom,dcvs-freq@3 {
  128. reg = <3>;
  129. qcom,freq = <0>;
  130. qcom,voltage = <0>;
  131. qcom,is_trans_level = <0>;
  132. qcom,active-energy-offset = <844545>;
  133. qcom,leakage-energy-offset = <0>;
  134. };
  135. };
  136. };
  137. };