msm8226-coresight.dtsi 11 KB

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  1. /* Copyright (c) 2013, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. &soc {
  13. tmc_etr: tmc@fc322000 {
  14. compatible = "arm,coresight-tmc";
  15. reg = <0xfc322000 0x1000>,
  16. <0xfc37c000 0x3000>;
  17. reg-names = "tmc-base", "bam-base";
  18. interrupts = <0 166 0>;
  19. interrupt-names = "byte-cntr-irq";
  20. qcom,memory-size = <0x100000>;
  21. coresight-id = <0>;
  22. coresight-name = "coresight-tmc-etr";
  23. coresight-nr-inports = <1>;
  24. coresight-ctis = <&cti0 &cti8>;
  25. };
  26. tpiu: tpiu@fc318000 {
  27. compatible = "arm,coresight-tpiu";
  28. reg = <0xfc318000 0x1000>;
  29. reg-names = "tpiu-base";
  30. coresight-id = <1>;
  31. coresight-name = "coresight-tpiu";
  32. coresight-nr-inports = <1>;
  33. vdd-supply = <&pm8226_l18>;
  34. qcom,vdd-voltage-level = <2950000 2950000>;
  35. qcom,vdd-current-level = <9000 800000>;
  36. vdd-io-supply = <&pm8226_l21>;
  37. qcom,vdd-io-voltage-level = <2950000 2950000>;
  38. qcom,vdd-io-current-level = <6 22000>;
  39. };
  40. replicator: replicator@fc31c000 {
  41. compatible = "qcom,coresight-replicator";
  42. reg = <0xfc31c000 0x1000>;
  43. reg-names = "replicator-base";
  44. coresight-id = <2>;
  45. coresight-name = "coresight-replicator";
  46. coresight-nr-inports = <1>;
  47. coresight-outports = <0 1>;
  48. coresight-child-list = <&tmc_etr &tpiu>;
  49. coresight-child-ports = <0 0>;
  50. };
  51. tmc_etf: tmc@fc307000 {
  52. compatible = "arm,coresight-tmc";
  53. reg = <0xfc307000 0x1000>;
  54. reg-names = "tmc-base";
  55. coresight-id = <3>;
  56. coresight-name = "coresight-tmc-etf";
  57. coresight-nr-inports = <1>;
  58. coresight-outports = <0>;
  59. coresight-child-list = <&replicator>;
  60. coresight-child-ports = <0>;
  61. coresight-default-sink;
  62. coresight-ctis = <&cti0 &cti8>;
  63. };
  64. funnel_merg: funnel@fc31b000 {
  65. compatible = "arm,coresight-funnel";
  66. reg = <0xfc31b000 0x1000>;
  67. reg-names = "funnel-base";
  68. coresight-id = <4>;
  69. coresight-name = "coresight-funnel-merg";
  70. coresight-nr-inports = <2>;
  71. coresight-outports = <0>;
  72. coresight-child-list = <&tmc_etf>;
  73. coresight-child-ports = <0>;
  74. };
  75. funnel_in0: funnel@fc319000 {
  76. compatible = "arm,coresight-funnel";
  77. reg = <0xfc319000 0x1000>;
  78. reg-names = "funnel-base";
  79. coresight-id = <5>;
  80. coresight-name = "coresight-funnel-in0";
  81. coresight-nr-inports = <8>;
  82. coresight-outports = <0>;
  83. coresight-child-list = <&funnel_merg>;
  84. coresight-child-ports = <0>;
  85. };
  86. funnel_in1: funnel@fc31a000 {
  87. compatible = "arm,coresight-funnel";
  88. reg = <0xfc31a000 0x1000>;
  89. reg-names = "funnel-base";
  90. coresight-id = <6>;
  91. coresight-name = "coresight-funnel-in1";
  92. coresight-nr-inports = <8>;
  93. coresight-outports = <0>;
  94. coresight-child-list = <&funnel_merg>;
  95. coresight-child-ports = <1>;
  96. };
  97. funnel_a7ss: funnel@fc345000 {
  98. compatible = "arm,coresight-funnel";
  99. reg = <0xfc345000 0x1000>;
  100. reg-names = "funnel-base";
  101. coresight-id = <7>;
  102. coresight-name = "coresight-funnel-a7ss";
  103. coresight-nr-inports = <4>;
  104. coresight-outports = <0>;
  105. coresight-child-list = <&funnel_in1>;
  106. coresight-child-ports = <5>;
  107. };
  108. funnel_mmss: funnel@fc364000 {
  109. compatible = "arm,coresight-funnel";
  110. reg = <0xfc364000 0x1000>;
  111. reg-names = "funnel-base";
  112. coresight-id = <8>;
  113. coresight-name = "coresight-funnel-mmss";
  114. coresight-nr-inports = <8>;
  115. coresight-outports = <0>;
  116. coresight-child-list = <&funnel_in1>;
  117. coresight-child-ports = <1>;
  118. };
  119. stm: stm@fc321000 {
  120. compatible = "arm,coresight-stm";
  121. reg = <0xfc321000 0x1000>,
  122. <0xfa280000 0x180000>;
  123. reg-names = "stm-base", "stm-data-base";
  124. coresight-id = <9>;
  125. coresight-name = "coresight-stm";
  126. coresight-nr-inports = <0>;
  127. coresight-outports = <0>;
  128. coresight-child-list = <&funnel_in1>;
  129. coresight-child-ports = <7>;
  130. };
  131. etm0: etm@fc33c000 {
  132. compatible = "arm,coresight-etm";
  133. reg = <0xfc33c000 0x1000>;
  134. reg-names = "etm-base";
  135. coresight-id = <10>;
  136. coresight-name = "coresight-etm0";
  137. coresight-nr-inports = <0>;
  138. coresight-outports = <0>;
  139. coresight-child-list = <&funnel_a7ss>;
  140. coresight-child-ports = <0>;
  141. qcom,round-robin;
  142. };
  143. etm1: etm@fc33d000 {
  144. compatible = "arm,coresight-etm";
  145. reg = <0xfc33d000 0x1000>;
  146. reg-names = "etm-base";
  147. coresight-id = <11>;
  148. coresight-name = "coresight-etm1";
  149. coresight-nr-inports = <0>;
  150. coresight-outports = <0>;
  151. coresight-child-list = <&funnel_a7ss>;
  152. coresight-child-ports = <1>;
  153. qcom,round-robin;
  154. };
  155. etm2: etm@fc33e000 {
  156. compatible = "arm,coresight-etm";
  157. reg = <0xfc33e000 0x1000>;
  158. reg-names = "etm-base";
  159. coresight-id = <12>;
  160. coresight-name = "coresight-etm2";
  161. coresight-nr-inports = <0>;
  162. coresight-outports = <0>;
  163. coresight-child-list = <&funnel_a7ss>;
  164. coresight-child-ports = <2>;
  165. qcom,round-robin;
  166. };
  167. etm3: etm@fc33f000 {
  168. compatible = "arm,coresight-etm";
  169. reg = <0xfc33f000 0x1000>;
  170. reg-names = "etm-base";
  171. coresight-id = <13>;
  172. coresight-name = "coresight-etm3";
  173. coresight-nr-inports = <0>;
  174. coresight-outports = <0>;
  175. coresight-child-list = <&funnel_a7ss>;
  176. coresight-child-ports = <3>;
  177. qcom,round-robin;
  178. };
  179. audio_etm0 {
  180. compatible = "qcom,coresight-audio-etm";
  181. coresight-id = <14>;
  182. coresight-name = "coresight-audio-etm0";
  183. coresight-nr-inports = <0>;
  184. coresight-outports = <0>;
  185. coresight-child-list = <&funnel_in0>;
  186. coresight-child-ports = <2>;
  187. };
  188. modem_etm0 {
  189. compatible = "qcom,coresight-modem-etm";
  190. coresight-id = <15>;
  191. coresight-name = "coresight-modem-etm0";
  192. coresight-nr-inports = <0>;
  193. coresight-outports = <0>;
  194. coresight-child-list = <&funnel_in0>;
  195. coresight-child-ports = <1>;
  196. };
  197. wcn_etm0 {
  198. compatible = "qcom,coresight-wcn-etm";
  199. coresight-id = <16>;
  200. coresight-name = "coresight-wcn-etm0";
  201. coresight-nr-inports = <0>;
  202. coresight-outports = <0>;
  203. coresight-child-list = <&funnel_in1>;
  204. coresight-child-ports = <2>;
  205. };
  206. rpm_etm0 {
  207. compatible = "qcom,coresight-rpm-etm";
  208. coresight-id = <17>;
  209. coresight-name = "coresight-rpm-etm0";
  210. coresight-nr-inports = <0>;
  211. coresight-outports = <0>;
  212. coresight-child-list = <&funnel_in0>;
  213. coresight-child-ports = <0>;
  214. };
  215. csr: csr@fc302000 {
  216. compatible = "qcom,coresight-csr";
  217. reg = <0xfc302000 0x1000>;
  218. reg-names = "csr-base";
  219. coresight-id = <18>;
  220. coresight-name = "coresight-csr";
  221. coresight-nr-inports = <0>;
  222. qcom,blk-size = <1>;
  223. };
  224. cti0: cti@fc308000 {
  225. compatible = "arm,coresight-cti";
  226. reg = <0xfc308000 0x1000>;
  227. reg-names = "cti-base";
  228. coresight-id = <19>;
  229. coresight-name = "coresight-cti0";
  230. coresight-nr-inports = <0>;
  231. };
  232. cti1: cti@fc309000 {
  233. compatible = "arm,coresight-cti";
  234. reg = <0xfc309000 0x1000>;
  235. reg-names = "cti-base";
  236. coresight-id = <20>;
  237. coresight-name = "coresight-cti1";
  238. coresight-nr-inports = <0>;
  239. };
  240. cti2: cti@fc30a000 {
  241. compatible = "arm,coresight-cti";
  242. reg = <0xfc30a000 0x1000>;
  243. reg-names = "cti-base";
  244. coresight-id = <21>;
  245. coresight-name = "coresight-cti2";
  246. coresight-nr-inports = <0>;
  247. };
  248. cti3: cti@fc30b000 {
  249. compatible = "arm,coresight-cti";
  250. reg = <0xfc30b000 0x1000>;
  251. reg-names = "cti-base";
  252. coresight-id = <22>;
  253. coresight-name = "coresight-cti3";
  254. coresight-nr-inports = <0>;
  255. };
  256. cti4: cti@fc30c000 {
  257. compatible = "arm,coresight-cti";
  258. reg = <0xfc30c000 0x1000>;
  259. reg-names = "cti-base";
  260. coresight-id = <23>;
  261. coresight-name = "coresight-cti4";
  262. coresight-nr-inports = <0>;
  263. };
  264. cti5: cti@fc30d000 {
  265. compatible = "arm,coresight-cti";
  266. reg = <0xfc30d000 0x1000>;
  267. reg-names = "cti-base";
  268. coresight-id = <24>;
  269. coresight-name = "coresight-cti5";
  270. coresight-nr-inports = <0>;
  271. };
  272. cti6: cti@fc30e000 {
  273. compatible = "arm,coresight-cti";
  274. reg = <0xfc30e000 0x1000>;
  275. reg-names = "cti-base";
  276. coresight-id = <25>;
  277. coresight-name = "coresight-cti6";
  278. coresight-nr-inports = <0>;
  279. };
  280. cti7: cti@fc30f000 {
  281. compatible = "arm,coresight-cti";
  282. reg = <0xfc30f000 0x1000>;
  283. reg-names = "cti-base";
  284. coresight-id = <26>;
  285. coresight-name = "coresight-cti7";
  286. coresight-nr-inports = <0>;
  287. };
  288. cti8: cti@fc310000 {
  289. compatible = "arm,coresight-cti";
  290. reg = <0xfc310000 0x1000>;
  291. reg-names = "cti-base";
  292. coresight-id = <27>;
  293. coresight-name = "coresight-cti8";
  294. coresight-nr-inports = <0>;
  295. };
  296. cti_l2: cti@fc340000 {
  297. compatible = "arm,coresight-cti";
  298. reg = <0xfc340000 0x1000>;
  299. reg-names = "cti-base";
  300. coresight-id = <28>;
  301. coresight-name = "coresight-cti-l2";
  302. coresight-nr-inports = <0>;
  303. };
  304. cti_cpu0: cti@fc341000 {
  305. compatible = "arm,coresight-cti";
  306. reg = <0xfc341000 0x1000>;
  307. reg-names = "cti-base";
  308. coresight-id = <29>;
  309. coresight-name = "coresight-cti-cpu0";
  310. coresight-nr-inports = <0>;
  311. };
  312. cti_cpu1: cti@fc342000 {
  313. compatible = "arm,coresight-cti";
  314. reg = <0xfc342000 0x1000>;
  315. reg-names = "cti-base";
  316. coresight-id = <30>;
  317. coresight-name = "coresight-cti-cpu1";
  318. coresight-nr-inports = <0>;
  319. };
  320. cti_cpu2: cti@fc343000 {
  321. compatible = "arm,coresight-cti";
  322. reg = <0xfc343000 0x1000>;
  323. reg-names = "cti-base";
  324. coresight-id = <31>;
  325. coresight-name = "coresight-cti-cpu2";
  326. coresight-nr-inports = <0>;
  327. };
  328. cti_cpu3: cti@fc344000 {
  329. compatible = "arm,coresight-cti";
  330. reg = <0xfc344000 0x1000>;
  331. reg-names = "cti-base";
  332. coresight-id = <32>;
  333. coresight-name = "coresight-cti-cpu3";
  334. coresight-nr-inports = <0>;
  335. };
  336. cti_video_cpu0: cti@fc348000 {
  337. compatible = "arm,coresight-cti";
  338. reg = <0xfc348000 0x1000>;
  339. reg-names = "cti-base";
  340. coresight-id = <33>;
  341. coresight-name = "coresight-cti-video-cpu0";
  342. coresight-nr-inports = <0>;
  343. };
  344. cti_wcn_cpu0: cti@fc34d000 {
  345. compatible = "arm,coresight-cti";
  346. reg = <0xfc34d000 0x1000>;
  347. reg-names = "cti-base";
  348. coresight-id = <34>;
  349. coresight-name = "coresight-cti-wcn-cpu0";
  350. coresight-nr-inports = <0>;
  351. };
  352. cti_modem_cpu0: cti@fc350000 {
  353. compatible = "arm,coresight-cti";
  354. reg = <0xfc350000 0x1000>;
  355. reg-names = "cti-base";
  356. coresight-id = <35>;
  357. coresight-name = "coresight-cti-modem-cpu0";
  358. coresight-nr-inports = <0>;
  359. };
  360. cti_audio_cpu0: cti@fc354000 {
  361. compatible = "arm,coresight-cti";
  362. reg = <0xfc354000 0x1000>;
  363. reg-names = "cti-base";
  364. coresight-id = <36>;
  365. coresight-name = "coresight-cti-audio-cpu0";
  366. coresight-nr-inports = <0>;
  367. };
  368. cti_rpm_cpu0: cti@fc358000 {
  369. compatible = "arm,coresight-cti";
  370. reg = <0xfc358000 0x1000>;
  371. reg-names = "cti-base";
  372. coresight-id = <37>;
  373. coresight-name = "coresight-cti-rpm-cpu0";
  374. coresight-nr-inports = <0>;
  375. };
  376. hwevent: hwevent@fd828018 {
  377. compatible = "qcom,coresight-hwevent";
  378. reg = <0xfd828018 0x80>,
  379. <0xf9011080 0x80>,
  380. <0xfd4ab160 0x80>,
  381. <0xfc401600 0x80>;
  382. reg-names = "mmss-mux", "apcs-mux", "ppss-mux", "gcc-mux";
  383. coresight-id = <38>;
  384. coresight-name = "coresight-hwevent";
  385. coresight-nr-inports = <0>;
  386. qcom,hwevent-clks = "core_mmss_clk";
  387. };
  388. fuse: fuse@fc4be024 {
  389. compatible = "arm,coresight-fuse";
  390. reg = <0xfc4be024 0x8>;
  391. reg-names = "fuse-base";
  392. coresight-id = <39>;
  393. coresight-name = "coresight-fuse";
  394. coresight-nr-inports = <0>;
  395. };
  396. };