msm-pm8226.dtsi 18 KB

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  1. /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. &spmi_bus {
  13. #address-cells = <1>;
  14. #size-cells = <0>;
  15. interrupt-controller;
  16. #interrupt-cells = <3>;
  17. qcom,pm8226@0 {
  18. spmi-slave-container;
  19. reg = <0x0>;
  20. #address-cells = <1>;
  21. #size-cells = <1>;
  22. pm8226_revid: qcom,revid@100 {
  23. compatible = "qcom,qpnp-revid";
  24. reg = <0x100 0x100>;
  25. };
  26. qcom,power-on@800 {
  27. compatible = "qcom,qpnp-power-on";
  28. reg = <0x800 0x100>;
  29. interrupts = <0x0 0x8 0x0>,
  30. <0x0 0x8 0x1>,
  31. <0x0 0x8 0x4>,
  32. <0x0 0x8 0x5>;
  33. interrupt-names = "kpdpwr", "resin",
  34. "resin-bark", "kpdpwr-resin-bark";
  35. qcom,pon-dbc-delay = <15625>;
  36. qcom,system-reset;
  37. qcom,s3-debounce = <32>;
  38. qcom,s3-src = "kpdpwr-and-resin";
  39. qcom,pon_1 {
  40. qcom,pon-type = <0>;
  41. qcom,support-reset = <1>;
  42. qcom,pull-up = <1>;
  43. qcom,s1-timer = <10256>;
  44. qcom,s2-timer = <2000>;
  45. qcom,s2-type = <1>;
  46. linux,code = <116>;
  47. };
  48. qcom,pon_2 {
  49. qcom,pon-type = <1>;
  50. qcom,pull-up = <1>;
  51. linux,code = <114>;
  52. };
  53. qcom,pon_3 {
  54. qcom,pon-type = <3>;
  55. qcom,support-reset = <1>;
  56. qcom,pull-up = <1>;
  57. qcom,s1-timer = <6720>;
  58. qcom,s2-timer = <2000>;
  59. qcom,s2-type = <7>;
  60. qcom,use-bark;
  61. };
  62. };
  63. pm8226_chg: qcom,charger {
  64. spmi-dev-container;
  65. compatible = "qcom,qpnp-charger";
  66. #address-cells = <1>;
  67. #size-cells = <1>;
  68. status = "disabled";
  69. qcom,vddmax-mv = <4200>;
  70. qcom,vddsafe-mv = <4230>;
  71. qcom,vinmin-mv = <4300>;
  72. qcom,vbatdet-delta-mv = <100>;
  73. qcom,ibatmax-ma = <1500>;
  74. qcom,ibatterm-ma = <100>;
  75. qcom,ibatsafe-ma = <1500>;
  76. qcom,thermal-mitigation = <1500 700 600 325>;
  77. qcom,resume-soc = <99>;
  78. qcom,tchg-mins = <150>;
  79. qcom,chg-vadc = <&pm8226_vadc>;
  80. qcom,chg-adc_tm = <&pm8226_adc_tm>;
  81. qcom,pmic-revid = <&pm8226_revid>;
  82. qcom,ibatmax-warm-ma = <350>;
  83. qcom,warm-bat-decidegc = <450>;
  84. qcom,warm-bat-mv = <4100>;
  85. qcom,cool-bat-decidegc = <100>;
  86. qcom,cool-bat-mv = <4100>;
  87. qcom,ibatmax-cool-ma = <350>;
  88. qcom,chg-iadc = <&pm8226_iadc>;
  89. qcom,ibat-calibration-enabled;
  90. pm8226_chg_chgr: qcom,chgr@1000 {
  91. status = "disabled";
  92. reg = <0x1000 0x100>;
  93. interrupts = <0x0 0x10 0x0>,
  94. <0x0 0x10 0x1>,
  95. <0x0 0x10 0x2>,
  96. <0x0 0x10 0x3>,
  97. <0x0 0x10 0x4>,
  98. <0x0 0x10 0x5>,
  99. <0x0 0x10 0x6>,
  100. <0x0 0x10 0x7>;
  101. interrupt-names = "vbat-det-lo",
  102. "vbat-det-hi",
  103. "chgwdog",
  104. "state-change",
  105. "trkl-chg-on",
  106. "fast-chg-on",
  107. "chg-failed",
  108. "chg-done";
  109. };
  110. qcom,buck@1100 {
  111. status = "disabled";
  112. reg = <0x1100 0x100>;
  113. interrupts = <0x0 0x11 0x0>,
  114. <0x0 0x11 0x1>,
  115. <0x0 0x11 0x2>,
  116. <0x0 0x11 0x3>,
  117. <0x0 0x11 0x4>,
  118. <0x0 0x11 0x5>,
  119. <0x0 0x11 0x6>;
  120. interrupt-names = "vbat-ov",
  121. "vreg-ov",
  122. "overtemp",
  123. "vchg-loop",
  124. "ichg-loop",
  125. "ibat-loop",
  126. "vdd-loop";
  127. };
  128. pm8226_chg_batif: qcom,bat-if@1200 {
  129. status = "disabled";
  130. reg = <0x1200 0x100>;
  131. interrupts = <0x0 0x12 0x0>,
  132. <0x0 0x12 0x1>,
  133. <0x0 0x12 0x2>,
  134. <0x0 0x12 0x3>,
  135. <0x0 0x12 0x4>;
  136. interrupt-names = "batt-pres",
  137. "bat-temp-ok",
  138. "bat-fet-on",
  139. "vcp-on",
  140. "psi";
  141. };
  142. pm8226_chg_boost: qcom,boost@1500 {
  143. status = "disabled";
  144. reg = <0x1500 0x100>;
  145. interrupts = <0x0 0x15 0x0>,
  146. <0x0 0x15 0x1>;
  147. interrupt-names = "boost-pwr-ok",
  148. "limit-error";
  149. };
  150. pm8226_chg_otg: qcom,usb-chgpth@1300 {
  151. status = "disabled";
  152. reg = <0x1300 0x100>;
  153. interrupts = <0 0x13 0x0>,
  154. <0 0x13 0x1>,
  155. <0x0 0x13 0x2>,
  156. <0x0 0x13 0x3>;
  157. interrupt-names = "coarse-det-usb",
  158. "usbin-valid",
  159. "chg-gone",
  160. "usb-ocp";
  161. };
  162. qcom,chg-misc@1600 {
  163. status = "disabled";
  164. reg = <0x1600 0x100>;
  165. };
  166. };
  167. pm8226_bms: qcom,bms {
  168. spmi-dev-container;
  169. compatible = "qcom,qpnp-bms";
  170. #address-cells = <1>;
  171. #size-cells = <1>;
  172. status = "disabled";
  173. qcom,r-sense-uohm = <10000>;
  174. qcom,v-cutoff-uv = <3400000>;
  175. qcom,max-voltage-uv = <4200000>;
  176. qcom,r-conn-mohm = <0>;
  177. qcom,shutdown-soc-valid-limit = <100>;
  178. qcom,adjust-soc-low-threshold = <15>;
  179. qcom,ocv-voltage-high-threshold-uv = <3750000>;
  180. qcom,ocv-voltage-low-threshold-uv = <3650000>;
  181. qcom,low-soc-calculate-soc-threshold = <15>;
  182. qcom,low-voltage-calculate-soc-ms = <1000>;
  183. qcom,low-soc-calculate-soc-ms = <5000>;
  184. qcom,calculate-soc-ms = <20000>;
  185. qcom,chg-term-ua = <100000>;
  186. qcom,batt-type = <0>;
  187. qcom,tm-temp-margin = <5000>;
  188. qcom,low-ocv-correction-limit-uv = <100>;
  189. qcom,high-ocv-correction-limit-uv = <250>;
  190. qcom,hold-soc-est = <3>;
  191. qcom,low-voltage-threshold = <3420000>;
  192. qcom,bms-vadc = <&pm8226_vadc>;
  193. qcom,bms-iadc = <&pm8226_iadc>;
  194. qcom,bms-adc_tm = <&pm8226_adc_tm>;
  195. qcom,batt-pres-status@1208 {
  196. reg = <0x1208 0x1>;
  197. };
  198. qcom,bms-iadc@3800 {
  199. reg = <0x3800 0x100>;
  200. };
  201. qcom,bms-bms@4000 {
  202. reg = <0x4000 0x100>;
  203. interrupts = <0x0 0x40 0x0>,
  204. <0x0 0x40 0x1>,
  205. <0x0 0x40 0x2>,
  206. <0x0 0x40 0x3>,
  207. <0x0 0x40 0x4>,
  208. <0x0 0x40 0x5>,
  209. <0x0 0x40 0x6>,
  210. <0x0 0x40 0x7>;
  211. interrupt-names = "cc_thr",
  212. "ocv_for_r",
  213. "good_ocv",
  214. "charge_begin",
  215. "ocv_thr",
  216. "sw_cc_thr",
  217. "vsense_avg",
  218. "vsense_for_r";
  219. };
  220. };
  221. qcom,leds@a100 {
  222. compatible = "qcom,leds-qpnp";
  223. reg = <0xa100 0x100>;
  224. label = "mpp";
  225. };
  226. qcom,leds@a300 {
  227. compatible = "qcom,leds-qpnp";
  228. reg = <0xa300 0x100>;
  229. label = "mpp";
  230. };
  231. qcom,leds@a500 {
  232. compatible = "qcom,leds-qpnp";
  233. reg = <0xa500 0x100>;
  234. label = "mpp";
  235. };
  236. pm8226_gpios: gpios {
  237. spmi-dev-container;
  238. compatible = "qcom,qpnp-pin";
  239. gpio-controller;
  240. #gpio-cells = <2>;
  241. #address-cells = <1>;
  242. #size-cells = <1>;
  243. label = "pm8226-gpio";
  244. gpio@c000 {
  245. reg = <0xc000 0x100>;
  246. qcom,pin-num = <1>;
  247. };
  248. gpio@c100 {
  249. reg = <0xc100 0x100>;
  250. qcom,pin-num = <2>;
  251. };
  252. gpio@c200 {
  253. reg = <0xc200 0x100>;
  254. qcom,pin-num = <3>;
  255. };
  256. gpio@c300 {
  257. reg = <0xc300 0x100>;
  258. qcom,pin-num = <4>;
  259. };
  260. gpio@c400 {
  261. reg = <0xc400 0x100>;
  262. qcom,pin-num = <5>;
  263. };
  264. gpio@c500 {
  265. reg = <0xc500 0x100>;
  266. qcom,pin-num = <6>;
  267. };
  268. gpio@c600 {
  269. reg = <0xc600 0x100>;
  270. qcom,pin-num = <7>;
  271. };
  272. gpio@c700 {
  273. reg = <0xc700 0x100>;
  274. qcom,pin-num = <8>;
  275. };
  276. };
  277. pm8226_mpps: mpps {
  278. spmi-dev-container;
  279. compatible = "qcom,qpnp-pin";
  280. gpio-controller;
  281. #gpio-cells = <2>;
  282. #address-cells = <1>;
  283. #size-cells = <1>;
  284. label = "pm8226-mpp";
  285. mpp@a000 {
  286. reg = <0xa000 0x100>;
  287. qcom,pin-num = <1>;
  288. };
  289. mpp@a100 {
  290. reg = <0xa100 0x100>;
  291. qcom,pin-num = <2>;
  292. };
  293. mpp@a200 {
  294. reg = <0xa200 0x100>;
  295. qcom,pin-num = <3>;
  296. };
  297. mpp@a300 {
  298. reg = <0xa300 0x100>;
  299. qcom,pin-num = <4>;
  300. };
  301. mpp@a400 {
  302. reg = <0xa400 0x100>;
  303. qcom,pin-num = <5>;
  304. };
  305. mpp@a500 {
  306. reg = <0xa500 0x100>;
  307. qcom,pin-num = <6>;
  308. };
  309. mpp@a600 {
  310. reg = <0xa600 0x100>;
  311. qcom,pin-num = <7>;
  312. };
  313. mpp@a700 {
  314. reg = <0xa700 0x100>;
  315. qcom,pin-num = <8>;
  316. };
  317. };
  318. pm8226_vadc: vadc@3100 {
  319. compatible = "qcom,qpnp-vadc";
  320. reg = <0x3100 0x100>;
  321. #address-cells = <1>;
  322. #size-cells = <0>;
  323. interrupts = <0x0 0x31 0x0>;
  324. interrupt-names = "eoc-int-en-set";
  325. qcom,adc-bit-resolution = <15>;
  326. qcom,adc-vdd-reference = <1800>;
  327. qcom,vadc-poll-eoc;
  328. qcom,pmic-revid = <&pm8226_revid>;
  329. chan@8 {
  330. label = "die_temp";
  331. reg = <8>;
  332. qcom,decimation = <0>;
  333. qcom,pre-div-channel-scaling = <0>;
  334. qcom,calibration-type = "absolute";
  335. qcom,scale-function = <3>;
  336. qcom,hw-settle-time = <0>;
  337. qcom,fast-avg-setup = <0>;
  338. };
  339. chan@9 {
  340. label = "ref_625mv";
  341. reg = <9>;
  342. qcom,decimation = <0>;
  343. qcom,pre-div-channel-scaling = <0>;
  344. qcom,calibration-type = "absolute";
  345. qcom,scale-function = <0>;
  346. qcom,hw-settle-time = <0>;
  347. qcom,fast-avg-setup = <0>;
  348. };
  349. chan@a {
  350. label = "ref_1250v";
  351. reg = <0xa>;
  352. qcom,decimation = <0>;
  353. qcom,pre-div-channel-scaling = <0>;
  354. qcom,calibration-type = "absolute";
  355. qcom,scale-function = <0>;
  356. qcom,hw-settle-time = <0>;
  357. qcom,fast-avg-setup = <0>;
  358. };
  359. chan@c {
  360. label = "ref_buf_625mv";
  361. reg = <0xc>;
  362. qcom,decimation = <0>;
  363. qcom,pre-div-channel-scaling = <0>;
  364. qcom,calibration-type = "absolute";
  365. qcom,scale-function = <0>;
  366. qcom,hw-settle-time = <0>;
  367. qcom,fast-avg-setup = <0>;
  368. };
  369. };
  370. pm8226_iadc: iadc@3600 {
  371. compatible = "qcom,qpnp-iadc";
  372. reg = <0x3600 0x100>,
  373. <0x12f1 0x1>;
  374. reg-names = "iadc-base", "batt-id-trim-cnst-rds";
  375. #address-cells = <1>;
  376. #size-cells = <0>;
  377. interrupts = <0x0 0x36 0x0>;
  378. interrupt-names = "eoc-int-en-set";
  379. qcom,adc-bit-resolution = <16>;
  380. qcom,adc-vdd-reference = <1800>;
  381. qcom,iadc-vadc = <&pm8226_vadc>;
  382. qcom,iadc-poll-eoc;
  383. qcom,use-default-rds-trim = <2>;
  384. qcom,pmic-revid = <&pm8226_revid>;
  385. chan@0 {
  386. label = "internal_rsense";
  387. reg = <0>;
  388. qcom,decimation = <0>;
  389. qcom,fast-avg-setup = <0>;
  390. };
  391. chan@1 {
  392. label = "external_rsense";
  393. reg = <1>;
  394. qcom,decimation = <0>;
  395. qcom,fast-avg-setup = <0>;
  396. };
  397. };
  398. pm8226_adc_tm: vadc@3400 {
  399. compatible = "qcom,qpnp-adc-tm";
  400. reg = <0x3400 0x100>;
  401. #address-cells = <1>;
  402. #size-cells = <0>;
  403. interrupts = <0x0 0x34 0x0>,
  404. <0x0 0x34 0x3>,
  405. <0x0 0x34 0x4>;
  406. interrupt-names = "eoc-int-en-set",
  407. "high-thr-en-set",
  408. "low-thr-en-set";
  409. qcom,adc-bit-resolution = <15>;
  410. qcom,adc-vdd-reference = <1800>;
  411. qcom,adc_tm-vadc = <&pm8226_vadc>;
  412. };
  413. qcom,temp-alarm@2400 {
  414. compatible = "qcom,qpnp-temp-alarm";
  415. reg = <0x2400 0x100>;
  416. interrupts = <0x0 0x24 0x0>;
  417. label = "pm8226_tz";
  418. qcom,channel-num = <8>;
  419. qcom,threshold-set = <0>;
  420. qcom,temp_alarm-vadc = <&pm8226_vadc>;
  421. };
  422. qcom,pm8226_rtc {
  423. spmi-dev-container;
  424. compatible = "qcom,qpnp-rtc";
  425. #address-cells = <1>;
  426. #size-cells = <1>;
  427. qcom,qpnp-rtc-write = <0>;
  428. qcom,qpnp-rtc-alarm-pwrup = <0>;
  429. qcom,pm8226_rtc_rw@6000 {
  430. reg = <0x6000 0x100>;
  431. };
  432. qcom,pm8226_rtc_alarm@6100 {
  433. reg = <0x6100 0x100>;
  434. interrupts = <0x0 0x61 0x1>;
  435. };
  436. };
  437. };
  438. qcom,pm8226@1 {
  439. spmi-slave-container;
  440. reg = <0x1>;
  441. #address-cells = <1>;
  442. #size-cells = <1>;
  443. regulator@1400 {
  444. regulator-name = "8226_s1";
  445. spmi-dev-container;
  446. #address-cells = <1>;
  447. #size-cells = <1>;
  448. compatible = "qcom,qpnp-regulator";
  449. reg = <0x1400 0x300>;
  450. status = "disabled";
  451. qcom,ctl@1400 {
  452. reg = <0x1400 0x100>;
  453. };
  454. qcom,ps@1500 {
  455. reg = <0x1500 0x100>;
  456. };
  457. qcom,freq@1600 {
  458. reg = <0x1600 0x100>;
  459. };
  460. };
  461. regulator@1700 {
  462. regulator-name = "8226_s2";
  463. spmi-dev-container;
  464. #address-cells = <1>;
  465. #size-cells = <1>;
  466. compatible = "qcom,qpnp-regulator";
  467. reg = <0x1700 0x300>;
  468. status = "disabled";
  469. qcom,ctl@1700 {
  470. reg = <0x1700 0x100>;
  471. };
  472. qcom,ps@1800 {
  473. reg = <0x1800 0x100>;
  474. };
  475. qcom,freq@1900 {
  476. reg = <0x1900 0x100>;
  477. };
  478. };
  479. regulator@1a00 {
  480. regulator-name = "8226_s3";
  481. spmi-dev-container;
  482. #address-cells = <1>;
  483. #size-cells = <1>;
  484. compatible = "qcom,qpnp-regulator";
  485. reg = <0x1a00 0x300>;
  486. status = "disabled";
  487. qcom,ctl@1a00 {
  488. reg = <0x1a00 0x100>;
  489. };
  490. qcom,ps@1b00 {
  491. reg = <0x1b00 0x100>;
  492. };
  493. qcom,freq@1c00 {
  494. reg = <0x1c00 0x100>;
  495. };
  496. };
  497. regulator@1d00 {
  498. regulator-name = "8226_s4";
  499. spmi-dev-container;
  500. #address-cells = <1>;
  501. #size-cells = <1>;
  502. compatible = "qcom,qpnp-regulator";
  503. reg = <0x1d00 0x300>;
  504. status = "disabled";
  505. qcom,ctl@1d00 {
  506. reg = <0x1d00 0x100>;
  507. };
  508. qcom,ps@1e00 {
  509. reg = <0x1e00 0x100>;
  510. };
  511. qcom,freq@1f00 {
  512. reg = <0x1f00 0x100>;
  513. };
  514. };
  515. regulator@2000 {
  516. regulator-name = "8226_s5";
  517. spmi-dev-container;
  518. #address-cells = <1>;
  519. #size-cells = <1>;
  520. compatible = "qcom,qpnp-regulator";
  521. reg = <0x2000 0x300>;
  522. status = "disabled";
  523. qcom,ctl@2000 {
  524. reg = <0x2000 0x100>;
  525. };
  526. qcom,ps@2100 {
  527. reg = <0x2100 0x100>;
  528. };
  529. qcom,freq@2200 {
  530. reg = <0x2200 0x100>;
  531. };
  532. };
  533. regulator@4000 {
  534. regulator-name = "8226_l1";
  535. reg = <0x4000 0x100>;
  536. compatible = "qcom,qpnp-regulator";
  537. status = "disabled";
  538. };
  539. regulator@4100 {
  540. regulator-name = "8226_l2";
  541. reg = <0x4100 0x100>;
  542. compatible = "qcom,qpnp-regulator";
  543. status = "disabled";
  544. };
  545. regulator@4200 {
  546. regulator-name = "8226_l3";
  547. reg = <0x4200 0x100>;
  548. compatible = "qcom,qpnp-regulator";
  549. status = "disabled";
  550. };
  551. regulator@4300 {
  552. regulator-name = "8226_l4";
  553. reg = <0x4300 0x100>;
  554. compatible = "qcom,qpnp-regulator";
  555. status = "disabled";
  556. };
  557. regulator@4400 {
  558. regulator-name = "8226_l5";
  559. reg = <0x4400 0x100>;
  560. compatible = "qcom,qpnp-regulator";
  561. status = "disabled";
  562. };
  563. regulator@4500 {
  564. regulator-name = "8226_l6";
  565. reg = <0x4500 0x100>;
  566. compatible = "qcom,qpnp-regulator";
  567. status = "disabled";
  568. };
  569. regulator@4600 {
  570. regulator-name = "8226_l7";
  571. reg = <0x4600 0x100>;
  572. compatible = "qcom,qpnp-regulator";
  573. status = "disabled";
  574. };
  575. regulator@4700 {
  576. regulator-name = "8226_l8";
  577. reg = <0x4700 0x100>;
  578. compatible = "qcom,qpnp-regulator";
  579. status = "disabled";
  580. };
  581. regulator@4800 {
  582. regulator-name = "8226_l9";
  583. reg = <0x4800 0x100>;
  584. compatible = "qcom,qpnp-regulator";
  585. status = "disabled";
  586. };
  587. regulator@4900 {
  588. regulator-name = "8226_l10";
  589. reg = <0x4900 0x100>;
  590. compatible = "qcom,qpnp-regulator";
  591. status = "disabled";
  592. };
  593. regulator@4b00 {
  594. regulator-name = "8226_l12";
  595. reg = <0x4b00 0x100>;
  596. compatible = "qcom,qpnp-regulator";
  597. status = "disabled";
  598. };
  599. regulator@4d00 {
  600. regulator-name = "8226_l14";
  601. reg = <0x4d00 0x100>;
  602. compatible = "qcom,qpnp-regulator";
  603. status = "disabled";
  604. };
  605. regulator@4e00 {
  606. regulator-name = "8226_l15";
  607. reg = <0x4e00 0x100>;
  608. compatible = "qcom,qpnp-regulator";
  609. status = "disabled";
  610. };
  611. regulator@4f00 {
  612. regulator-name = "8226_l16";
  613. reg = <0x4f00 0x100>;
  614. compatible = "qcom,qpnp-regulator";
  615. status = "disabled";
  616. };
  617. regulator@5000 {
  618. regulator-name = "8226_l17";
  619. reg = <0x5000 0x100>;
  620. compatible = "qcom,qpnp-regulator";
  621. status = "disabled";
  622. };
  623. regulator@5100 {
  624. regulator-name = "8226_l18";
  625. reg = <0x5100 0x100>;
  626. compatible = "qcom,qpnp-regulator";
  627. status = "disabled";
  628. };
  629. regulator@5200 {
  630. regulator-name = "8226_l19";
  631. reg = <0x5200 0x100>;
  632. compatible = "qcom,qpnp-regulator";
  633. status = "disabled";
  634. };
  635. regulator@5300 {
  636. regulator-name = "8226_l20";
  637. reg = <0x5300 0x100>;
  638. compatible = "qcom,qpnp-regulator";
  639. status = "disabled";
  640. };
  641. regulator@5400 {
  642. regulator-name = "8226_l21";
  643. reg = <0x5400 0x100>;
  644. compatible = "qcom,qpnp-regulator";
  645. status = "disabled";
  646. };
  647. regulator@5500 {
  648. regulator-name = "8226_l22";
  649. reg = <0x5500 0x100>;
  650. compatible = "qcom,qpnp-regulator";
  651. status = "disabled";
  652. };
  653. regulator@5600 {
  654. regulator-name = "8226_l23";
  655. reg = <0x5600 0x100>;
  656. compatible = "qcom,qpnp-regulator";
  657. status = "disabled";
  658. };
  659. regulator@5700 {
  660. regulator-name = "8226_l24";
  661. reg = <0x5700 0x100>;
  662. compatible = "qcom,qpnp-regulator";
  663. status = "disabled";
  664. };
  665. regulator@5900 {
  666. regulator-name = "8226_l26";
  667. reg = <0x5900 0x100>;
  668. compatible = "qcom,qpnp-regulator";
  669. status = "disabled";
  670. };
  671. regulator@5a00 {
  672. regulator-name = "8226_l27";
  673. reg = <0x5a00 0x100>;
  674. compatible = "qcom,qpnp-regulator";
  675. status = "disabled";
  676. };
  677. regulator@5b00 {
  678. regulator-name = "8226_l28";
  679. reg = <0x5b00 0x100>;
  680. compatible = "qcom,qpnp-regulator";
  681. status = "disabled";
  682. };
  683. qcom,leds@d800 {
  684. compatible = "qcom,leds-qpnp";
  685. reg = <0xd800 0x100>;
  686. label = "wled";
  687. };
  688. pwm@b100 {
  689. compatible = "qcom,qpnp-pwm";
  690. reg = <0xb100 0x100>,
  691. <0xb042 0x7e>;
  692. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  693. qcom,channel-id = <0>;
  694. };
  695. pwm@b200 {
  696. compatible = "qcom,qpnp-pwm";
  697. reg = <0xb200 0x100>,
  698. <0xb042 0x7e>;
  699. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  700. qcom,channel-id = <1>;
  701. };
  702. pwm@b300 {
  703. compatible = "qcom,qpnp-pwm";
  704. reg = <0xb300 0x100>,
  705. <0xb042 0x7e>;
  706. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  707. qcom,channel-id = <2>;
  708. };
  709. pwm@b400 {
  710. compatible = "qcom,qpnp-pwm";
  711. reg = <0xb400 0x100>,
  712. <0xb042 0x7e>;
  713. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  714. qcom,channel-id = <3>;
  715. };
  716. pwm@b500 {
  717. compatible = "qcom,qpnp-pwm";
  718. reg = <0xb500 0x100>,
  719. <0xb042 0x7e>;
  720. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  721. qcom,channel-id = <4>;
  722. };
  723. pwm@b600 {
  724. compatible = "qcom,qpnp-pwm";
  725. reg = <0xb600 0x100>,
  726. <0xb042 0x7e>;
  727. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  728. qcom,channel-id = <5>;
  729. };
  730. regulator@8000 {
  731. regulator-name = "8226_lvs1";
  732. reg = <0x8000 0x100>;
  733. compatible = "qcom,qpnp-regulator";
  734. status = "disabled";
  735. };
  736. qcom,vibrator@c000 {
  737. compatible = "qcom,qpnp-vibrator";
  738. reg = <0xc000 0x100>;
  739. label = "vibrator";
  740. status = "disabled";
  741. };
  742. qcom,leds@d300 {
  743. compatible = "qcom,leds-qpnp";
  744. status = "okay";
  745. reg = <0xd300 0x100>;
  746. label = "flash";
  747. flash-boost-supply = <&pm8226_chg_boost>;
  748. flash-wa-supply = <&pm8226_chg_chgr>;
  749. pm8226_flash0: qcom,flash_0 {
  750. qcom,max-current = <1000>;
  751. qcom,default-state = "off";
  752. qcom,headroom = <3>;
  753. qcom,duration = <1280>;
  754. qcom,clamp-curr = <200>;
  755. qcom,startup-dly = <3>;
  756. qcom,safety-timer;
  757. label = "flash";
  758. linux,default-trigger =
  759. "flash0_trigger";
  760. qcom,id = <1>;
  761. linux,name = "led:flash_0";
  762. qcom,current = <625>;
  763. };
  764. pm8226_torch: qcom,flash_torch {
  765. qcom,max-current = <200>;
  766. qcom,default-state = "off";
  767. linux,default-trigger =
  768. "torch_trigger";
  769. label = "flash";
  770. qcom,id = <1>;
  771. linux,name = "led:flash_torch";
  772. qcom,current = <120>;
  773. qcom,torch-enable;
  774. };
  775. };
  776. };
  777. };