msm-iommu-v1.dtsi 20 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144
  1. /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. &soc {
  13. jpeg_iommu: qcom,iommu@fda64000 {
  14. compatible = "qcom,msm-smmu-v1";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. ranges;
  18. reg = <0xfda64000 0x10000>;
  19. reg-names = "iommu_base";
  20. interrupts = <0 67 0>;
  21. qcom,needs-alt-core-clk;
  22. label = "jpeg_iommu";
  23. status = "disabled";
  24. qcom,msm-bus,name = "jpeg_ebi";
  25. qcom,msm-bus,num-cases = <2>;
  26. qcom,msm-bus,num-paths = <1>;
  27. qcom,msm-bus,vectors-KBps =
  28. <62 512 0 0>,
  29. <62 512 0 1000>;
  30. qcom,iommu-pmu-ngroups = <1>;
  31. qcom,iommu-pmu-ncounters = <8>;
  32. qcom,iommu-pmu-event-classes = <0x00
  33. 0x01
  34. 0x08
  35. 0x09
  36. 0x0A
  37. 0x10
  38. 0x11
  39. 0x12
  40. 0x80
  41. 0x81
  42. 0x82
  43. 0x83
  44. 0x90
  45. 0x91
  46. 0x92
  47. 0xb0
  48. 0xb1>;
  49. qcom,iommu-bfb-regs = <0x204c
  50. 0x2050
  51. 0x2514
  52. 0x2540
  53. 0x256c
  54. 0x2314
  55. 0x2394
  56. 0x2414
  57. 0x20ac
  58. 0x215c
  59. 0x220c
  60. 0x2008
  61. 0x200c
  62. 0x2010
  63. 0x2014>;
  64. qcom,iommu-bfb-data = <0x0000ffff
  65. 0x0
  66. 0x4
  67. 0x4
  68. 0x0
  69. 0x0
  70. 0x10
  71. 0x50
  72. 0x0
  73. 0x10
  74. 0x20
  75. 0x0
  76. 0x0
  77. 0x0
  78. 0x0>;
  79. qcom,iommu-ctx@fda6c000 {
  80. compatible = "qcom,msm-smmu-v1-ctx";
  81. reg = <0xfda6c000 0x1000>;
  82. interrupts = <0 70 0>;
  83. qcom,iommu-ctx-sids = <0>;
  84. label = "jpeg_enc0";
  85. };
  86. qcom,iommu-ctx@fda6d000 {
  87. compatible = "qcom,msm-smmu-v1-ctx";
  88. reg = <0xfda6d000 0x1000>;
  89. interrupts = <0 70 0>;
  90. qcom,iommu-ctx-sids = <1>;
  91. label = "jpeg_enc1";
  92. };
  93. qcom,iommu-ctx@fda6e000 {
  94. compatible = "qcom,msm-smmu-v1-ctx";
  95. reg = <0xfda6e000 0x1000>;
  96. interrupts = <0 70 0>;
  97. qcom,iommu-ctx-sids = <2>;
  98. label = "jpeg_dec";
  99. };
  100. };
  101. mdp_iommu: qcom,iommu@fd928000 {
  102. compatible = "qcom,msm-smmu-v1";
  103. #address-cells = <1>;
  104. #size-cells = <1>;
  105. ranges;
  106. reg = <0xfd928000 0x10000>;
  107. reg-names = "iommu_base";
  108. interrupts = <0 73 0>;
  109. qcom,iommu-secure-id = <1>;
  110. label = "mdp_iommu";
  111. qcom,msm-bus,name = "mdp_ebi";
  112. qcom,msm-bus,num-cases = <2>;
  113. qcom,msm-bus,num-paths = <1>;
  114. qcom,msm-bus,vectors-KBps =
  115. <22 512 0 0>,
  116. <22 512 0 1000>;
  117. status = "disabled";
  118. qcom,iommu-pmu-ngroups = <1>;
  119. qcom,iommu-pmu-ncounters = <8>;
  120. qcom,iommu-pmu-event-classes = <0x00
  121. 0x01
  122. 0x08
  123. 0x09
  124. 0x0A
  125. 0x10
  126. 0x11
  127. 0x12
  128. 0x80
  129. 0x81
  130. 0x82
  131. 0x83
  132. 0x90
  133. 0x91
  134. 0x92
  135. 0xb0
  136. 0xb1>;
  137. qcom,iommu-bfb-regs = <0x204c
  138. 0x2050
  139. 0x2514
  140. 0x2540
  141. 0x256c
  142. 0x20ac
  143. 0x215c
  144. 0x220c
  145. 0x2314
  146. 0x2394
  147. 0x2414
  148. 0x2008
  149. 0x200c
  150. 0x2010
  151. 0x2014
  152. 0x2018
  153. 0x201c
  154. 0x2020>;
  155. qcom,iommu-bfb-data = <0xffffffff
  156. 0x0
  157. 0x00000004
  158. 0x00000010
  159. 0x00000000
  160. 0x00000000
  161. 0x00000034
  162. 0x00000044
  163. 0x0
  164. 0x34
  165. 0x74
  166. 0x0
  167. 0x0
  168. 0x0
  169. 0x0
  170. 0x0
  171. 0x0
  172. 0x0>;
  173. qcom,iommu-ctx@fd930000 {
  174. compatible = "qcom,msm-smmu-v1-ctx";
  175. reg = <0xfd930000 0x1000>;
  176. interrupts = <0 47 0>;
  177. qcom,iommu-ctx-sids = <0>;
  178. label = "mdp_0";
  179. };
  180. qcom,iommu-ctx@fd931000 {
  181. compatible = "qcom,msm-smmu-v1-ctx";
  182. reg = <0xfd931000 0x1000>;
  183. interrupts = <0 47 0>, <0 46 0>;
  184. qcom,iommu-ctx-sids = <1>;
  185. label = "mdp_1";
  186. qcom,secure-context;
  187. };
  188. qcom,iommu-ctx@fd932000 {
  189. compatible = "qcom,msm-smmu-v1-ctx";
  190. reg = <0xfd932000 0x1000>;
  191. interrupts = <0 47 0>, <0 46 0>;
  192. qcom,iommu-ctx-sids = <>;
  193. label = "mdp_2";
  194. qcom,secure-context;
  195. };
  196. };
  197. venus_iommu: qcom,iommu@fdc84000 {
  198. compatible = "qcom,msm-smmu-v1";
  199. #address-cells = <1>;
  200. #size-cells = <1>;
  201. ranges;
  202. reg = <0xfdc84000 0x10000
  203. 0xfdce0004 0x4>;
  204. reg-names = "iommu_base", "clk_base";
  205. interrupts = <0 45 0>;
  206. qcom,iommu-secure-id = <0>;
  207. qcom,needs-alt-core-clk;
  208. label = "venus_iommu";
  209. qcom,msm-bus,name = "venus_ebi";
  210. qcom,msm-bus,num-cases = <2>;
  211. qcom,msm-bus,num-paths = <1>;
  212. qcom,msm-bus,vectors-KBps =
  213. <63 512 0 0>,
  214. <63 512 0 1000>;
  215. status = "disabled";
  216. qcom,iommu-pmu-ngroups = <1>;
  217. qcom,iommu-pmu-ncounters = <8>;
  218. qcom,iommu-pmu-event-classes = <0x00
  219. 0x01
  220. 0x08
  221. 0x09
  222. 0x0A
  223. 0x10
  224. 0x11
  225. 0x12
  226. 0x80
  227. 0x81
  228. 0x82
  229. 0x83
  230. 0x90
  231. 0x91
  232. 0x92
  233. 0xb0
  234. 0xb1>;
  235. qcom,iommu-bfb-regs = <0x204c
  236. 0x2050
  237. 0x2514
  238. 0x2540
  239. 0x256c
  240. 0x20ac
  241. 0x215c
  242. 0x220c
  243. 0x2314
  244. 0x2394
  245. 0x2414
  246. 0x2008
  247. 0x200c
  248. 0x2010
  249. 0x2014
  250. 0x2018
  251. 0x201c
  252. 0x2020
  253. 0x2024
  254. 0x2028
  255. 0x202c
  256. 0x2030
  257. 0x2034
  258. 0x2038>;
  259. qcom,iommu-bfb-data = <0xffffffff
  260. 0xffffffff
  261. 0x00000004
  262. 0x00000008
  263. 0x00000000
  264. 0x00000000
  265. 0x00000094
  266. 0x000000b4
  267. 0x0
  268. 0x94
  269. 0x114
  270. 0x0
  271. 0x0
  272. 0x0
  273. 0x0
  274. 0x0
  275. 0x0
  276. 0x0
  277. 0x0
  278. 0x0
  279. 0x0
  280. 0x0
  281. 0x0
  282. 0x0>;
  283. venus_ns: qcom,iommu-ctx@fdc8c000 {
  284. compatible = "qcom,msm-smmu-v1-ctx";
  285. reg = <0xfdc8c000 0x1000>;
  286. interrupts = <0 42 0>;
  287. qcom,iommu-ctx-sids = <0 1 2 3 4 5>;
  288. label = "venus_ns";
  289. };
  290. venus_cp: qcom,iommu-ctx@fdc8d000 {
  291. compatible = "qcom,msm-smmu-v1-ctx";
  292. reg = <0xfdc8d000 0x1000>;
  293. interrupts = <0 42 0>, <0 43 0>;
  294. qcom,iommu-ctx-sids = <0x80 0x81 0x82 0x83 0x84 0x85>;
  295. label = "venus_cp";
  296. qcom,secure-context;
  297. };
  298. venus_fw: qcom,iommu-ctx@fdc8e000 {
  299. compatible = "qcom,msm-smmu-v1-ctx";
  300. reg = <0xfdc8e000 0x1000>;
  301. interrupts = <0 42 0>, <0 43 0>;
  302. qcom,iommu-ctx-sids = <0xc0 0xc6>;
  303. label = "venus_fw";
  304. qcom,secure-context;
  305. };
  306. };
  307. kgsl_iommu: qcom,iommu@fdb10000 {
  308. compatible = "qcom,msm-smmu-v1";
  309. #address-cells = <1>;
  310. #size-cells = <1>;
  311. ranges;
  312. reg = <0xfdb10000 0x10000>;
  313. reg-names = "iommu_base";
  314. interrupts = <0 38 0>;
  315. label = "kgsl_iommu";
  316. qcom,msm-bus,name = "kgsl_ebi";
  317. qcom,msm-bus,num-cases = <2>;
  318. qcom,msm-bus,num-paths = <1>;
  319. qcom,msm-bus,vectors-KBps =
  320. <26 512 0 0>,
  321. <26 512 0 1000>;
  322. status = "disabled";
  323. qcom,iommu-pmu-ngroups = <1>;
  324. qcom,iommu-pmu-ncounters = <8>;
  325. qcom,iommu-pmu-event-classes = <0x00
  326. 0x01
  327. 0x08
  328. 0x09
  329. 0x0A
  330. 0x10
  331. 0x11
  332. 0x12
  333. 0x80
  334. 0x81
  335. 0x82
  336. 0x83
  337. 0x90
  338. 0x91
  339. 0x92
  340. 0xb0
  341. 0xb1>;
  342. qcom,iommu-bfb-regs = <0x204c
  343. 0x2050
  344. 0x2514
  345. 0x2540
  346. 0x256c
  347. 0x20ac
  348. 0x215c
  349. 0x220c
  350. 0x2314
  351. 0x2394
  352. 0x2414
  353. 0x2008>;
  354. qcom,iommu-bfb-data = <0x00000003
  355. 0x0
  356. 0x00000004
  357. 0x00000010
  358. 0x00000000
  359. 0x00000000
  360. 0x00000001
  361. 0x00000021
  362. 0x0
  363. 0x1
  364. 0x81
  365. 0x0>;
  366. qcom,iommu-ctx@fdb18000 {
  367. compatible = "qcom,msm-smmu-v1-ctx";
  368. reg = <0xfdb18000 0x1000>;
  369. interrupts = <0 241 0>;
  370. qcom,iommu-ctx-sids = <0>;
  371. label = "gfx3d_user";
  372. };
  373. qcom,iommu-ctx@fdb19000 {
  374. compatible = "qcom,msm-smmu-v1-ctx";
  375. reg = <0xfdb19000 0x1000>;
  376. interrupts = <0 241 0>;
  377. qcom,iommu-ctx-sids = <1>;
  378. label = "gfx3d_priv";
  379. };
  380. qcom,iommu-ctx@fdb1a000 {
  381. compatible = "qcom,msm-smmu-v1-ctx";
  382. reg = <0xfdb1a000 0x1000>;
  383. interrupts = <0 241 0>;
  384. qcom,iommu-ctx-sids = <2>;
  385. label = "gfx3d_spare";
  386. };
  387. };
  388. vfe_iommu: qcom,iommu@fda44000 {
  389. compatible = "qcom,msm-smmu-v1";
  390. #address-cells = <1>;
  391. #size-cells = <1>;
  392. ranges;
  393. reg = <0xfda44000 0x10000>;
  394. reg-names = "iommu_base";
  395. interrupts = <0 62 0>;
  396. qcom,needs-alt-core-clk;
  397. label = "vfe_iommu";
  398. qcom,msm-bus,name = "vfe_ebi";
  399. qcom,msm-bus,num-cases = <2>;
  400. qcom,msm-bus,num-paths = <1>;
  401. qcom,msm-bus,vectors-KBps =
  402. <29 512 0 0>,
  403. <29 512 0 1000>;
  404. status = "disabled";
  405. qcom,iommu-pmu-ngroups = <1>;
  406. qcom,iommu-pmu-ncounters = <8>;
  407. qcom,iommu-pmu-event-classes = <0x00
  408. 0x01
  409. 0x08
  410. 0x09
  411. 0x0A
  412. 0x10
  413. 0x11
  414. 0x12
  415. 0x80
  416. 0x81
  417. 0x82
  418. 0x83
  419. 0x90
  420. 0x91
  421. 0x92
  422. 0xb0
  423. 0xb1>;
  424. qcom,iommu-bfb-regs = <0x204c
  425. 0x2050
  426. 0x2514
  427. 0x2540
  428. 0x256c
  429. 0x2314
  430. 0x2394
  431. 0x2414
  432. 0x20ac
  433. 0x215c
  434. 0x220c
  435. 0x2008
  436. 0x200c
  437. 0x2010
  438. 0x2014
  439. 0x2018
  440. 0x201c
  441. 0x2020>;
  442. qcom,iommu-bfb-data = <0xffffffff
  443. 0x00000000
  444. 0x4
  445. 0x8
  446. 0x0
  447. 0x0
  448. 0x20
  449. 0x78
  450. 0x0
  451. 0x20
  452. 0x36
  453. 0x0
  454. 0x0
  455. 0x0
  456. 0x0
  457. 0x0
  458. 0x0
  459. 0x0>;
  460. qcom,iommu-ctx@fda4c000 {
  461. compatible = "qcom,msm-smmu-v1-ctx";
  462. reg = <0xfda4c000 0x1000>;
  463. interrupts = <0 65 0>;
  464. qcom,iommu-ctx-sids = <0>;
  465. label = "vfe0";
  466. };
  467. qcom,iommu-ctx@fda4d000 {
  468. compatible = "qcom,msm-smmu-v1-ctx";
  469. reg = <0xfda4d000 0x1000>;
  470. interrupts = <0 65 0>;
  471. qcom,iommu-ctx-sids = <1>;
  472. label = "vfe1";
  473. };
  474. qcom,iommu-ctx@fda4e000 {
  475. compatible = "qcom,msm-smmu-v1-ctx";
  476. reg = <0xfda4e000 0x1000>;
  477. interrupts = <0 65 0>;
  478. qcom,iommu-ctx-sids = <2>;
  479. label = "cpp";
  480. };
  481. };
  482. copss_iommu: qcom,iommu@f9bc4000 {
  483. compatible = "qcom,msm-smmu-v1";
  484. #address-cells = <1>;
  485. #size-cells = <1>;
  486. ranges;
  487. reg = <0xf9bc4000 0x10000>;
  488. reg-names = "iommu_base";
  489. interrupts = <0 153 0>;
  490. label = "copss_iommu";
  491. qcom,msm-bus,name = "copss_ebi";
  492. qcom,msm-bus,num-cases = <2>;
  493. qcom,msm-bus,num-paths = <1>;
  494. qcom,msm-bus,vectors-KBps =
  495. <88 512 0 0>,
  496. <88 512 0 1000>;
  497. status = "disabled";
  498. qcom,iommu-pmu-ngroups = <1>;
  499. qcom,iommu-pmu-ncounters = <8>;
  500. qcom,iommu-pmu-event-classes = <0x00
  501. 0x01
  502. 0x08
  503. 0x09
  504. 0x0a
  505. 0x10
  506. 0x11
  507. 0x12
  508. 0x80
  509. 0x81
  510. 0x82
  511. 0x83
  512. 0x90
  513. 0x91
  514. 0x92
  515. 0xb0
  516. 0xb1>;
  517. qcom,iommu-bfb-regs = <0x204c
  518. 0x2514
  519. 0x2540
  520. 0x256c
  521. 0x20ac
  522. 0x215c
  523. 0x220c
  524. 0x22bc
  525. 0x2314
  526. 0x2394
  527. 0x2414
  528. 0x2494
  529. 0x2008>;
  530. qcom,iommu-bfb-data = <0x3
  531. 0x4
  532. 0x4
  533. 0x0
  534. 0x0
  535. 0x0
  536. 0x1
  537. 0x0
  538. 0x0
  539. 0x40
  540. 0x44
  541. 0x0
  542. 0x0>;
  543. qcom,iommu-lpae-bfb-regs = <0x204c
  544. 0x2514
  545. 0x2540
  546. 0x256c
  547. 0x20ac
  548. 0x215c
  549. 0x220c
  550. 0x22bc
  551. 0x2314
  552. 0x2394
  553. 0x2414
  554. 0x2494
  555. 0x2008>;
  556. qcom,iommu-lpae-bfb-data = <0x3
  557. 0x0
  558. 0x4
  559. 0x4
  560. 0x0
  561. 0x5
  562. 0x0
  563. 0x1
  564. 0x0
  565. 0x0
  566. 0x40
  567. 0x44
  568. 0x0>;
  569. copss_cb_0: qcom,iommu-ctx@f9bcc000 {
  570. compatible = "qcom,msm-smmu-v1-ctx";
  571. reg = <0xf9bcc000 0x1000>;
  572. interrupts = <0 142 0>;
  573. qcom,iommu-ctx-sids = <0>;
  574. label = "copss_cb_0";
  575. };
  576. copss_cb_1: qcom,iommu-ctx@f9bcd000 {
  577. compatible = "qcom,msm-smmu-v1-ctx";
  578. reg = <0xf9bcd000 0x1000>;
  579. interrupts = <0 142 0>;
  580. qcom,iommu-ctx-sids = <1>;
  581. label = "copss_cb_1";
  582. };
  583. copss_cb_2: qcom,iommu-ctx@f9bce000 {
  584. compatible = "qcom,msm-smmu-v1-ctx";
  585. reg = <0xf9bce000 0x1000>;
  586. interrupts = <0 142 0>;
  587. qcom,iommu-ctx-sids = <2>;
  588. label = "copss_cb_2";
  589. };
  590. copss_cb_3: qcom,iommu-ctx@f9bcf000 {
  591. compatible = "qcom,msm-smmu-v1-ctx";
  592. reg = <0xf9bcf000 0x1000>;
  593. interrupts = <0 142 0>;
  594. qcom,iommu-ctx-sids = <3>;
  595. label = "copss_cb_3";
  596. };
  597. copss_cb_4: qcom,iommu-ctx@f9bd0000 {
  598. compatible = "qcom,msm-smmu-v1-ctx";
  599. reg = <0xf9bd0000 0x1000>;
  600. interrupts = <0 142 0>;
  601. qcom,iommu-ctx-sids = <4>;
  602. label = "copss_cb_4";
  603. };
  604. copss_cb_5: qcom,iommu-ctx@f9bd1000 {
  605. compatible = "qcom,msm-smmu-v1-ctx";
  606. reg = <0xf9bd1000 0x1000>;
  607. interrupts = <0 142 0>;
  608. qcom,iommu-ctx-sids = <5>;
  609. label = "copss_cb_5";
  610. };
  611. copss_cb_6: qcom,iommu-ctx@f9bd2000 {
  612. compatible = "qcom,msm-smmu-v1-ctx";
  613. reg = <0xf9bd2000 0x1000>;
  614. interrupts = <0 142 0>;
  615. qcom,iommu-ctx-sids = <6>;
  616. label = "copss_cb_6";
  617. };
  618. copss_cb_7: qcom,iommu-ctx@f9bd3000 {
  619. compatible = "qcom,msm-smmu-v1-ctx";
  620. reg = <0xf9bd3000 0x1000>;
  621. interrupts = <0 142 0>;
  622. qcom,iommu-ctx-sids = <7>;
  623. label = "copss_cb_7";
  624. };
  625. };
  626. vpu_iommu: qcom,iommu@fdee4000 {
  627. compatible = "qcom,msm-smmu-v1";
  628. #address-cells = <1>;
  629. #size-cells = <1>;
  630. ranges;
  631. reg = <0xfdee4000 0x10000>;
  632. reg-names = "iommu_base";
  633. interrupts = <0 147 0>;
  634. label = "vpu_iommu";
  635. qcom,msm-bus,name = "vpu_ebi";
  636. qcom,msm-bus,num-cases = <2>;
  637. qcom,msm-bus,num-paths = <1>;
  638. qcom,msm-bus,vectors-KBps =
  639. <93 512 0 0>,
  640. <93 512 0 1000>;
  641. status = "disabled";
  642. qcom,iommu-pmu-ngroups = <1>;
  643. qcom,iommu-pmu-ncounters = <8>;
  644. qcom,iommu-pmu-event-classes = <0x00
  645. 0x01
  646. 0x08
  647. 0x09
  648. 0x0a
  649. 0x10
  650. 0x11
  651. 0x12
  652. 0x80
  653. 0x81
  654. 0x82
  655. 0x83
  656. 0x90
  657. 0x91
  658. 0x92
  659. 0xb0
  660. 0xb1>;
  661. qcom,iommu-bfb-regs = <0x204c
  662. 0x2514
  663. 0x2540
  664. 0x256c
  665. 0x2314
  666. 0x2394
  667. 0x2414
  668. 0x2494
  669. 0x20ac
  670. 0x215c
  671. 0x220c
  672. 0x22bc
  673. 0x2008
  674. 0x200c
  675. 0x2010
  676. 0x2014>;
  677. qcom,iommu-bfb-data = <0xffff
  678. 0x4
  679. 0x10
  680. 0x0
  681. 0x0
  682. 0xf
  683. 0x4b
  684. 0x0
  685. 0x1e00
  686. 0x1e00
  687. 0x5a0f
  688. 0x0
  689. 0x0
  690. 0x0
  691. 0x0
  692. 0x0>;
  693. qcom,iommu-lpae-bfb-regs = <0x204c
  694. 0x2514
  695. 0x2540
  696. 0x256c
  697. 0x2314
  698. 0x2394
  699. 0x2414
  700. 0x2494
  701. 0x20ac
  702. 0x215c
  703. 0x220c
  704. 0x22bc
  705. 0x2008
  706. 0x200c
  707. 0x2010
  708. 0x2014>;
  709. qcom,iommu-lpae-bfb-data = <0xffff
  710. 0x0
  711. 0x4
  712. 0x10
  713. 0x0
  714. 0x0
  715. 0xf
  716. 0x4b
  717. 0x1e00
  718. 0x5a2d
  719. 0x1e00
  720. 0x5a0f
  721. 0x0
  722. 0x0
  723. 0x0
  724. 0x0>;
  725. vpu_cb_0: qcom,iommu-ctx@fdeec000 {
  726. compatible = "qcom,msm-smmu-v1-ctx";
  727. reg = <0xfdeec000 0x1000>;
  728. interrupts = <0 145 0>;
  729. qcom,iommu-ctx-sids = <0 1 3>;
  730. label = "vpu_cb_0";
  731. };
  732. vpu_cb_1: qcom,iommu-ctx@fdeed000 {
  733. compatible = "qcom,msm-smmu-v1-ctx";
  734. reg = <0xfdeed000 0x1000>;
  735. interrupts = <0 145 0>;
  736. qcom,iommu-ctx-sids = <8 9>;
  737. label = "vpu_cb_1";
  738. };
  739. vpu_cb_2: qcom,iommu-ctx@fdeee000 {
  740. compatible = "qcom,msm-smmu-v1-ctx";
  741. reg = <0xfdeee000 0x1000>;
  742. interrupts = <0 145 0>;
  743. qcom,iommu-ctx-sids = <5 7 15>;
  744. label = "vpu_cb_2";
  745. };
  746. };
  747. lpass_qdsp_iommu: qcom,iommu@fe054000 {
  748. compatible = "qcom,msm-smmu-v1";
  749. #address-cells = <1>;
  750. #size-cells = <1>;
  751. ranges;
  752. reg = <0xfe054000 0x10000>;
  753. reg-names = "iommu_base";
  754. interrupts = <0 202 0>;
  755. label = "lpass_qdsp_iommu";
  756. qcom,msm-bus,name = "lpass_qdsp_ebi";
  757. qcom,msm-bus,num-cases = <2>;
  758. qcom,msm-bus,num-paths = <1>;
  759. qcom,msm-bus,vectors-KBps =
  760. <11 512 0 0>,
  761. <11 512 0 1000>;
  762. status = "disabled";
  763. qcom,iommu-pmu-ngroups = <1>;
  764. qcom,iommu-pmu-ncounters = <8>;
  765. qcom,iommu-pmu-event-classes = <0x00
  766. 0x01
  767. 0x08
  768. 0x09
  769. 0x0a
  770. 0x10
  771. 0x11
  772. 0x12
  773. 0x80
  774. 0x81
  775. 0x82
  776. 0x83
  777. 0x90
  778. 0x91
  779. 0x92
  780. 0xb0
  781. 0xb1>;
  782. qcom,iommu-bfb-regs = <0x204c
  783. 0x2514
  784. 0x2540
  785. 0x256c
  786. 0x20ac
  787. 0x215c
  788. 0x220c
  789. 0x22bc
  790. 0x2314
  791. 0x2394
  792. 0x2414
  793. 0x2494
  794. 0x2008>;
  795. qcom,iommu-bfb-data = <0x3
  796. 0x4
  797. 0x4
  798. 0x0
  799. 0x0
  800. 0x0
  801. 0x10
  802. 0x0
  803. 0x0
  804. 0x15e
  805. 0x19e
  806. 0x0
  807. 0x0>;
  808. qcom,iommu-lpae-bfb-regs = <0x204c
  809. 0x2514
  810. 0x2540
  811. 0x256c
  812. 0x20ac
  813. 0x215c
  814. 0x220c
  815. 0x22bc
  816. 0x2314
  817. 0x2394
  818. 0x2414
  819. 0x2494
  820. 0x2008>;
  821. qcom,iommu-lpae-bfb-data = <0x3
  822. 0x0
  823. 0x4
  824. 0x4
  825. 0x0
  826. 0x20
  827. 0x0
  828. 0x10
  829. 0x0
  830. 0x0
  831. 0x15e
  832. 0x19e
  833. 0x0>;
  834. lpass_qdsp_cb_0: qcom,iommu-ctx@fe05c000 {
  835. compatible = "qcom,msm-smmu-v1-ctx";
  836. reg = <0xfe05c000 0x1000>;
  837. interrupts = <0 265 0>;
  838. qcom,iommu-ctx-sids = <0>;
  839. label = "lpass_qdsp_cb_0";
  840. };
  841. lpass_qdsp_cb_1: qcom,iommu-ctx@fe05d000 {
  842. compatible = "qcom,msm-smmu-v1-ctx";
  843. reg = <0xfe05d000 0x1000>;
  844. interrupts = <0 265 0>;
  845. qcom,iommu-ctx-sids = <1>;
  846. label = "lpass_qdsp_cb_1";
  847. };
  848. lpass_qdsp_cb_2: qcom,iommu-ctx@fe05e000 {
  849. compatible = "qcom,msm-smmu-v1-ctx";
  850. reg = <0xfe05e000 0x1000>;
  851. interrupts = <0 265 0>;
  852. qcom,iommu-ctx-sids = <2>;
  853. label = "lpass_qdsp_cb_2";
  854. };
  855. lpass_qdsp_cb_3: qcom,iommu-ctx@fe05f000 {
  856. compatible = "qcom,msm-smmu-v1-ctx";
  857. reg = <0xfe05f000 0x1000>;
  858. interrupts = <0 265 0>;
  859. qcom,iommu-ctx-sids = <3>;
  860. label = "lpass_qdsp_cb_3";
  861. };
  862. };
  863. lpass_core_iommu: qcom,iommu@fe064000 {
  864. compatible = "qcom,msm-smmu-v1";
  865. #address-cells = <1>;
  866. #size-cells = <1>;
  867. ranges;
  868. reg = <0xfe064000 0x10000>;
  869. reg-names = "iommu_base";
  870. interrupts = <0 166 0>;
  871. label = "lpass_core_iommu";
  872. qcom,msm-bus,name = "lpass_core_ebi";
  873. qcom,msm-bus,num-cases = <2>;
  874. qcom,msm-bus,num-paths = <1>;
  875. qcom,msm-bus,vectors-KBps =
  876. <52 512 0 0>,
  877. <52 512 0 1000>;
  878. status = "disabled";
  879. qcom,iommu-pmu-ngroups = <1>;
  880. qcom,iommu-pmu-ncounters = <8>;
  881. qcom,iommu-pmu-event-classes = <0x00
  882. 0x01
  883. 0x08
  884. 0x09
  885. 0x0a
  886. 0x10
  887. 0x11
  888. 0x12
  889. 0x80
  890. 0x81
  891. 0x82
  892. 0x83
  893. 0x90
  894. 0x91
  895. 0x92
  896. 0xb0
  897. 0xb1>;
  898. qcom,iommu-bfb-regs = <0x204c
  899. 0x2514
  900. 0x2540
  901. 0x256c
  902. 0x20ac
  903. 0x215c
  904. 0x220c
  905. 0x22bc
  906. 0x2314
  907. 0x2394
  908. 0x2414
  909. 0x2494
  910. 0x2008>;
  911. qcom,iommu-bfb-data = <0x3
  912. 0x4
  913. 0x4
  914. 0x0
  915. 0x0
  916. 0x0
  917. 0x4
  918. 0x0
  919. 0x0
  920. 0x40
  921. 0x50
  922. 0x0
  923. 0x0>;
  924. qcom,iommu-lpae-bfb-regs = <0x204c
  925. 0x2514
  926. 0x2540
  927. 0x256c
  928. 0x20ac
  929. 0x215c
  930. 0x220c
  931. 0x22bc
  932. 0x2314
  933. 0x2394
  934. 0x2414
  935. 0x2494
  936. 0x2008>;
  937. qcom,iommu-lpae-bfb-data = <0x3
  938. 0x0
  939. 0x4
  940. 0x4
  941. 0x0
  942. 0xc
  943. 0x0
  944. 0x4
  945. 0x0
  946. 0x0
  947. 0x40
  948. 0x50
  949. 0x0>;
  950. lpass_core_cb_0: qcom,iommu-ctx@fe06c000 {
  951. compatible = "qcom,msm-smmu-v1-ctx";
  952. reg = <0xfe06c000 0x1000>;
  953. interrupts = <0 267 0>;
  954. qcom,iommu-ctx-sids = <0>;
  955. label = "lpass_core_cb_0";
  956. };
  957. lpass_core_cb_1: qcom,iommu-ctx@fe06d000 {
  958. compatible = "qcom,msm-smmu-v1-ctx";
  959. reg = <0xfe06d000 0x1000>;
  960. interrupts = <0 267 0>;
  961. qcom,iommu-ctx-sids = <1>;
  962. label = "lpass_core_cb_1";
  963. };
  964. lpass_core_cb_2: qcom,iommu-ctx@fe06e000 {
  965. compatible = "qcom,msm-smmu-v1-ctx";
  966. reg = <0xfe06e000 0x1000>;
  967. interrupts = <0 267 0>;
  968. qcom,iommu-ctx-sids = <2>;
  969. label = "lpass_core_cb_2";
  970. };
  971. };
  972. vcap_iommu: qcom,iommu@fdfb6000 {
  973. compatible = "qcom,msm-smmu-v1";
  974. #address-cells = <1>;
  975. #size-cells = <1>;
  976. ranges;
  977. reg = <0xfdfb6000 0x10000>;
  978. reg-names = "iommu_base";
  979. interrupts = <0 315 0>;
  980. qcom,needs-alt-core-clk;
  981. label = "vcap_iommu";
  982. status = "disabled";
  983. qcom,msm-bus,name = "vcap_ebi";
  984. qcom,msm-bus,num-cases = <2>;
  985. qcom,msm-bus,num-paths = <1>;
  986. qcom,msm-bus,vectors-KBps =
  987. <48 512 0 0>,
  988. <48 512 0 1000>;
  989. qcom,iommu-pmu-ngroups = <1>;
  990. qcom,iommu-pmu-ncounters = <8>;
  991. qcom,iommu-pmu-event-classes = <0x00
  992. 0x01
  993. 0x08
  994. 0x09
  995. 0x0A
  996. 0x10
  997. 0x11
  998. 0x12
  999. 0x80
  1000. 0x81
  1001. 0x82
  1002. 0x83
  1003. 0x90
  1004. 0x91
  1005. 0x92
  1006. 0xb0
  1007. 0xb1>;
  1008. qcom,iommu-bfb-regs = <0x204c
  1009. 0x2514
  1010. 0x2540
  1011. 0x256c
  1012. 0x2314
  1013. 0x2394
  1014. 0x2414
  1015. 0x2494
  1016. 0x20ac
  1017. 0x215c
  1018. 0x220c
  1019. 0x22bc
  1020. 0x2008
  1021. 0x200c>;
  1022. qcom,iommu-bfb-data = <0x0ff
  1023. 0x00000004
  1024. 0x00000008
  1025. 0x0
  1026. 0x0
  1027. 0x00000008
  1028. 0x00000028
  1029. 0x0
  1030. 0x001000
  1031. 0x001000
  1032. 0x003008
  1033. 0x0
  1034. 0x0
  1035. 0x0>;
  1036. qcom,iommu-ctx@fdfbe000 {
  1037. compatible = "qcom,msm-smmu-v1-ctx";
  1038. reg = <0xfdfbe000 0x1000>;
  1039. interrupts = <0 313 0>;
  1040. qcom,iommu-ctx-sids = <0>;
  1041. label = "vcap_cb0";
  1042. };
  1043. qcom,iommu-ctx@fdfbf000 {
  1044. compatible = "qcom,msm-smmu-v1-ctx";
  1045. reg = <0xfdfbf000 0x1000>;
  1046. interrupts = <0 313 0>;
  1047. qcom,iommu-ctx-sids = <1>;
  1048. label = "vcap_cb1";
  1049. };
  1050. qcom,iommu-ctx@fdfc0000 {
  1051. compatible = "qcom,msm-smmu-v1-ctx";
  1052. reg = <0xfdfc0000 0x1000>;
  1053. interrupts = <0 313 0>;
  1054. qcom,iommu-ctx-sids = <>;
  1055. label = "vcap_cb2";
  1056. };
  1057. };
  1058. };