mpq8092.dtsi 7.3 KB

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  1. /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. /include/ "skeleton.dtsi"
  13. / {
  14. model = "Qualcomm MPQ8092";
  15. compatible = "qcom,mpq8092";
  16. interrupt-parent = <&intc>;
  17. soc: soc { };
  18. };
  19. /include/ "mpq8092-iommu.dtsi"
  20. /include/ "mpq8092-iommu-domains.dtsi"
  21. /include/ "msm-gdsc.dtsi"
  22. /include/ "mpq8092-ion.dtsi"
  23. &soc {
  24. #address-cells = <1>;
  25. #size-cells = <1>;
  26. ranges;
  27. intc: interrupt-controller@f9000000 {
  28. compatible = "qcom,msm-qgic2";
  29. interrupt-controller;
  30. #interrupt-cells = <3>;
  31. reg = <0xf9000000 0x1000>,
  32. <0xf9002000 0x1000>;
  33. };
  34. msmgpio: gpio@fd510000 {
  35. compatible = "qcom,msm-gpio";
  36. gpio-controller;
  37. #gpio-cells = <2>;
  38. interrupt-controller;
  39. #interrupt-cells = <2>;
  40. reg = <0xfd510000 0x4000>;
  41. ngpio = <146>;
  42. interrupts = <0 208 0>;
  43. qcom,direct-connect-irqs = <8>;
  44. };
  45. timer {
  46. compatible = "arm,armv7-timer";
  47. interrupts = <1 2 0>, <1 3 0>;
  48. clock-frequency = <19200000>;
  49. };
  50. timer@f9020000 {
  51. #address-cells = <1>;
  52. #size-cells = <1>;
  53. ranges;
  54. compatible = "arm,armv7-timer-mem";
  55. reg = <0xf9020000 0x1000>;
  56. clock-frequency = <19200000>;
  57. frame@f9021000 {
  58. frame-number = <0>;
  59. interrupts = <0 8 0x4>,
  60. <0 7 0x4>;
  61. reg = <0xf9021000 0x1000>,
  62. <0xf9022000 0x1000>;
  63. };
  64. frame@f9023000 {
  65. frame-number = <1>;
  66. interrupts = <0 9 0x4>;
  67. reg = <0xf9023000 0x1000>;
  68. status = "disabled";
  69. };
  70. frame@f9024000 {
  71. frame-number = <2>;
  72. interrupts = <0 10 0x4>;
  73. reg = <0xf9024000 0x1000>;
  74. status = "disabled";
  75. };
  76. frame@f9025000 {
  77. frame-number = <3>;
  78. interrupts = <0 11 0x4>;
  79. reg = <0xf9025000 0x1000>;
  80. status = "disabled";
  81. };
  82. frame@f9026000 {
  83. frame-number = <4>;
  84. interrupts = <0 12 0x4>;
  85. reg = <0xf9026000 0x1000>;
  86. status = "disabled";
  87. };
  88. frame@f9027000 {
  89. frame-number = <5>;
  90. interrupts = <0 13 0x4>;
  91. reg = <0xf9027000 0x1000>;
  92. status = "disabled";
  93. };
  94. frame@f9028000 {
  95. frame-number = <6>;
  96. interrupts = <0 14 0x4>;
  97. reg = <0xf9028000 0x1000>;
  98. status = "disabled";
  99. };
  100. };
  101. serial@f991f000 {
  102. compatible = "qcom,msm-lsuart-v14";
  103. reg = <0xf991f000 0x1000>;
  104. interrupts = <0 109 0>;
  105. status = "disabled";
  106. };
  107. serial@f9922000 {
  108. compatible = "qcom,msm-lsuart-v14";
  109. reg = <0xf9922000 0x1000>;
  110. interrupts = <0 112 0>;
  111. status = "disabled";
  112. };
  113. serial@f995e000 {
  114. compatible = "qcom,msm-lsuart-v14";
  115. reg = <0xf995e000 0x1000>;
  116. interrupts = <0 114 0>;
  117. status = "disabled";
  118. };
  119. qcom,msm-imem@fe805000 {
  120. compatible = "qcom,msm-imem";
  121. reg = <0xfe805000 0x1000>; /* Address and size of IMEM */
  122. };
  123. usb@f9a55000 {
  124. compatible = "qcom,hsusb-otg";
  125. reg = <0xf9a55000 0x400>;
  126. interrupts = <0 134 0>, <0 140 0>;
  127. interrupt-names = "core_irq", "async_irq";
  128. HSUSB_VDDCX-supply = <&pma8084_s8>;
  129. HSUSB_1p8-supply = <&pma8084_l22>;
  130. HSUSB_3p3-supply = <&pma8084_l24>;
  131. qcom,vdd-voltage-level = <1050000 1050000>;
  132. qcom,hsusb-otg-phy-type = <2>;
  133. qcom,hsusb-otg-mode = <1>;
  134. qcom,hsusb-otg-otg-control = <1>;
  135. qcom,hsusb-otg-disable-reset;
  136. qcom,msm_bus,name = "usb_otg";
  137. qcom,msm_bus,num_cases = <3>;
  138. qcom,msm_bus,active_only = <0>;
  139. qcom,msm_bus,num_paths = <1>;
  140. qcom,msm-bus,vectors-KBps =
  141. <87 512 0 0>,
  142. <87 512 60000 960000>,
  143. <87 512 6000 6000>;
  144. };
  145. android_usb@fe8050c8 {
  146. compatible = "qcom,android-usb";
  147. reg = <0xfe8050c8 0xc8>;
  148. qcom,android-usb-swfi-latency = <1>;
  149. };
  150. spmi_bus: qcom,spmi@fc4c0000 {
  151. cell-index = <0>;
  152. compatible = "qcom,spmi-pmic-arb";
  153. reg-names = "core", "intr", "cnfg";
  154. reg = <0xfc4cf000 0x1000>,
  155. <0Xfc4cb000 0x1000>,
  156. <0Xfc4ca000 0x1000>;
  157. /* 190,ee0_krait_hlos_spmi_periph_irq */
  158. /* 187,channel_0_krait_hlos_trans_done_irq */
  159. interrupts = <0 190 0 0 187 0>;
  160. qcom,not-wakeup;
  161. qcom,pmic-arb-ee = <0>;
  162. qcom,pmic-arb-channel = <0>;
  163. };
  164. sdcc1: qcom,sdcc@f9824000 {
  165. cell-index = <1>; /* SDC1 eMMC slot */
  166. compatible = "qcom,msm-sdcc";
  167. reg = <0xf9824000 0x800>;
  168. reg-names = "core_mem";
  169. interrupts = <0 123 0>;
  170. interrupt-names = "core_irq";
  171. qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
  172. qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
  173. qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */
  174. qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
  175. qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
  176. qcom,sup-voltages = <2950 2950>;
  177. qcom,bus-width = <8>;
  178. qcom,nonremovable;
  179. qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
  180. };
  181. sdcc2: qcom,sdcc@f98a4000 {
  182. cell-index = <2>; /* SDC2 SD card slot */
  183. compatible = "qcom,msm-sdcc";
  184. reg = <0xf98a4000 0x800>;
  185. reg-names = "core_mem";
  186. interrupts = <0 125 0>;
  187. interrupt-names = "core_irq";
  188. qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
  189. qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
  190. qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */
  191. qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
  192. qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
  193. qcom,sup-voltages = <2950 2950>;
  194. qcom,bus-width = <4>;
  195. qcom,xpc;
  196. qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
  197. qcom,current-limit = <800>;
  198. };
  199. qcom,sps@f9980000 {
  200. compatible = "qcom,msm_sps";
  201. reg = <0xf9984000 0x15000>,
  202. <0xf9999000 0xb000>;
  203. reg-names = "bam_mem", "core_mem";
  204. interrupts = <0 94 0>;
  205. qcom,pipe-attr-ee;
  206. };
  207. sata: sata@fc580000 {
  208. compatible = "qcom,msm-ahci";
  209. reg = <0xfc580000 0x17c>;
  210. interrupts = <0 243 0>;
  211. };
  212. qcom,wdt@f9017000 {
  213. compatible = "qcom,msm-watchdog";
  214. reg = <0xf9017000 0x1000>;
  215. interrupts = <0 3 0>, <0 4 0>;
  216. qcom,bark-time = <11000>;
  217. qcom,pet-time = <10000>;
  218. qcom,ipi-ping;
  219. };
  220. qcom,ocmem@fdd00000 {
  221. compatible = "qcom,msm-ocmem";
  222. reg = <0xfdd00000 0x2000>,
  223. <0xfdd02000 0x2000>,
  224. <0xfe070000 0x400>,
  225. <0xfec00000 0x180000>;
  226. reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
  227. interrupts = <0 76 0>, <0 77 0>;
  228. interrupt-names = "ocmem_irq", "dm_irq";
  229. qcom,ocmem-num-regions = <0x3>;
  230. qcom,ocmem-num-macros = <0x18>;
  231. qcom,resource-type = <0x706d636f>;
  232. #address-cells = <1>;
  233. #size-cells = <1>;
  234. ranges = <0x0 0xfec00000 0x180000>;
  235. partition@0 {
  236. reg = <0x0 0x100000>;
  237. qcom,ocmem-part-name = "graphics";
  238. qcom,ocmem-part-min = <0x80000>;
  239. };
  240. partition@80000 {
  241. reg = <0x100000 0x80000>;
  242. qcom,ocmem-part-name = "lp_audio";
  243. qcom,ocmem-part-min = <0x80000>;
  244. };
  245. partition@100000 {
  246. reg = <0x100000 0x80000>;
  247. qcom,ocmem-part-name = "video";
  248. qcom,ocmem-part-min = <0x55000>;
  249. };
  250. };
  251. };
  252. &gdsc_venus {
  253. status = "ok";
  254. };
  255. &gdsc_mdss {
  256. status = "ok";
  257. };
  258. &gdsc_jpeg {
  259. status = "ok";
  260. };
  261. &gdsc_vpu {
  262. status = "ok";
  263. };
  264. &gdsc_oxili_gx {
  265. status = "ok";
  266. };
  267. &gdsc_oxili_cx {
  268. status = "ok";
  269. };
  270. &gdsc_usb_hsic {
  271. status = "ok";
  272. };
  273. &gdsc_vcap {
  274. status = "ok";
  275. };
  276. /include/ "msm-pma8084.dtsi"
  277. /include/ "mpq8092-regulator.dtsi"