imx53.dtsi 6.7 KB

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  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. /include/ "skeleton.dtsi"
  13. / {
  14. aliases {
  15. serial0 = &uart1;
  16. serial1 = &uart2;
  17. serial2 = &uart3;
  18. serial3 = &uart4;
  19. serial4 = &uart5;
  20. };
  21. tzic: tz-interrupt-controller@0fffc000 {
  22. compatible = "fsl,imx53-tzic", "fsl,tzic";
  23. interrupt-controller;
  24. #interrupt-cells = <1>;
  25. reg = <0x0fffc000 0x4000>;
  26. };
  27. clocks {
  28. #address-cells = <1>;
  29. #size-cells = <0>;
  30. ckil {
  31. compatible = "fsl,imx-ckil", "fixed-clock";
  32. clock-frequency = <32768>;
  33. };
  34. ckih1 {
  35. compatible = "fsl,imx-ckih1", "fixed-clock";
  36. clock-frequency = <22579200>;
  37. };
  38. ckih2 {
  39. compatible = "fsl,imx-ckih2", "fixed-clock";
  40. clock-frequency = <0>;
  41. };
  42. osc {
  43. compatible = "fsl,imx-osc", "fixed-clock";
  44. clock-frequency = <24000000>;
  45. };
  46. };
  47. soc {
  48. #address-cells = <1>;
  49. #size-cells = <1>;
  50. compatible = "simple-bus";
  51. interrupt-parent = <&tzic>;
  52. ranges;
  53. aips@50000000 { /* AIPS1 */
  54. compatible = "fsl,aips-bus", "simple-bus";
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. reg = <0x50000000 0x10000000>;
  58. ranges;
  59. spba@50000000 {
  60. compatible = "fsl,spba-bus", "simple-bus";
  61. #address-cells = <1>;
  62. #size-cells = <1>;
  63. reg = <0x50000000 0x40000>;
  64. ranges;
  65. esdhc@50004000 { /* ESDHC1 */
  66. compatible = "fsl,imx53-esdhc";
  67. reg = <0x50004000 0x4000>;
  68. interrupts = <1>;
  69. status = "disabled";
  70. };
  71. esdhc@50008000 { /* ESDHC2 */
  72. compatible = "fsl,imx53-esdhc";
  73. reg = <0x50008000 0x4000>;
  74. interrupts = <2>;
  75. status = "disabled";
  76. };
  77. uart3: uart@5000c000 {
  78. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  79. reg = <0x5000c000 0x4000>;
  80. interrupts = <33>;
  81. status = "disabled";
  82. };
  83. ecspi@50010000 { /* ECSPI1 */
  84. #address-cells = <1>;
  85. #size-cells = <0>;
  86. compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
  87. reg = <0x50010000 0x4000>;
  88. interrupts = <36>;
  89. status = "disabled";
  90. };
  91. esdhc@50020000 { /* ESDHC3 */
  92. compatible = "fsl,imx53-esdhc";
  93. reg = <0x50020000 0x4000>;
  94. interrupts = <3>;
  95. status = "disabled";
  96. };
  97. esdhc@50024000 { /* ESDHC4 */
  98. compatible = "fsl,imx53-esdhc";
  99. reg = <0x50024000 0x4000>;
  100. interrupts = <4>;
  101. status = "disabled";
  102. };
  103. };
  104. gpio1: gpio@53f84000 {
  105. compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
  106. reg = <0x53f84000 0x4000>;
  107. interrupts = <50 51>;
  108. gpio-controller;
  109. #gpio-cells = <2>;
  110. interrupt-controller;
  111. #interrupt-cells = <1>;
  112. };
  113. gpio2: gpio@53f88000 {
  114. compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
  115. reg = <0x53f88000 0x4000>;
  116. interrupts = <52 53>;
  117. gpio-controller;
  118. #gpio-cells = <2>;
  119. interrupt-controller;
  120. #interrupt-cells = <1>;
  121. };
  122. gpio3: gpio@53f8c000 {
  123. compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
  124. reg = <0x53f8c000 0x4000>;
  125. interrupts = <54 55>;
  126. gpio-controller;
  127. #gpio-cells = <2>;
  128. interrupt-controller;
  129. #interrupt-cells = <1>;
  130. };
  131. gpio4: gpio@53f90000 {
  132. compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
  133. reg = <0x53f90000 0x4000>;
  134. interrupts = <56 57>;
  135. gpio-controller;
  136. #gpio-cells = <2>;
  137. interrupt-controller;
  138. #interrupt-cells = <1>;
  139. };
  140. wdog@53f98000 { /* WDOG1 */
  141. compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
  142. reg = <0x53f98000 0x4000>;
  143. interrupts = <58>;
  144. status = "disabled";
  145. };
  146. wdog@53f9c000 { /* WDOG2 */
  147. compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
  148. reg = <0x53f9c000 0x4000>;
  149. interrupts = <59>;
  150. status = "disabled";
  151. };
  152. uart1: uart@53fbc000 {
  153. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  154. reg = <0x53fbc000 0x4000>;
  155. interrupts = <31>;
  156. status = "disabled";
  157. };
  158. uart2: uart@53fc0000 {
  159. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  160. reg = <0x53fc0000 0x4000>;
  161. interrupts = <32>;
  162. status = "disabled";
  163. };
  164. gpio5: gpio@53fdc000 {
  165. compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
  166. reg = <0x53fdc000 0x4000>;
  167. interrupts = <103 104>;
  168. gpio-controller;
  169. #gpio-cells = <2>;
  170. interrupt-controller;
  171. #interrupt-cells = <1>;
  172. };
  173. gpio6: gpio@53fe0000 {
  174. compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
  175. reg = <0x53fe0000 0x4000>;
  176. interrupts = <105 106>;
  177. gpio-controller;
  178. #gpio-cells = <2>;
  179. interrupt-controller;
  180. #interrupt-cells = <1>;
  181. };
  182. gpio7: gpio@53fe4000 {
  183. compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
  184. reg = <0x53fe4000 0x4000>;
  185. interrupts = <107 108>;
  186. gpio-controller;
  187. #gpio-cells = <2>;
  188. interrupt-controller;
  189. #interrupt-cells = <1>;
  190. };
  191. i2c@53fec000 { /* I2C3 */
  192. #address-cells = <1>;
  193. #size-cells = <0>;
  194. compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
  195. reg = <0x53fec000 0x4000>;
  196. interrupts = <64>;
  197. status = "disabled";
  198. };
  199. uart4: uart@53ff0000 {
  200. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  201. reg = <0x53ff0000 0x4000>;
  202. interrupts = <13>;
  203. status = "disabled";
  204. };
  205. };
  206. aips@60000000 { /* AIPS2 */
  207. compatible = "fsl,aips-bus", "simple-bus";
  208. #address-cells = <1>;
  209. #size-cells = <1>;
  210. reg = <0x60000000 0x10000000>;
  211. ranges;
  212. uart5: uart@63f90000 {
  213. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  214. reg = <0x63f90000 0x4000>;
  215. interrupts = <86>;
  216. status = "disabled";
  217. };
  218. ecspi@63fac000 { /* ECSPI2 */
  219. #address-cells = <1>;
  220. #size-cells = <0>;
  221. compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
  222. reg = <0x63fac000 0x4000>;
  223. interrupts = <37>;
  224. status = "disabled";
  225. };
  226. sdma@63fb0000 {
  227. compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
  228. reg = <0x63fb0000 0x4000>;
  229. interrupts = <6>;
  230. };
  231. cspi@63fc0000 {
  232. #address-cells = <1>;
  233. #size-cells = <0>;
  234. compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
  235. reg = <0x63fc0000 0x4000>;
  236. interrupts = <38>;
  237. status = "disabled";
  238. };
  239. i2c@63fc4000 { /* I2C2 */
  240. #address-cells = <1>;
  241. #size-cells = <0>;
  242. compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
  243. reg = <0x63fc4000 0x4000>;
  244. interrupts = <63>;
  245. status = "disabled";
  246. };
  247. i2c@63fc8000 { /* I2C1 */
  248. #address-cells = <1>;
  249. #size-cells = <0>;
  250. compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
  251. reg = <0x63fc8000 0x4000>;
  252. interrupts = <62>;
  253. status = "disabled";
  254. };
  255. fec@63fec000 {
  256. compatible = "fsl,imx53-fec", "fsl,imx25-fec";
  257. reg = <0x63fec000 0x4000>;
  258. interrupts = <87>;
  259. status = "disabled";
  260. };
  261. };
  262. };
  263. };