apq8084.dtsi 10 KB

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  1. /* Copyright (c) 2013, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. /include/ "skeleton64.dtsi"
  13. / {
  14. model = "Qualcomm APQ 8084";
  15. compatible = "qcom,apq8084";
  16. interrupt-parent = <&intc>;
  17. soc: soc { };
  18. };
  19. /include/ "msm-gdsc.dtsi"
  20. /include/ "apq8084-ion.dtsi"
  21. /include/ "apq8084-iommu.dtsi"
  22. /include/ "apq8084-smp2p.dtsi"
  23. /include/ "apq8084-coresight.dtsi"
  24. /include/ "apq8084-mdss.dtsi"
  25. /include/ "apq8084-gpu.dtsi"
  26. &soc {
  27. #address-cells = <1>;
  28. #size-cells = <1>;
  29. ranges = <0 0 0 0xffffffff>;
  30. intc: interrupt-controller@f9000000 {
  31. compatible = "qcom,msm-qgic2";
  32. interrupt-controller;
  33. #interrupt-cells = <3>;
  34. reg = <0xF9000000 0x1000>,
  35. <0xF9002000 0x1000>;
  36. };
  37. msmgpio: gpio@fd510000 {
  38. compatible = "qcom,msm-gpio";
  39. gpio-controller;
  40. #gpio-cells = <2>;
  41. interrupt-controller;
  42. #interrupt-cells = <2>;
  43. reg = <0xfd510000 0x4000>;
  44. ngpio = <146>;
  45. interrupts = <0 208 0>;
  46. qcom,direct-connect-irqs = <8>;
  47. };
  48. timer {
  49. compatible = "arm,armv7-timer";
  50. interrupts = <1 2 0 1 3 0>;
  51. clock-frequency = <19200000>;
  52. };
  53. serial@f991f000 {
  54. compatible = "qcom,msm-lsuart-v14";
  55. reg = <0xf991f000 0x1000>;
  56. interrupts = <0 109 0>;
  57. status = "disabled";
  58. };
  59. qcom,cache_erp {
  60. compatible = "qcom,cache_erp";
  61. interrupts = <1 9 0>, <0 2 0>;
  62. interrupt-names = "l1_irq", "l2_irq";
  63. };
  64. qcom,cache_dump {
  65. compatible = "qcom,cache_dump";
  66. qcom,l1-dump-size = <0x100000>;
  67. qcom,l2-dump-size = <0x500000>;
  68. };
  69. rpm_bus: qcom,rpm-smd {
  70. compatible = "qcom,rpm-smd";
  71. rpm-channel-name = "rpm_requests";
  72. rpm-channel-type = <15>; /* SMD_APPS_RPM */
  73. rpm-standalone;
  74. };
  75. qcom,msm-imem@fe805000 {
  76. compatible = "qcom,msm-imem";
  77. reg = <0xfe805000 0x1000>; /* Address and size of IMEM */
  78. };
  79. qcom,msm-rtb {
  80. compatible = "qcom,msm-rtb";
  81. qcom,memory-reservation-type = "EBI1";
  82. qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */
  83. };
  84. sdcc1: qcom,sdcc@f9824000 {
  85. cell-index = <1>; /* SDC1 eMMC slot */
  86. compatible = "qcom,msm-sdcc";
  87. reg = <0xf9824000 0x800>;
  88. reg-names = "core_mem";
  89. interrupts = <0 123 0>;
  90. interrupt-names = "core_irq";
  91. qcom,bus-width = <8>;
  92. status = "disabled";
  93. };
  94. sdcc2: qcom,sdcc@f98a4000 {
  95. cell-index = <2>; /* SDC2 SD card slot */
  96. compatible = "qcom,msm-sdcc";
  97. reg = <0xf98a4000 0x800>;
  98. reg-names = "core_mem";
  99. interrupts = <0 125 0>;
  100. interrupt-names = "core_irq";
  101. qcom,bus-width = <4>;
  102. status = "disabled";
  103. };
  104. qcom,sps@f9980000 {
  105. compatible = "qcom,msm_sps";
  106. reg = <0xf9984000 0x15000>,
  107. <0xf9999000 0xb000>;
  108. interrupts = <0 94 0>;
  109. qcom,pipe-attr-ee;
  110. };
  111. spmi_bus: qcom,spmi@fc4c0000 {
  112. cell-index = <0>;
  113. compatible = "qcom,spmi-pmic-arb";
  114. reg-names = "core", "intr", "cnfg";
  115. reg = <0xfc4cf000 0x1000>,
  116. <0Xfc4cb000 0x1000>,
  117. <0Xfc4ca000 0x1000>;
  118. /* 190,ee0_krait_hlos_spmi_periph_irq */
  119. /* 187,channel_0_krait_hlos_trans_done_irq */
  120. interrupts = <0 190 0>, <0 187 0>;
  121. qcom,not-wakeup;
  122. qcom,pmic-arb-ee = <0>;
  123. qcom,pmic-arb-channel = <0>;
  124. #address-cells = <1>;
  125. #size-cells = <0>;
  126. interrupt-controller;
  127. #interrupt-cells = <3>;
  128. };
  129. i2c_0: i2c@f9925000 { /* BLSP1 QUP3 */
  130. cell-index = <0>;
  131. compatible = "qcom,i2c-qup";
  132. #address-cells = <1>;
  133. #size-cells = <0>;
  134. reg-names = "qup_phys_addr";
  135. reg = <0xf9925000 0x1000>;
  136. interrupt-names = "qup_err_intr";
  137. interrupts = <0 97 0>;
  138. qcom,i2c-bus-freq = <100000>;
  139. qcom,i2c-src-freq = <50000000>;
  140. qcom,sda-gpio = <&msmgpio 10 0>;
  141. qcom,scl-gpio = <&msmgpio 11 0>;
  142. };
  143. qcom,usbbam@f9304000 {
  144. compatible = "qcom,usb-bam-msm";
  145. reg = <0xf9304000 0x5000>,
  146. <0xf92f880c 0x4>;
  147. reg-names = "ssusb", "qscratch_ram1_reg";
  148. interrupts = <0 132 0>;
  149. interrupt-names = "ssusb";
  150. qcom,usb-bam-num-pipes = <16>;
  151. qcom,usb-bam-fifo-baseaddr = <0x00000000 0xf9200000>;
  152. qcom,ignore-core-reset-ack;
  153. qcom,disable-clk-gating;
  154. qcom,pipe0 {
  155. label = "ssusb-qdss-in-0";
  156. qcom,usb-bam-mem-type = <1>;
  157. qcom,bam-type = <0>;
  158. qcom,dir = <1>;
  159. qcom,pipe-num = <0>;
  160. qcom,peer-bam = <1>;
  161. qcom,src-bam-physical-address = <0xfc37C000>;
  162. qcom,src-bam-pipe-index = <0>;
  163. qcom,dst-bam-physical-address = <0xf9304000>;
  164. qcom,dst-bam-pipe-index = <2>;
  165. qcom,data-fifo-offset = <0xf0000>;
  166. qcom,data-fifo-size = <0x1800>;
  167. qcom,descriptor-fifo-offset = <0xf4000>;
  168. qcom,descriptor-fifo-size = <0x1400>;
  169. qcom,reset-bam-on-connect;
  170. };
  171. };
  172. usb3: qcom,ssusb@f9200000 {
  173. compatible = "qcom,dwc-usb3-msm";
  174. reg = <0xf9200000 0xfc000>,
  175. <0xfd4ab000 0x4>;
  176. #address-cells = <1>;
  177. #size-cells = <1>;
  178. ranges;
  179. interrupts = <0 133 0>;
  180. interrupt-names = "hs_phy_irq";
  181. ssusb_vdd_dig-supply = <&pma8084_s1>;
  182. SSUSB_1p8-supply = <&pma8084_l6>;
  183. hsusb_vdd_dig-supply = <&pma8084_s1>;
  184. HSUSB_1p8-supply = <&pma8084_l6>;
  185. HSUSB_3p3-supply = <&pma8084_l24>;
  186. qcom,dwc-usb3-msm-dbm-eps = <4>;
  187. qcom,vdd-voltage-level = <0 900000 1050000>;
  188. dwc3@f9200000 {
  189. compatible = "synopsys,dwc3";
  190. reg = <0xf9200000 0xfc000>;
  191. interrupt-parent = <&intc>;
  192. interrupts = <0 131 0>, <0 179 0>;
  193. interrupt-names = "irq", "otg_irq";
  194. tx-fifo-resize;
  195. };
  196. };
  197. android_usb {
  198. compatible = "qcom,android-usb";
  199. };
  200. tsens: tsens@fc4a8000 {
  201. compatible = "qcom,msm-tsens";
  202. reg = <0xfc4a8000 0x2000>,
  203. <0xfc4bc000 0x1000>;
  204. reg-names = "tsens_physical", "tsens_eeprom_physical";
  205. interrupts = <0 184 0>;
  206. qcom,sensors = <11>;
  207. qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 3200
  208. 3200 3200>;
  209. qcom,calib-mode = "fuse_map1";
  210. };
  211. qcom,ocmem@fdd00000 {
  212. compatible = "qcom,msm-ocmem";
  213. reg = <0xfdd00000 0x2000>,
  214. <0xfdd02000 0x2000>,
  215. <0xfe039000 0x400>,
  216. <0xfec00000 0x200000>;
  217. reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
  218. interrupts = <0 76 0 0 77 0>;
  219. interrupt-names = "ocmem_irq", "dm_irq";
  220. qcom,ocmem-num-regions = <0x4>;
  221. qcom,ocmem-num-macros = <0x20>;
  222. qcom,resource-type = <0x706d636f>;
  223. #address-cells = <1>;
  224. #size-cells = <1>;
  225. ranges = <0x0 0xfec00000 0x200000>;
  226. partition@0 {
  227. reg = <0x0 0x180000>;
  228. qcom,ocmem-part-name = "graphics";
  229. qcom,ocmem-part-min = <0x80000>;
  230. };
  231. partition@80000 {
  232. reg = <0x180000 0x80000>;
  233. qcom,ocmem-part-name = "lp_audio";
  234. qcom,ocmem-part-min = <0x80000>;
  235. };
  236. partition@100000 {
  237. reg = <0x180000 0x80000>;
  238. qcom,ocmem-part-name = "video";
  239. qcom,ocmem-part-min = <0x55000>;
  240. };
  241. };
  242. memory_hole: qcom,msm-mem-hole {
  243. compatible = "qcom,msm-mem-hole";
  244. qcom,memblock-remove = <0x0d200000 0x02c00000>; /* Address and Size of Hole */
  245. };
  246. qcom,ipc-spinlock@fd484000 {
  247. compatible = "qcom,ipc-spinlock-sfpb";
  248. reg = <0xfd484000 0x400>;
  249. qcom,num-locks = <8>;
  250. };
  251. qcom,smem@fa00000 {
  252. compatible = "qcom,smem";
  253. reg = <0xfa00000 0x200000>,
  254. <0xf9011000 0x1000>,
  255. <0xfc428000 0x4000>;
  256. reg-names = "smem", "irq-reg-base", "aux-mem1";
  257. qcom,smd-adsp {
  258. compatible = "qcom,smd";
  259. qcom,smd-edge = <1>;
  260. qcom,smd-irq-offset = <0x8>;
  261. qcom,smd-irq-bitmask = <0x100>;
  262. qcom,pil-string = "adsp";
  263. interrupts = <0 156 1>;
  264. };
  265. qcom,smsm-adsp {
  266. compatible = "qcom,smsm";
  267. qcom,smsm-edge = <1>;
  268. qcom,smsm-irq-offset = <0x8>;
  269. qcom,smsm-irq-bitmask = <0x200>;
  270. interrupts = <0 157 1>;
  271. };
  272. qcom,smd-rpm {
  273. compatible = "qcom,smd";
  274. qcom,smd-edge = <15>;
  275. qcom,smd-irq-offset = <0x8>;
  276. qcom,smd-irq-bitmask = <0x1>;
  277. interrupts = <0 168 1>;
  278. qcom,irq-no-suspend;
  279. };
  280. };
  281. qcom,venus@fdce0000 {
  282. compatible = "qcom,pil-venus";
  283. reg = <0xfdce0000 0x4000>,
  284. <0xfdc80000 0x400>;
  285. reg-names = "wrapper_base", "vbif_base";
  286. vdd-supply = <&gdsc_venus>;
  287. qcom,firmware-name = "venus";
  288. };
  289. ufs1: ufshc@0xfc598000 {
  290. compatible = "jedec,ufs-1.1";
  291. reg = <0xfc598000 0x800>;
  292. interrupts = <0 28 0>;
  293. status = "disabled";
  294. };
  295. qcom,wdt@f9017000 {
  296. compatible = "qcom,msm-watchdog";
  297. reg = <0xf9017000 0x1000>;
  298. interrupts = <0 3 0>, <0 4 0>;
  299. qcom,bark-time = <11000>;
  300. qcom,pet-time = <10000>;
  301. qcom,ipi-ping;
  302. };
  303. qcom,msm-rng@f9bff000{
  304. compatible = "qcom,msm-rng";
  305. reg = <0xf9bff000 0x200>;
  306. qcom,msm-rng-iface-clk;
  307. };
  308. };
  309. &gdsc_venus {
  310. status = "ok";
  311. };
  312. &gdsc_venus_core0 {
  313. status = "ok";
  314. };
  315. &gdsc_venus_core1 {
  316. status = "ok";
  317. };
  318. &gdsc_vpu {
  319. status = "ok";
  320. };
  321. &gdsc_mdss {
  322. status = "ok";
  323. };
  324. &gdsc_jpeg {
  325. status = "ok";
  326. };
  327. &gdsc_vfe {
  328. status = "ok";
  329. };
  330. &gdsc_oxili_gx {
  331. status = "ok";
  332. };
  333. &gdsc_oxili_cx {
  334. status = "ok";
  335. };
  336. &gdsc_usb_hsic {
  337. status = "ok";
  338. };
  339. &gdsc_pcie_0{
  340. status = "ok";
  341. };
  342. &gdsc_pcie_1{
  343. status = "ok";
  344. };
  345. &gdsc_usb30{
  346. status = "ok";
  347. };
  348. &gdsc_usb30_sec{
  349. status = "ok";
  350. };
  351. /include/ "msm-pma8084.dtsi"
  352. /include/ "apq8084-regulator.dtsi"
  353. &pma8084_vadc {
  354. chan@b0 {
  355. label = "apq_therm";
  356. reg = <0xb0>;
  357. qcom,decimation = <0>;
  358. qcom,pre-div-channel-scaling = <0>;
  359. qcom,calibration-type = "ratiometric";
  360. qcom,scale-function = <2>;
  361. qcom,hw-settle-time = <2>;
  362. qcom,fast-avg-setup = <0>;
  363. };
  364. chan@b3 {
  365. label = "quiet_therm";
  366. reg = <0xb3>;
  367. qcom,decimation = <0>;
  368. qcom,pre-div-channel-scaling = <0>;
  369. qcom,calibration-type = "ratiometric";
  370. qcom,scale-function = <2>;
  371. qcom,hw-settle-time = <2>;
  372. qcom,fast-avg-setup = <0>;
  373. };
  374. };
  375. &pma8084_adc_tm {
  376. chan@8 {
  377. label = "die_temp";
  378. reg = <8>;
  379. qcom,decimation = <0>;
  380. qcom,pre-div-channel-scaling = <0>;
  381. qcom,calibration-type = "absolute";
  382. qcom,scale-function = <3>;
  383. qcom,hw-settle-time = <0>;
  384. qcom,fast-avg-setup = <3>;
  385. qcom,btm-channel-number = <0x48>;
  386. };
  387. chan@b0 {
  388. label = "apq_therm";
  389. reg = <0xb0>;
  390. qcom,decimation = <0>;
  391. qcom,pre-div-channel-scaling = <0>;
  392. qcom,calibration-type = "ratiometric";
  393. qcom,scale-function = <2>;
  394. qcom,hw-settle-time = <2>;
  395. qcom,fast-avg-setup = <3>;
  396. qcom,btm-channel-number = <0x68>;
  397. qcom,thermal-node;
  398. };
  399. chan@b3 {
  400. label = "quiet_therm";
  401. reg = <0xb3>;
  402. qcom,decimation = <0>;
  403. qcom,pre-div-channel-scaling = <0>;
  404. qcom,calibration-type = "ratiometric";
  405. qcom,scale-function = <2>;
  406. qcom,hw-settle-time = <2>;
  407. qcom,fast-avg-setup = <3>;
  408. qcom,btm-channel-number = <0x70>;
  409. qcom,thermal-node;
  410. };
  411. };