msm-ssusb.txt 4.5 KB

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  1. MSM SuperSpeed USB3.0 SoC controller
  2. Required properties :
  3. - compatible : should be "qcom,dwc-usb3-msm"
  4. - reg : offset and length of the register set in the memory map
  5. offset and length of the TCSR register for routing USB
  6. signals to either picoPHY0 or picoPHY1.
  7. - interrupts: IRQ lines used by this controller
  8. - <supply-name>-supply: phandle to the regulator device tree node
  9. Required "supply-name" examples are:
  10. "SSUSB_lp8" : 1.8v supply for SSPHY
  11. "HSUSB_1p8" : 1.8v supply for HSPHY
  12. "HSUSB_3p3" : 3.3v supply for HSPHY
  13. "vbus_dwc3" : vbus supply for host mode
  14. "ssusb_vdd_dig" : vdd supply for SSPHY digital circuit operation
  15. "hsusb_vdd_dig" : vdd supply for HSPHY digital circuit operation
  16. - qcom,dwc-usb3-msm-dbm-eps: Number of endpoints avaliable for
  17. the DBM (Device Bus Manager). The DBM is HW unit which is part of
  18. the MSM USB3.0 core (which also includes the Synopsys DesignWare
  19. USB3.0 controller)
  20. - qcom,vdd-voltage-level: This property must be a list of three integer
  21. values (no, min, max) where each value represents either a voltage in
  22. microvolts or a value corresponding to voltage corner
  23. Optional properties :
  24. - Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
  25. below optional properties:
  26. - qcom,msm_bus,name
  27. - qcom,msm_bus,num_cases
  28. - qcom,msm_bus,active_only
  29. - qcom,msm_bus,num_paths
  30. - qcom,msm_bus,vectors
  31. - interrupt-names : Optional interrupt resource entries are:
  32. "hs_phy_irq" : Interrupt from HSPHY for asynchronous events in LPM.
  33. This is not used if wakeup events are received externally (e.g. PMIC)
  34. "pmic_id_irq" : Interrupt from PMIC for external ID pin notification.
  35. - qcom,otg-capability: If present then depend on PMIC for VBUS notifications,
  36. otherwise depend on PHY.
  37. - qcom,charging-disabled: If present then battery charging using USB
  38. is disabled.
  39. - qcom,dwc-hsphy-init: This property if present represents phy init
  40. value to be used for overriding HSPHY parameters into QSCRATCH register.
  41. This 32 bit value represents parameters as follows:
  42. bits 0-5 PARAMETER_OVERRIDE_A
  43. bits 6-12 PARAMETER_OVERRIDE_B
  44. bits 13-19 PARAMETER_OVERRIDE_C
  45. bits 20-25 PARAMETER_OVERRIDE_D
  46. - qcom,skip-charger-detection: If present then charger detection using BC1.2
  47. is not supported and attached host should always be assumed as SDP.
  48. - USB3_GDSC-supply : phandle to the globally distributed switch controller
  49. regulator node to the USB controller.
  50. - qcom,dwc_usb3-adc_tm: Corresponding ADC_TM device's phandle to set recurring
  51. measurements on USB_ID channel when using ADC and receive
  52. notifications for set thresholds.
  53. - qcom,dwc-usb3-msm-tx-fifo-size: If present, represents RAM size available for
  54. TX fifo allocation in bytes
  55. - qcom,dwc-usb3-msm-qdss-tx-fifo-size: If present, represent RAM size available
  56. for TX fifo allocation in QDSS composition
  57. - qcom,dwc-ssphy-deemphasis-value: This property if present represents ss phy
  58. deemphasis value to be used for overriding into SSPHY register.
  59. - qcom,usbin-vadc: Corresponding vadc device's phandle to read usbin voltage using VADC.
  60. This will be used to get value of usb power supply's VOLTAGE_NOW property,
  61. - qcom,utmi-clk-rate: Indicates refclk frequency (in Hz) to the core. If not
  62. specified, default of 19.2MHz is assumed.
  63. Sub nodes:
  64. - Sub node for "DWC3- USB3 controller".
  65. This sub node is required property for device node. The properties of this subnode
  66. are specified in dwc3.txt.
  67. Example MSM USB3.0 controller device node :
  68. usb@f9200000 {
  69. compatible = "qcom,dwc-usb3-msm";
  70. reg = <0xf9200000 0xfc000>,
  71. <0xfd4ab000 0x4>;
  72. interrupts = <0 133 0>;
  73. interrupt-names = "hs_phy_irq";
  74. ssusb_vdd_dig-supply = <&pm8841_s2_corner>;
  75. SSUSB_1p8-supply = <&pm8941_l6>;
  76. hsusb_vdd_dig-supply = <&pm8841_s2_corner>;
  77. HSUSB_1p8-supply = <&pm8941_l6>;
  78. HSUSB_3p3-supply = <&pm8941_l24>;
  79. vbus_dwc3-supply = <&pm8941_mvs1>;
  80. USB3_GDSC-supply = <&gdsc_usb30>;
  81. qcom,dwc-usb3-msm-dbm-eps = <4>
  82. qcom,vdd-voltage-level = <1 5 7>;
  83. qcom,dwc-hsphy-init = <0x00D195A4>;
  84. qcom,dwc_usb3-adc_tm = <&pm8941_adc_tm>;
  85. qcom,dwc-usb3-msm-tx-fifo-size = <29696>;
  86. qcom,dwc-usb3-msm-qdss-tx-fifo-size = <16384>;
  87. qcom,dwc-ssphy-deemphasis-value = <26>;
  88. qcom,usbin-vadc = <&pm8941_vadc>;
  89. qcom,msm_bus,name = "usb3";
  90. qcom,msm_bus,num_cases = <2>;
  91. qcom,msm_bus,active_only = <0>;
  92. qcom,msm_bus,num_paths = <1>;
  93. qcom,msm_bus,vectors =
  94. <61 512 0 0>,
  95. <61 512 240000000 960000000>;
  96. dwc3@f9200000 {
  97. compatible = "synopsys,dwc3";
  98. reg = <0xf9200000 0xfc000>;
  99. interrupts = <0 131 0>, <0 179 0>;
  100. interrupt-names = "irq", "otg_irq";
  101. tx-fifo-resize;
  102. };
  103. };