msm_serial_hs.txt 4.3 KB

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  1. * Qualcomm MSM HSUART
  2. Required properties:
  3. - compatible :
  4. - "qcom,msm-hsuart-v14" to be used for UARTDM Core v1.4
  5. - reg : offset and length of the register set for both the device,
  6. uart core and bam core
  7. - reg-names :
  8. - "core_mem" to be used as name of the uart core
  9. - "bam_mem" to be used as name of the bam core
  10. - interrupts : interrupts for both the device,uart core and bam core
  11. - interrupt-names :
  12. - "core_irq" to be used as uart irq
  13. - "bam irq" to be used as bam irq
  14. - #interrupt-cells: Specifies the number of cells needed to encode an interrupt
  15. source. The type shall be a <u32> and the value shall be 1
  16. - #address-cells: Specifies the number of cells needed to encode an address.
  17. The type shall be <u32> and the value shall be 0
  18. - interrupt-parent = It is needed for interrupt mapping
  19. - bam-tx-ep-pipe-index : BAM TX Endpoint Pipe Index for HSUART
  20. - bam-rx-ep-pipe-index : BAM RX Endpoint Pipe Index for HSUART
  21. BLSP has a static pipe allocation and assumes a pair-pipe for each uart core.
  22. Pipes [2*i : 2*i+1] are allocated for UART cores where i = [0 : 5].
  23. Hence, Minimum and Maximum permitted value of endpoint pipe index to be used
  24. with uart core is 0 and 11 respectively.
  25. There is one HSUART block used in MSM devices,
  26. "qcom,msm-hsuart-v14". The msm-serial-hs driver is
  27. able to handle this, and matches against the "qcom,msm-hsuart-v14"
  28. as the compatibility.
  29. The registers for the "qcom,msm-hsuart-v14" device need to specify both
  30. register blocks - uart core and bam core.
  31. Example:
  32. uart7: uart@f995d000 {
  33. compatible = "qcom,msm-hsuart-v14";
  34. reg = <0xf995d000 0x1000>,
  35. <0xf9944000 0x5000>;
  36. reg-names = "core_mem", "bam_mem";
  37. interrupt-names = "core_irq", "bam_irq";
  38. #address-cells = <0>;
  39. interrupt-parent = <&uart7>;
  40. interrupts = <0 1>;
  41. #interrupt-cells = <1>;
  42. interrupt-map = <0 &intc 0 113 0
  43. 1 &intc 0 239 0>
  44. qcom,bam-tx-ep-pipe-index = <0>;
  45. qcom,bam-rx-ep-pipe-index = <1>;
  46. };
  47. Optional properties:
  48. - qcom,<gpio-name>-gpio : handle to the GPIO node, see "gpios property" in
  49. Documentation/devicetree/bindings/gpio/gpio.txt.
  50. "gpio-name" can be "tx", "rx", "cts" and "rfr" based on number of UART GPIOs
  51. need to configured.
  52. Gpio's are optional if it is required to be not configured by UART driver or
  53. case where there is nothing connected and we want to use internal loopback mode
  54. for uart.
  55. - qcom, wakeup_irq : UART RX GPIO IRQ line to be configured as wakeup source.
  56. - qcom,inject-rx-on-wakeup : inject_rx_on_wakeup enables feature where on
  57. receiving interrupt with UART RX GPIO IRQ line (i.e. above wakeup_irq property),
  58. HSUART driver injects provided character with property rx_to_inject.
  59. - qcom, rx-char-to-inject : The character to be inserted on wakeup.
  60. - qcom, no-suspend-delay : This decides system to go to suspend immediately
  61. or not
  62. - Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
  63. below optional properties:
  64. - qcom,msm_bus,name
  65. - qcom,msm_bus,num_cases
  66. - qcom,msm_bus,active_only
  67. - qcom,msm_bus,num_paths
  68. - qcom,msm_bus,vectors
  69. Aliases :
  70. An alias may be optionally used to bind the UART device to a TTY device
  71. (ttyHS<alias_num>) with a given alias number. Aliases are of the form
  72. uart<n> where <n> is an integer representing the alias number to use.
  73. On systems with multiple UART devices present, an alias may optionally be
  74. defined for such devices. The alias value should be from 0 to 255.
  75. Example:
  76. aliases {
  77. uart4 = &uart7; // This device will be enumerated as ttyHS4
  78. };
  79. uart7: uart@f995d000 {
  80. compatible = "qcom,msm-hsuart-v14"
  81. reg = <0x19c40000 0x1000">,
  82. <0xf9944000 0x5000>;
  83. reg-names = "core_mem", "bam_mem";
  84. interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
  85. #address-cells = <0>;
  86. interrupt-parent = <&uart7>;
  87. interrupts = <0 1 2>;
  88. #interrupt-cells = <1>;
  89. interrupt-map-mask = <0xffffffff>;
  90. interrupt-map = <0 &intc 0 113 0
  91. 1 &intc 0 239 0
  92. 2 &msmgpio 42 0>;
  93. qcom,tx-gpio = <&msmgpio 41 0x00>;
  94. qcom,rx-gpio = <&msmgpio 42 0x00>;
  95. qcom,cts-gpio = <&msmgpio 43 0x00>;
  96. qcom,rfr-gpio = <&msmgpio 44 0x00>;
  97. qcom,inject-rx-on-wakeup = <1>;
  98. qcom,rx-char-to-inject = <0xFD>;
  99. qcom,bam-tx-ep-pipe-index = <0>;
  100. qcom,bam-rx-ep-pipe-index = <1>;
  101. qcom,msm-bus,name = "uart7";
  102. qcom,msm-bus,num-cases = <2>;
  103. qcom,msm-bus,num-paths = <1>;
  104. qcom,msm-bus,vectors-KBps =
  105. <84 512 0 0>,
  106. <84 512 500 800>;
  107. };