qpnp-rtc.txt 1.8 KB

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  1. * msm-qpnp-rtc
  2. msm-qpnp-rtc is a RTC driver that supports 32 bit RTC housed inside PMIC.
  3. Driver utilizes MSM SPMI interface to communicate with the RTC module.
  4. RTC device is divided into two sub-peripherals one which controls basic RTC
  5. and other for controlling alarm.
  6. [PMIC RTC Device Declarations]
  7. -Root Node-
  8. Required properties :
  9. - compatible: Must be "qcom,qpnp-rtc"
  10. - #address-cells: The number of cells dedicated to represent an address
  11. This must be set to '1'.
  12. - #size-cells: The number of cells dedicated to represent address
  13. space range of a peripheral. This must be set to '1'.
  14. - spmi-dev-container: This specifies that all the device nodes specified
  15. within this node should have their resources
  16. coalesced into a single spmi_device.
  17. Optional properties:
  18. - qcom,qpnp-rtc-write: This property enables/disables rtc write
  19. operation. If not mentioned rtc driver keeps
  20. rtc writes disabled.
  21. 0 = Disable rtc writes.
  22. 1 = Enable rtc writes.
  23. - qcom,qpnp-rtc-alarm-pwrup: This property enables/disables feature of
  24. powering up phone (from power down state)
  25. through alarm interrupt.
  26. If not mentioned rtc driver will disable
  27. feature of powring-up phone through alarm.
  28. 0 = Disable powering up of phone through
  29. alarm interrupt.
  30. 1 = Enable powering up of phone through
  31. alarm interrupt.
  32. -Child Nodes-
  33. Required properties :
  34. - reg : Specify the spmi offset and size for device.
  35. - interrupts: Specifies alarm interrupt, only for rtc_alarm
  36. sub-peripheral.
  37. Example:
  38. qcom,pm8941_rtc {
  39. spmi-dev-container;
  40. compatible = "qcom,qpnp-rtc";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. qcom,qpnp-rtc-write = <0>;
  44. qcom,qpnp-rtc-alarm-pwrup = <0>;
  45. qcom,pm8941_rtc_rw@6000 {
  46. reg = <0x6000 0x100>;
  47. };
  48. qcom,pm8941_rtc_alarm@6100 {
  49. reg = <0x6100 0x100>;
  50. interrupts = <0x0 0x61 0x1>;
  51. };
  52. };