8xxx_gpio.txt 1.8 KB

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  1. GPIO controllers on MPC8xxx SoCs
  2. This is for the non-QE/CPM/GUTs GPIO controllers as found on
  3. 8349, 8572, 8610 and compatible.
  4. Every GPIO controller node must have #gpio-cells property defined,
  5. this information will be used to translate gpio-specifiers.
  6. Required properties:
  7. - compatible : "fsl,<CHIP>-gpio" followed by "fsl,mpc8349-gpio" for
  8. 83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx.
  9. - #gpio-cells : Should be two. The first cell is the pin number and the
  10. second cell is used to specify optional parameters (currently unused).
  11. - interrupts : Interrupt mapping for GPIO IRQ.
  12. - interrupt-parent : Phandle for the interrupt controller that
  13. services interrupts for this device.
  14. - gpio-controller : Marks the port as GPIO controller.
  15. Example of gpio-controller nodes for a MPC8347 SoC:
  16. gpio1: gpio-controller@c00 {
  17. #gpio-cells = <2>;
  18. compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
  19. reg = <0xc00 0x100>;
  20. interrupts = <74 0x8>;
  21. interrupt-parent = <&ipic>;
  22. gpio-controller;
  23. };
  24. gpio2: gpio-controller@d00 {
  25. #gpio-cells = <2>;
  26. compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
  27. reg = <0xd00 0x100>;
  28. interrupts = <75 0x8>;
  29. interrupt-parent = <&ipic>;
  30. gpio-controller;
  31. };
  32. See booting-without-of.txt for details of how to specify GPIO
  33. information for devices.
  34. To use GPIO pins as interrupt sources for peripherals, specify the
  35. GPIO controller as the interrupt parent and define GPIO number +
  36. trigger mode using the interrupts property, which is defined like
  37. this:
  38. interrupts = <number trigger>, where:
  39. - number: GPIO pin (0..31)
  40. - trigger: trigger mode:
  41. 2 = trigger on falling edge
  42. 3 = trigger on both edges
  43. Example of device using this is:
  44. funkyfpga@0 {
  45. compatible = "funky-fpga";
  46. ...
  47. interrupts = <4 3>;
  48. interrupt-parent = <&gpio1>;
  49. };