fsl-sec2.txt 2.7 KB

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  1. Freescale SoC SEC Security Engines versions 2.x-3.x
  2. Required properties:
  3. - compatible : Should contain entries for this and backward compatible
  4. SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0"
  5. - reg : Offset and length of the register set for the device
  6. - interrupts : the SEC's interrupt number
  7. - fsl,num-channels : An integer representing the number of channels
  8. available.
  9. - fsl,channel-fifo-len : An integer representing the number of
  10. descriptor pointers each channel fetch fifo can hold.
  11. - fsl,exec-units-mask : The bitmask representing what execution units
  12. (EUs) are available. It's a single 32-bit cell. EU information
  13. should be encoded following the SEC's Descriptor Header Dword
  14. EU_SEL0 field documentation, i.e. as follows:
  15. bit 0 = reserved - should be 0
  16. bit 1 = set if SEC has the ARC4 EU (AFEU)
  17. bit 2 = set if SEC has the DES/3DES EU (DEU)
  18. bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
  19. bit 4 = set if SEC has the random number generator EU (RNG)
  20. bit 5 = set if SEC has the public key EU (PKEU)
  21. bit 6 = set if SEC has the AES EU (AESU)
  22. bit 7 = set if SEC has the Kasumi EU (KEU)
  23. bit 8 = set if SEC has the CRC EU (CRCU)
  24. bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
  25. remaining bits are reserved for future SEC EUs.
  26. - fsl,descriptor-types-mask : The bitmask representing what descriptors
  27. are available. It's a single 32-bit cell. Descriptor type information
  28. should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
  29. field documentation, i.e. as follows:
  30. bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
  31. bit 1 = set if SEC supports the ipsec_esp descriptor type
  32. bit 2 = set if SEC supports the common_nonsnoop desc. type
  33. bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
  34. bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
  35. bit 5 = set if SEC supports the srtp descriptor type
  36. bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
  37. bit 7 = set if SEC supports the pkeu_assemble descriptor type
  38. bit 8 = set if SEC supports the aesu_key_expand_output desc.type
  39. bit 9 = set if SEC supports the pkeu_ptmul descriptor type
  40. bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
  41. bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
  42. ..and so on and so forth.
  43. Optional properties:
  44. - interrupt-parent : the phandle for the interrupt controller that
  45. services interrupts for this device.
  46. Example:
  47. /* MPC8548E */
  48. crypto@30000 {
  49. compatible = "fsl,sec2.1", "fsl,sec2.0";
  50. reg = <0x30000 0x10000>;
  51. interrupts = <29 2>;
  52. interrupt-parent = <&mpic>;
  53. fsl,num-channels = <4>;
  54. fsl,channel-fifo-len = <24>;
  55. fsl,exec-units-mask = <0xfe>;
  56. fsl,descriptor-types-mask = <0x12b0ebf>;
  57. };