cpus.txt 1.5 KB

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  1. * ARM CPUs binding description
  2. The device tree allows to describe the layout of CPUs in a system through
  3. the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
  4. defining properties for every cpu.
  5. Bindings for CPU nodes follow the ePAPR standard, available from:
  6. http://devicetree.org
  7. For the ARM architecture every CPU node must contain the following properties:
  8. - device_type: must be "cpu"
  9. - reg: property matching the CPU MPIDR[23:0] register bits
  10. reg[31:24] bits must be set to 0
  11. - compatible: should be one of:
  12. "arm,arm1020"
  13. "arm,arm1020e"
  14. "arm,arm1022"
  15. "arm,arm1026"
  16. "arm,arm720"
  17. "arm,arm740"
  18. "arm,arm7tdmi"
  19. "arm,arm920"
  20. "arm,arm922"
  21. "arm,arm925"
  22. "arm,arm926"
  23. "arm,arm940"
  24. "arm,arm946"
  25. "arm,arm9tdmi"
  26. "arm,cortex-a5"
  27. "arm,cortex-a7"
  28. "arm,cortex-a8"
  29. "arm,cortex-a9"
  30. "arm,cortex-a15"
  31. "arm,arm1136"
  32. "arm,arm1156"
  33. "arm,arm1176"
  34. "arm,arm11mpcore"
  35. "faraday,fa526"
  36. "intel,sa110"
  37. "intel,sa1100"
  38. "marvell,feroceon"
  39. "marvell,mohawk"
  40. "marvell,xsc3"
  41. "marvell,xscale"
  42. "qcom,krait"
  43. Example:
  44. cpus {
  45. #size-cells = <0>;
  46. #address-cells = <1>;
  47. CPU0: cpu@0 {
  48. device_type = "cpu";
  49. compatible = "arm,cortex-a15";
  50. reg = <0x0>;
  51. };
  52. CPU1: cpu@1 {
  53. device_type = "cpu";
  54. compatible = "arm,cortex-a15";
  55. reg = <0x1>;
  56. };
  57. CPU2: cpu@100 {
  58. device_type = "cpu";
  59. compatible = "arm,cortex-a7";
  60. reg = <0x100>;
  61. };
  62. CPU3: cpu@101 {
  63. device_type = "cpu";
  64. compatible = "arm,cortex-a7";
  65. reg = <0x101>;
  66. };
  67. };