s3c2410_udc.c 49 KB

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  1. /*
  2. * linux/drivers/usb/gadget/s3c2410_udc.c
  3. *
  4. * Samsung S3C24xx series on-chip full speed USB device controllers
  5. *
  6. * Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
  7. * Additional cleanups by Ben Dooks <ben-linux@fluff.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <linux/delay.h>
  17. #include <linux/ioport.h>
  18. #include <linux/sched.h>
  19. #include <linux/slab.h>
  20. #include <linux/errno.h>
  21. #include <linux/init.h>
  22. #include <linux/timer.h>
  23. #include <linux/list.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/clk.h>
  27. #include <linux/gpio.h>
  28. #include <linux/prefetch.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/seq_file.h>
  31. #include <linux/usb.h>
  32. #include <linux/usb/gadget.h>
  33. #include <asm/byteorder.h>
  34. #include <asm/io.h>
  35. #include <asm/irq.h>
  36. #include <asm/unaligned.h>
  37. #include <mach/irqs.h>
  38. #include <mach/hardware.h>
  39. #include <plat/regs-udc.h>
  40. #include <plat/udc.h>
  41. #include "s3c2410_udc.h"
  42. #define DRIVER_DESC "S3C2410 USB Device Controller Gadget"
  43. #define DRIVER_VERSION "29 Apr 2007"
  44. #define DRIVER_AUTHOR "Herbert Pötzl <herbert@13thfloor.at>, " \
  45. "Arnaud Patard <arnaud.patard@rtp-net.org>"
  46. static const char gadget_name[] = "s3c2410_udc";
  47. static const char driver_desc[] = DRIVER_DESC;
  48. static struct s3c2410_udc *the_controller;
  49. static struct clk *udc_clock;
  50. static struct clk *usb_bus_clock;
  51. static void __iomem *base_addr;
  52. static u64 rsrc_start;
  53. static u64 rsrc_len;
  54. static struct dentry *s3c2410_udc_debugfs_root;
  55. static inline u32 udc_read(u32 reg)
  56. {
  57. return readb(base_addr + reg);
  58. }
  59. static inline void udc_write(u32 value, u32 reg)
  60. {
  61. writeb(value, base_addr + reg);
  62. }
  63. static inline void udc_writeb(void __iomem *base, u32 value, u32 reg)
  64. {
  65. writeb(value, base + reg);
  66. }
  67. static struct s3c2410_udc_mach_info *udc_info;
  68. /*************************** DEBUG FUNCTION ***************************/
  69. #define DEBUG_NORMAL 1
  70. #define DEBUG_VERBOSE 2
  71. #ifdef CONFIG_USB_S3C2410_DEBUG
  72. #define USB_S3C2410_DEBUG_LEVEL 0
  73. static uint32_t s3c2410_ticks = 0;
  74. static int dprintk(int level, const char *fmt, ...)
  75. {
  76. static char printk_buf[1024];
  77. static long prevticks;
  78. static int invocation;
  79. va_list args;
  80. int len;
  81. if (level > USB_S3C2410_DEBUG_LEVEL)
  82. return 0;
  83. if (s3c2410_ticks != prevticks) {
  84. prevticks = s3c2410_ticks;
  85. invocation = 0;
  86. }
  87. len = scnprintf(printk_buf,
  88. sizeof(printk_buf), "%1lu.%02d USB: ",
  89. prevticks, invocation++);
  90. va_start(args, fmt);
  91. len = vscnprintf(printk_buf+len,
  92. sizeof(printk_buf)-len, fmt, args);
  93. va_end(args);
  94. return printk(KERN_DEBUG "%s", printk_buf);
  95. }
  96. #else
  97. static int dprintk(int level, const char *fmt, ...)
  98. {
  99. return 0;
  100. }
  101. #endif
  102. static int s3c2410_udc_debugfs_seq_show(struct seq_file *m, void *p)
  103. {
  104. u32 addr_reg,pwr_reg,ep_int_reg,usb_int_reg;
  105. u32 ep_int_en_reg, usb_int_en_reg, ep0_csr;
  106. u32 ep1_i_csr1,ep1_i_csr2,ep1_o_csr1,ep1_o_csr2;
  107. u32 ep2_i_csr1,ep2_i_csr2,ep2_o_csr1,ep2_o_csr2;
  108. addr_reg = udc_read(S3C2410_UDC_FUNC_ADDR_REG);
  109. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  110. ep_int_reg = udc_read(S3C2410_UDC_EP_INT_REG);
  111. usb_int_reg = udc_read(S3C2410_UDC_USB_INT_REG);
  112. ep_int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  113. usb_int_en_reg = udc_read(S3C2410_UDC_USB_INT_EN_REG);
  114. udc_write(0, S3C2410_UDC_INDEX_REG);
  115. ep0_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  116. udc_write(1, S3C2410_UDC_INDEX_REG);
  117. ep1_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  118. ep1_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  119. ep1_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  120. ep1_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  121. udc_write(2, S3C2410_UDC_INDEX_REG);
  122. ep2_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  123. ep2_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  124. ep2_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  125. ep2_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  126. seq_printf(m, "FUNC_ADDR_REG : 0x%04X\n"
  127. "PWR_REG : 0x%04X\n"
  128. "EP_INT_REG : 0x%04X\n"
  129. "USB_INT_REG : 0x%04X\n"
  130. "EP_INT_EN_REG : 0x%04X\n"
  131. "USB_INT_EN_REG : 0x%04X\n"
  132. "EP0_CSR : 0x%04X\n"
  133. "EP1_I_CSR1 : 0x%04X\n"
  134. "EP1_I_CSR2 : 0x%04X\n"
  135. "EP1_O_CSR1 : 0x%04X\n"
  136. "EP1_O_CSR2 : 0x%04X\n"
  137. "EP2_I_CSR1 : 0x%04X\n"
  138. "EP2_I_CSR2 : 0x%04X\n"
  139. "EP2_O_CSR1 : 0x%04X\n"
  140. "EP2_O_CSR2 : 0x%04X\n",
  141. addr_reg,pwr_reg,ep_int_reg,usb_int_reg,
  142. ep_int_en_reg, usb_int_en_reg, ep0_csr,
  143. ep1_i_csr1,ep1_i_csr2,ep1_o_csr1,ep1_o_csr2,
  144. ep2_i_csr1,ep2_i_csr2,ep2_o_csr1,ep2_o_csr2
  145. );
  146. return 0;
  147. }
  148. static int s3c2410_udc_debugfs_fops_open(struct inode *inode,
  149. struct file *file)
  150. {
  151. return single_open(file, s3c2410_udc_debugfs_seq_show, NULL);
  152. }
  153. static const struct file_operations s3c2410_udc_debugfs_fops = {
  154. .open = s3c2410_udc_debugfs_fops_open,
  155. .read = seq_read,
  156. .llseek = seq_lseek,
  157. .release = single_release,
  158. .owner = THIS_MODULE,
  159. };
  160. /* io macros */
  161. static inline void s3c2410_udc_clear_ep0_opr(void __iomem *base)
  162. {
  163. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  164. udc_writeb(base, S3C2410_UDC_EP0_CSR_SOPKTRDY,
  165. S3C2410_UDC_EP0_CSR_REG);
  166. }
  167. static inline void s3c2410_udc_clear_ep0_sst(void __iomem *base)
  168. {
  169. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  170. writeb(0x00, base + S3C2410_UDC_EP0_CSR_REG);
  171. }
  172. static inline void s3c2410_udc_clear_ep0_se(void __iomem *base)
  173. {
  174. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  175. udc_writeb(base, S3C2410_UDC_EP0_CSR_SSE, S3C2410_UDC_EP0_CSR_REG);
  176. }
  177. static inline void s3c2410_udc_set_ep0_ipr(void __iomem *base)
  178. {
  179. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  180. udc_writeb(base, S3C2410_UDC_EP0_CSR_IPKRDY, S3C2410_UDC_EP0_CSR_REG);
  181. }
  182. static inline void s3c2410_udc_set_ep0_de(void __iomem *base)
  183. {
  184. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  185. udc_writeb(base, S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_EP0_CSR_REG);
  186. }
  187. inline void s3c2410_udc_set_ep0_ss(void __iomem *b)
  188. {
  189. udc_writeb(b, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  190. udc_writeb(b, S3C2410_UDC_EP0_CSR_SENDSTL, S3C2410_UDC_EP0_CSR_REG);
  191. }
  192. static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base)
  193. {
  194. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  195. udc_writeb(base,(S3C2410_UDC_EP0_CSR_SOPKTRDY
  196. | S3C2410_UDC_EP0_CSR_DE),
  197. S3C2410_UDC_EP0_CSR_REG);
  198. }
  199. static inline void s3c2410_udc_set_ep0_sse_out(void __iomem *base)
  200. {
  201. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  202. udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
  203. | S3C2410_UDC_EP0_CSR_SSE),
  204. S3C2410_UDC_EP0_CSR_REG);
  205. }
  206. static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base)
  207. {
  208. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  209. udc_writeb(base, (S3C2410_UDC_EP0_CSR_IPKRDY
  210. | S3C2410_UDC_EP0_CSR_DE),
  211. S3C2410_UDC_EP0_CSR_REG);
  212. }
  213. /*------------------------- I/O ----------------------------------*/
  214. /*
  215. * s3c2410_udc_done
  216. */
  217. static void s3c2410_udc_done(struct s3c2410_ep *ep,
  218. struct s3c2410_request *req, int status)
  219. {
  220. unsigned halted = ep->halted;
  221. list_del_init(&req->queue);
  222. if (likely (req->req.status == -EINPROGRESS))
  223. req->req.status = status;
  224. else
  225. status = req->req.status;
  226. ep->halted = 1;
  227. req->req.complete(&ep->ep, &req->req);
  228. ep->halted = halted;
  229. }
  230. static void s3c2410_udc_nuke(struct s3c2410_udc *udc,
  231. struct s3c2410_ep *ep, int status)
  232. {
  233. /* Sanity check */
  234. if (&ep->queue == NULL)
  235. return;
  236. while (!list_empty (&ep->queue)) {
  237. struct s3c2410_request *req;
  238. req = list_entry (ep->queue.next, struct s3c2410_request,
  239. queue);
  240. s3c2410_udc_done(ep, req, status);
  241. }
  242. }
  243. static inline void s3c2410_udc_clear_ep_state(struct s3c2410_udc *dev)
  244. {
  245. unsigned i;
  246. /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
  247. * fifos, and pending transactions mustn't be continued in any case.
  248. */
  249. for (i = 1; i < S3C2410_ENDPOINTS; i++)
  250. s3c2410_udc_nuke(dev, &dev->ep[i], -ECONNABORTED);
  251. }
  252. static inline int s3c2410_udc_fifo_count_out(void)
  253. {
  254. int tmp;
  255. tmp = udc_read(S3C2410_UDC_OUT_FIFO_CNT2_REG) << 8;
  256. tmp |= udc_read(S3C2410_UDC_OUT_FIFO_CNT1_REG);
  257. return tmp;
  258. }
  259. /*
  260. * s3c2410_udc_write_packet
  261. */
  262. static inline int s3c2410_udc_write_packet(int fifo,
  263. struct s3c2410_request *req,
  264. unsigned max)
  265. {
  266. unsigned len = min(req->req.length - req->req.actual, max);
  267. u8 *buf = req->req.buf + req->req.actual;
  268. prefetch(buf);
  269. dprintk(DEBUG_VERBOSE, "%s %d %d %d %d\n", __func__,
  270. req->req.actual, req->req.length, len, req->req.actual + len);
  271. req->req.actual += len;
  272. udelay(5);
  273. writesb(base_addr + fifo, buf, len);
  274. return len;
  275. }
  276. /*
  277. * s3c2410_udc_write_fifo
  278. *
  279. * return: 0 = still running, 1 = completed, negative = errno
  280. */
  281. static int s3c2410_udc_write_fifo(struct s3c2410_ep *ep,
  282. struct s3c2410_request *req)
  283. {
  284. unsigned count;
  285. int is_last;
  286. u32 idx;
  287. int fifo_reg;
  288. u32 ep_csr;
  289. idx = ep->bEndpointAddress & 0x7F;
  290. switch (idx) {
  291. default:
  292. idx = 0;
  293. case 0:
  294. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  295. break;
  296. case 1:
  297. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  298. break;
  299. case 2:
  300. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  301. break;
  302. case 3:
  303. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  304. break;
  305. case 4:
  306. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  307. break;
  308. }
  309. count = s3c2410_udc_write_packet(fifo_reg, req, ep->ep.maxpacket);
  310. /* last packet is often short (sometimes a zlp) */
  311. if (count != ep->ep.maxpacket)
  312. is_last = 1;
  313. else if (req->req.length != req->req.actual || req->req.zero)
  314. is_last = 0;
  315. else
  316. is_last = 2;
  317. /* Only ep0 debug messages are interesting */
  318. if (idx == 0)
  319. dprintk(DEBUG_NORMAL,
  320. "Written ep%d %d.%d of %d b [last %d,z %d]\n",
  321. idx, count, req->req.actual, req->req.length,
  322. is_last, req->req.zero);
  323. if (is_last) {
  324. /* The order is important. It prevents sending 2 packets
  325. * at the same time */
  326. if (idx == 0) {
  327. /* Reset signal => no need to say 'data sent' */
  328. if (! (udc_read(S3C2410_UDC_USB_INT_REG)
  329. & S3C2410_UDC_USBINT_RESET))
  330. s3c2410_udc_set_ep0_de_in(base_addr);
  331. ep->dev->ep0state=EP0_IDLE;
  332. } else {
  333. udc_write(idx, S3C2410_UDC_INDEX_REG);
  334. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  335. udc_write(idx, S3C2410_UDC_INDEX_REG);
  336. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  337. S3C2410_UDC_IN_CSR1_REG);
  338. }
  339. s3c2410_udc_done(ep, req, 0);
  340. is_last = 1;
  341. } else {
  342. if (idx == 0) {
  343. /* Reset signal => no need to say 'data sent' */
  344. if (! (udc_read(S3C2410_UDC_USB_INT_REG)
  345. & S3C2410_UDC_USBINT_RESET))
  346. s3c2410_udc_set_ep0_ipr(base_addr);
  347. } else {
  348. udc_write(idx, S3C2410_UDC_INDEX_REG);
  349. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  350. udc_write(idx, S3C2410_UDC_INDEX_REG);
  351. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  352. S3C2410_UDC_IN_CSR1_REG);
  353. }
  354. }
  355. return is_last;
  356. }
  357. static inline int s3c2410_udc_read_packet(int fifo, u8 *buf,
  358. struct s3c2410_request *req, unsigned avail)
  359. {
  360. unsigned len;
  361. len = min(req->req.length - req->req.actual, avail);
  362. req->req.actual += len;
  363. readsb(fifo + base_addr, buf, len);
  364. return len;
  365. }
  366. /*
  367. * return: 0 = still running, 1 = queue empty, negative = errno
  368. */
  369. static int s3c2410_udc_read_fifo(struct s3c2410_ep *ep,
  370. struct s3c2410_request *req)
  371. {
  372. u8 *buf;
  373. u32 ep_csr;
  374. unsigned bufferspace;
  375. int is_last=1;
  376. unsigned avail;
  377. int fifo_count = 0;
  378. u32 idx;
  379. int fifo_reg;
  380. idx = ep->bEndpointAddress & 0x7F;
  381. switch (idx) {
  382. default:
  383. idx = 0;
  384. case 0:
  385. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  386. break;
  387. case 1:
  388. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  389. break;
  390. case 2:
  391. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  392. break;
  393. case 3:
  394. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  395. break;
  396. case 4:
  397. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  398. break;
  399. }
  400. if (!req->req.length)
  401. return 1;
  402. buf = req->req.buf + req->req.actual;
  403. bufferspace = req->req.length - req->req.actual;
  404. if (!bufferspace) {
  405. dprintk(DEBUG_NORMAL, "%s: buffer full!\n", __func__);
  406. return -1;
  407. }
  408. udc_write(idx, S3C2410_UDC_INDEX_REG);
  409. fifo_count = s3c2410_udc_fifo_count_out();
  410. dprintk(DEBUG_NORMAL, "%s fifo count : %d\n", __func__, fifo_count);
  411. if (fifo_count > ep->ep.maxpacket)
  412. avail = ep->ep.maxpacket;
  413. else
  414. avail = fifo_count;
  415. fifo_count = s3c2410_udc_read_packet(fifo_reg, buf, req, avail);
  416. /* checking this with ep0 is not accurate as we already
  417. * read a control request
  418. **/
  419. if (idx != 0 && fifo_count < ep->ep.maxpacket) {
  420. is_last = 1;
  421. /* overflowed this request? flush extra data */
  422. if (fifo_count != avail)
  423. req->req.status = -EOVERFLOW;
  424. } else {
  425. is_last = (req->req.length <= req->req.actual) ? 1 : 0;
  426. }
  427. udc_write(idx, S3C2410_UDC_INDEX_REG);
  428. fifo_count = s3c2410_udc_fifo_count_out();
  429. /* Only ep0 debug messages are interesting */
  430. if (idx == 0)
  431. dprintk(DEBUG_VERBOSE, "%s fifo count : %d [last %d]\n",
  432. __func__, fifo_count,is_last);
  433. if (is_last) {
  434. if (idx == 0) {
  435. s3c2410_udc_set_ep0_de_out(base_addr);
  436. ep->dev->ep0state = EP0_IDLE;
  437. } else {
  438. udc_write(idx, S3C2410_UDC_INDEX_REG);
  439. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  440. udc_write(idx, S3C2410_UDC_INDEX_REG);
  441. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  442. S3C2410_UDC_OUT_CSR1_REG);
  443. }
  444. s3c2410_udc_done(ep, req, 0);
  445. } else {
  446. if (idx == 0) {
  447. s3c2410_udc_clear_ep0_opr(base_addr);
  448. } else {
  449. udc_write(idx, S3C2410_UDC_INDEX_REG);
  450. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  451. udc_write(idx, S3C2410_UDC_INDEX_REG);
  452. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  453. S3C2410_UDC_OUT_CSR1_REG);
  454. }
  455. }
  456. return is_last;
  457. }
  458. static int s3c2410_udc_read_fifo_crq(struct usb_ctrlrequest *crq)
  459. {
  460. unsigned char *outbuf = (unsigned char*)crq;
  461. int bytes_read = 0;
  462. udc_write(0, S3C2410_UDC_INDEX_REG);
  463. bytes_read = s3c2410_udc_fifo_count_out();
  464. dprintk(DEBUG_NORMAL, "%s: fifo_count=%d\n", __func__, bytes_read);
  465. if (bytes_read > sizeof(struct usb_ctrlrequest))
  466. bytes_read = sizeof(struct usb_ctrlrequest);
  467. readsb(S3C2410_UDC_EP0_FIFO_REG + base_addr, outbuf, bytes_read);
  468. dprintk(DEBUG_VERBOSE, "%s: len=%d %02x:%02x {%x,%x,%x}\n", __func__,
  469. bytes_read, crq->bRequest, crq->bRequestType,
  470. crq->wValue, crq->wIndex, crq->wLength);
  471. return bytes_read;
  472. }
  473. static int s3c2410_udc_get_status(struct s3c2410_udc *dev,
  474. struct usb_ctrlrequest *crq)
  475. {
  476. u16 status = 0;
  477. u8 ep_num = crq->wIndex & 0x7F;
  478. u8 is_in = crq->wIndex & USB_DIR_IN;
  479. switch (crq->bRequestType & USB_RECIP_MASK) {
  480. case USB_RECIP_INTERFACE:
  481. break;
  482. case USB_RECIP_DEVICE:
  483. status = dev->devstatus;
  484. break;
  485. case USB_RECIP_ENDPOINT:
  486. if (ep_num > 4 || crq->wLength > 2)
  487. return 1;
  488. if (ep_num == 0) {
  489. udc_write(0, S3C2410_UDC_INDEX_REG);
  490. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  491. status = status & S3C2410_UDC_EP0_CSR_SENDSTL;
  492. } else {
  493. udc_write(ep_num, S3C2410_UDC_INDEX_REG);
  494. if (is_in) {
  495. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  496. status = status & S3C2410_UDC_ICSR1_SENDSTL;
  497. } else {
  498. status = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  499. status = status & S3C2410_UDC_OCSR1_SENDSTL;
  500. }
  501. }
  502. status = status ? 1 : 0;
  503. break;
  504. default:
  505. return 1;
  506. }
  507. /* Seems to be needed to get it working. ouch :( */
  508. udelay(5);
  509. udc_write(status & 0xFF, S3C2410_UDC_EP0_FIFO_REG);
  510. udc_write(status >> 8, S3C2410_UDC_EP0_FIFO_REG);
  511. s3c2410_udc_set_ep0_de_in(base_addr);
  512. return 0;
  513. }
  514. /*------------------------- usb state machine -------------------------------*/
  515. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value);
  516. static void s3c2410_udc_handle_ep0_idle(struct s3c2410_udc *dev,
  517. struct s3c2410_ep *ep,
  518. struct usb_ctrlrequest *crq,
  519. u32 ep0csr)
  520. {
  521. int len, ret, tmp;
  522. /* start control request? */
  523. if (!(ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY))
  524. return;
  525. s3c2410_udc_nuke(dev, ep, -EPROTO);
  526. len = s3c2410_udc_read_fifo_crq(crq);
  527. if (len != sizeof(*crq)) {
  528. dprintk(DEBUG_NORMAL, "setup begin: fifo READ ERROR"
  529. " wanted %d bytes got %d. Stalling out...\n",
  530. sizeof(*crq), len);
  531. s3c2410_udc_set_ep0_ss(base_addr);
  532. return;
  533. }
  534. dprintk(DEBUG_NORMAL, "bRequest = %d bRequestType %d wLength = %d\n",
  535. crq->bRequest, crq->bRequestType, crq->wLength);
  536. /* cope with automagic for some standard requests. */
  537. dev->req_std = (crq->bRequestType & USB_TYPE_MASK)
  538. == USB_TYPE_STANDARD;
  539. dev->req_config = 0;
  540. dev->req_pending = 1;
  541. switch (crq->bRequest) {
  542. case USB_REQ_SET_CONFIGURATION:
  543. dprintk(DEBUG_NORMAL, "USB_REQ_SET_CONFIGURATION ... \n");
  544. if (crq->bRequestType == USB_RECIP_DEVICE) {
  545. dev->req_config = 1;
  546. s3c2410_udc_set_ep0_de_out(base_addr);
  547. }
  548. break;
  549. case USB_REQ_SET_INTERFACE:
  550. dprintk(DEBUG_NORMAL, "USB_REQ_SET_INTERFACE ... \n");
  551. if (crq->bRequestType == USB_RECIP_INTERFACE) {
  552. dev->req_config = 1;
  553. s3c2410_udc_set_ep0_de_out(base_addr);
  554. }
  555. break;
  556. case USB_REQ_SET_ADDRESS:
  557. dprintk(DEBUG_NORMAL, "USB_REQ_SET_ADDRESS ... \n");
  558. if (crq->bRequestType == USB_RECIP_DEVICE) {
  559. tmp = crq->wValue & 0x7F;
  560. dev->address = tmp;
  561. udc_write((tmp | S3C2410_UDC_FUNCADDR_UPDATE),
  562. S3C2410_UDC_FUNC_ADDR_REG);
  563. s3c2410_udc_set_ep0_de_out(base_addr);
  564. return;
  565. }
  566. break;
  567. case USB_REQ_GET_STATUS:
  568. dprintk(DEBUG_NORMAL, "USB_REQ_GET_STATUS ... \n");
  569. s3c2410_udc_clear_ep0_opr(base_addr);
  570. if (dev->req_std) {
  571. if (!s3c2410_udc_get_status(dev, crq)) {
  572. return;
  573. }
  574. }
  575. break;
  576. case USB_REQ_CLEAR_FEATURE:
  577. s3c2410_udc_clear_ep0_opr(base_addr);
  578. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  579. break;
  580. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  581. break;
  582. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0);
  583. s3c2410_udc_set_ep0_de_out(base_addr);
  584. return;
  585. case USB_REQ_SET_FEATURE:
  586. s3c2410_udc_clear_ep0_opr(base_addr);
  587. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  588. break;
  589. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  590. break;
  591. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1);
  592. s3c2410_udc_set_ep0_de_out(base_addr);
  593. return;
  594. default:
  595. s3c2410_udc_clear_ep0_opr(base_addr);
  596. break;
  597. }
  598. if (crq->bRequestType & USB_DIR_IN)
  599. dev->ep0state = EP0_IN_DATA_PHASE;
  600. else
  601. dev->ep0state = EP0_OUT_DATA_PHASE;
  602. if (!dev->driver)
  603. return;
  604. /* deliver the request to the gadget driver */
  605. ret = dev->driver->setup(&dev->gadget, crq);
  606. if (ret < 0) {
  607. if (dev->req_config) {
  608. dprintk(DEBUG_NORMAL, "config change %02x fail %d?\n",
  609. crq->bRequest, ret);
  610. return;
  611. }
  612. if (ret == -EOPNOTSUPP)
  613. dprintk(DEBUG_NORMAL, "Operation not supported\n");
  614. else
  615. dprintk(DEBUG_NORMAL,
  616. "dev->driver->setup failed. (%d)\n", ret);
  617. udelay(5);
  618. s3c2410_udc_set_ep0_ss(base_addr);
  619. s3c2410_udc_set_ep0_de_out(base_addr);
  620. dev->ep0state = EP0_IDLE;
  621. /* deferred i/o == no response yet */
  622. } else if (dev->req_pending) {
  623. dprintk(DEBUG_VERBOSE, "dev->req_pending... what now?\n");
  624. dev->req_pending=0;
  625. }
  626. dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]);
  627. }
  628. static void s3c2410_udc_handle_ep0(struct s3c2410_udc *dev)
  629. {
  630. u32 ep0csr;
  631. struct s3c2410_ep *ep = &dev->ep[0];
  632. struct s3c2410_request *req;
  633. struct usb_ctrlrequest crq;
  634. if (list_empty(&ep->queue))
  635. req = NULL;
  636. else
  637. req = list_entry(ep->queue.next, struct s3c2410_request, queue);
  638. /* We make the assumption that S3C2410_UDC_IN_CSR1_REG equal to
  639. * S3C2410_UDC_EP0_CSR_REG when index is zero */
  640. udc_write(0, S3C2410_UDC_INDEX_REG);
  641. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  642. dprintk(DEBUG_NORMAL, "ep0csr %x ep0state %s\n",
  643. ep0csr, ep0states[dev->ep0state]);
  644. /* clear stall status */
  645. if (ep0csr & S3C2410_UDC_EP0_CSR_SENTSTL) {
  646. s3c2410_udc_nuke(dev, ep, -EPIPE);
  647. dprintk(DEBUG_NORMAL, "... clear SENT_STALL ...\n");
  648. s3c2410_udc_clear_ep0_sst(base_addr);
  649. dev->ep0state = EP0_IDLE;
  650. return;
  651. }
  652. /* clear setup end */
  653. if (ep0csr & S3C2410_UDC_EP0_CSR_SE) {
  654. dprintk(DEBUG_NORMAL, "... serviced SETUP_END ...\n");
  655. s3c2410_udc_nuke(dev, ep, 0);
  656. s3c2410_udc_clear_ep0_se(base_addr);
  657. dev->ep0state = EP0_IDLE;
  658. }
  659. switch (dev->ep0state) {
  660. case EP0_IDLE:
  661. s3c2410_udc_handle_ep0_idle(dev, ep, &crq, ep0csr);
  662. break;
  663. case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
  664. dprintk(DEBUG_NORMAL, "EP0_IN_DATA_PHASE ... what now?\n");
  665. if (!(ep0csr & S3C2410_UDC_EP0_CSR_IPKRDY) && req) {
  666. s3c2410_udc_write_fifo(ep, req);
  667. }
  668. break;
  669. case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
  670. dprintk(DEBUG_NORMAL, "EP0_OUT_DATA_PHASE ... what now?\n");
  671. if ((ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY) && req ) {
  672. s3c2410_udc_read_fifo(ep,req);
  673. }
  674. break;
  675. case EP0_END_XFER:
  676. dprintk(DEBUG_NORMAL, "EP0_END_XFER ... what now?\n");
  677. dev->ep0state = EP0_IDLE;
  678. break;
  679. case EP0_STALL:
  680. dprintk(DEBUG_NORMAL, "EP0_STALL ... what now?\n");
  681. dev->ep0state = EP0_IDLE;
  682. break;
  683. }
  684. }
  685. /*
  686. * handle_ep - Manage I/O endpoints
  687. */
  688. static void s3c2410_udc_handle_ep(struct s3c2410_ep *ep)
  689. {
  690. struct s3c2410_request *req;
  691. int is_in = ep->bEndpointAddress & USB_DIR_IN;
  692. u32 ep_csr1;
  693. u32 idx;
  694. if (likely (!list_empty(&ep->queue)))
  695. req = list_entry(ep->queue.next,
  696. struct s3c2410_request, queue);
  697. else
  698. req = NULL;
  699. idx = ep->bEndpointAddress & 0x7F;
  700. if (is_in) {
  701. udc_write(idx, S3C2410_UDC_INDEX_REG);
  702. ep_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  703. dprintk(DEBUG_VERBOSE, "ep%01d write csr:%02x %d\n",
  704. idx, ep_csr1, req ? 1 : 0);
  705. if (ep_csr1 & S3C2410_UDC_ICSR1_SENTSTL) {
  706. dprintk(DEBUG_VERBOSE, "st\n");
  707. udc_write(idx, S3C2410_UDC_INDEX_REG);
  708. udc_write(ep_csr1 & ~S3C2410_UDC_ICSR1_SENTSTL,
  709. S3C2410_UDC_IN_CSR1_REG);
  710. return;
  711. }
  712. if (!(ep_csr1 & S3C2410_UDC_ICSR1_PKTRDY) && req) {
  713. s3c2410_udc_write_fifo(ep,req);
  714. }
  715. } else {
  716. udc_write(idx, S3C2410_UDC_INDEX_REG);
  717. ep_csr1 = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  718. dprintk(DEBUG_VERBOSE, "ep%01d rd csr:%02x\n", idx, ep_csr1);
  719. if (ep_csr1 & S3C2410_UDC_OCSR1_SENTSTL) {
  720. udc_write(idx, S3C2410_UDC_INDEX_REG);
  721. udc_write(ep_csr1 & ~S3C2410_UDC_OCSR1_SENTSTL,
  722. S3C2410_UDC_OUT_CSR1_REG);
  723. return;
  724. }
  725. if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req) {
  726. s3c2410_udc_read_fifo(ep,req);
  727. }
  728. }
  729. }
  730. #include <mach/regs-irq.h>
  731. /*
  732. * s3c2410_udc_irq - interrupt handler
  733. */
  734. static irqreturn_t s3c2410_udc_irq(int dummy, void *_dev)
  735. {
  736. struct s3c2410_udc *dev = _dev;
  737. int usb_status;
  738. int usbd_status;
  739. int pwr_reg;
  740. int ep0csr;
  741. int i;
  742. u32 idx, idx2;
  743. unsigned long flags;
  744. spin_lock_irqsave(&dev->lock, flags);
  745. /* Driver connected ? */
  746. if (!dev->driver) {
  747. /* Clear interrupts */
  748. udc_write(udc_read(S3C2410_UDC_USB_INT_REG),
  749. S3C2410_UDC_USB_INT_REG);
  750. udc_write(udc_read(S3C2410_UDC_EP_INT_REG),
  751. S3C2410_UDC_EP_INT_REG);
  752. }
  753. /* Save index */
  754. idx = udc_read(S3C2410_UDC_INDEX_REG);
  755. /* Read status registers */
  756. usb_status = udc_read(S3C2410_UDC_USB_INT_REG);
  757. usbd_status = udc_read(S3C2410_UDC_EP_INT_REG);
  758. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  759. udc_writeb(base_addr, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  760. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  761. dprintk(DEBUG_NORMAL, "usbs=%02x, usbds=%02x, pwr=%02x ep0csr=%02x\n",
  762. usb_status, usbd_status, pwr_reg, ep0csr);
  763. /*
  764. * Now, handle interrupts. There's two types :
  765. * - Reset, Resume, Suspend coming -> usb_int_reg
  766. * - EP -> ep_int_reg
  767. */
  768. /* RESET */
  769. if (usb_status & S3C2410_UDC_USBINT_RESET) {
  770. /* two kind of reset :
  771. * - reset start -> pwr reg = 8
  772. * - reset end -> pwr reg = 0
  773. **/
  774. dprintk(DEBUG_NORMAL, "USB reset csr %x pwr %x\n",
  775. ep0csr, pwr_reg);
  776. dev->gadget.speed = USB_SPEED_UNKNOWN;
  777. udc_write(0x00, S3C2410_UDC_INDEX_REG);
  778. udc_write((dev->ep[0].ep.maxpacket & 0x7ff) >> 3,
  779. S3C2410_UDC_MAXP_REG);
  780. dev->address = 0;
  781. dev->ep0state = EP0_IDLE;
  782. dev->gadget.speed = USB_SPEED_FULL;
  783. /* clear interrupt */
  784. udc_write(S3C2410_UDC_USBINT_RESET,
  785. S3C2410_UDC_USB_INT_REG);
  786. udc_write(idx, S3C2410_UDC_INDEX_REG);
  787. spin_unlock_irqrestore(&dev->lock, flags);
  788. return IRQ_HANDLED;
  789. }
  790. /* RESUME */
  791. if (usb_status & S3C2410_UDC_USBINT_RESUME) {
  792. dprintk(DEBUG_NORMAL, "USB resume\n");
  793. /* clear interrupt */
  794. udc_write(S3C2410_UDC_USBINT_RESUME,
  795. S3C2410_UDC_USB_INT_REG);
  796. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  797. && dev->driver
  798. && dev->driver->resume)
  799. dev->driver->resume(&dev->gadget);
  800. }
  801. /* SUSPEND */
  802. if (usb_status & S3C2410_UDC_USBINT_SUSPEND) {
  803. dprintk(DEBUG_NORMAL, "USB suspend\n");
  804. /* clear interrupt */
  805. udc_write(S3C2410_UDC_USBINT_SUSPEND,
  806. S3C2410_UDC_USB_INT_REG);
  807. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  808. && dev->driver
  809. && dev->driver->suspend)
  810. dev->driver->suspend(&dev->gadget);
  811. dev->ep0state = EP0_IDLE;
  812. }
  813. /* EP */
  814. /* control traffic */
  815. /* check on ep0csr != 0 is not a good idea as clearing in_pkt_ready
  816. * generate an interrupt
  817. */
  818. if (usbd_status & S3C2410_UDC_INT_EP0) {
  819. dprintk(DEBUG_VERBOSE, "USB ep0 irq\n");
  820. /* Clear the interrupt bit by setting it to 1 */
  821. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_REG);
  822. s3c2410_udc_handle_ep0(dev);
  823. }
  824. /* endpoint data transfers */
  825. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  826. u32 tmp = 1 << i;
  827. if (usbd_status & tmp) {
  828. dprintk(DEBUG_VERBOSE, "USB ep%d irq\n", i);
  829. /* Clear the interrupt bit by setting it to 1 */
  830. udc_write(tmp, S3C2410_UDC_EP_INT_REG);
  831. s3c2410_udc_handle_ep(&dev->ep[i]);
  832. }
  833. }
  834. /* what else causes this interrupt? a receive! who is it? */
  835. if (!usb_status && !usbd_status && !pwr_reg && !ep0csr) {
  836. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  837. idx2 = udc_read(S3C2410_UDC_INDEX_REG);
  838. udc_write(i, S3C2410_UDC_INDEX_REG);
  839. if (udc_read(S3C2410_UDC_OUT_CSR1_REG) & 0x1)
  840. s3c2410_udc_handle_ep(&dev->ep[i]);
  841. /* restore index */
  842. udc_write(idx2, S3C2410_UDC_INDEX_REG);
  843. }
  844. }
  845. dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", IRQ_USBD);
  846. /* Restore old index */
  847. udc_write(idx, S3C2410_UDC_INDEX_REG);
  848. spin_unlock_irqrestore(&dev->lock, flags);
  849. return IRQ_HANDLED;
  850. }
  851. /*------------------------- s3c2410_ep_ops ----------------------------------*/
  852. static inline struct s3c2410_ep *to_s3c2410_ep(struct usb_ep *ep)
  853. {
  854. return container_of(ep, struct s3c2410_ep, ep);
  855. }
  856. static inline struct s3c2410_udc *to_s3c2410_udc(struct usb_gadget *gadget)
  857. {
  858. return container_of(gadget, struct s3c2410_udc, gadget);
  859. }
  860. static inline struct s3c2410_request *to_s3c2410_req(struct usb_request *req)
  861. {
  862. return container_of(req, struct s3c2410_request, req);
  863. }
  864. /*
  865. * s3c2410_udc_ep_enable
  866. */
  867. static int s3c2410_udc_ep_enable(struct usb_ep *_ep,
  868. const struct usb_endpoint_descriptor *desc)
  869. {
  870. struct s3c2410_udc *dev;
  871. struct s3c2410_ep *ep;
  872. u32 max, tmp;
  873. unsigned long flags;
  874. u32 csr1,csr2;
  875. u32 int_en_reg;
  876. ep = to_s3c2410_ep(_ep);
  877. if (!_ep || !desc || ep->desc
  878. || _ep->name == ep0name
  879. || desc->bDescriptorType != USB_DT_ENDPOINT)
  880. return -EINVAL;
  881. dev = ep->dev;
  882. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  883. return -ESHUTDOWN;
  884. max = usb_endpoint_maxp(desc) & 0x1fff;
  885. local_irq_save (flags);
  886. _ep->maxpacket = max & 0x7ff;
  887. ep->desc = desc;
  888. ep->halted = 0;
  889. ep->bEndpointAddress = desc->bEndpointAddress;
  890. /* set max packet */
  891. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  892. udc_write(max >> 3, S3C2410_UDC_MAXP_REG);
  893. /* set type, direction, address; reset fifo counters */
  894. if (desc->bEndpointAddress & USB_DIR_IN) {
  895. csr1 = S3C2410_UDC_ICSR1_FFLUSH|S3C2410_UDC_ICSR1_CLRDT;
  896. csr2 = S3C2410_UDC_ICSR2_MODEIN|S3C2410_UDC_ICSR2_DMAIEN;
  897. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  898. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  899. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  900. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  901. } else {
  902. /* don't flush in fifo or it will cause endpoint interrupt */
  903. csr1 = S3C2410_UDC_ICSR1_CLRDT;
  904. csr2 = S3C2410_UDC_ICSR2_DMAIEN;
  905. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  906. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  907. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  908. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  909. csr1 = S3C2410_UDC_OCSR1_FFLUSH | S3C2410_UDC_OCSR1_CLRDT;
  910. csr2 = S3C2410_UDC_OCSR2_DMAIEN;
  911. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  912. udc_write(csr1, S3C2410_UDC_OUT_CSR1_REG);
  913. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  914. udc_write(csr2, S3C2410_UDC_OUT_CSR2_REG);
  915. }
  916. /* enable irqs */
  917. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  918. udc_write(int_en_reg | (1 << ep->num), S3C2410_UDC_EP_INT_EN_REG);
  919. /* print some debug message */
  920. tmp = desc->bEndpointAddress;
  921. dprintk (DEBUG_NORMAL, "enable %s(%d) ep%x%s-blk max %02x\n",
  922. _ep->name,ep->num, tmp,
  923. desc->bEndpointAddress & USB_DIR_IN ? "in" : "out", max);
  924. local_irq_restore (flags);
  925. s3c2410_udc_set_halt(_ep, 0);
  926. return 0;
  927. }
  928. /*
  929. * s3c2410_udc_ep_disable
  930. */
  931. static int s3c2410_udc_ep_disable(struct usb_ep *_ep)
  932. {
  933. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  934. unsigned long flags;
  935. u32 int_en_reg;
  936. if (!_ep || !ep->desc) {
  937. dprintk(DEBUG_NORMAL, "%s not enabled\n",
  938. _ep ? ep->ep.name : NULL);
  939. return -EINVAL;
  940. }
  941. local_irq_save(flags);
  942. dprintk(DEBUG_NORMAL, "ep_disable: %s\n", _ep->name);
  943. ep->desc = NULL;
  944. ep->ep.desc = NULL;
  945. ep->halted = 1;
  946. s3c2410_udc_nuke (ep->dev, ep, -ESHUTDOWN);
  947. /* disable irqs */
  948. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  949. udc_write(int_en_reg & ~(1<<ep->num), S3C2410_UDC_EP_INT_EN_REG);
  950. local_irq_restore(flags);
  951. dprintk(DEBUG_NORMAL, "%s disabled\n", _ep->name);
  952. return 0;
  953. }
  954. /*
  955. * s3c2410_udc_alloc_request
  956. */
  957. static struct usb_request *
  958. s3c2410_udc_alloc_request(struct usb_ep *_ep, gfp_t mem_flags)
  959. {
  960. struct s3c2410_request *req;
  961. dprintk(DEBUG_VERBOSE,"%s(%pK,%d)\n", __func__, _ep, mem_flags);
  962. if (!_ep)
  963. return NULL;
  964. req = kzalloc (sizeof(struct s3c2410_request), mem_flags);
  965. if (!req)
  966. return NULL;
  967. INIT_LIST_HEAD (&req->queue);
  968. return &req->req;
  969. }
  970. /*
  971. * s3c2410_udc_free_request
  972. */
  973. static void
  974. s3c2410_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
  975. {
  976. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  977. struct s3c2410_request *req = to_s3c2410_req(_req);
  978. dprintk(DEBUG_VERBOSE, "%s(%pK,%pK)\n", __func__, _ep, _req);
  979. if (!ep || !_req || (!ep->desc && _ep->name != ep0name))
  980. return;
  981. WARN_ON (!list_empty (&req->queue));
  982. kfree(req);
  983. }
  984. /*
  985. * s3c2410_udc_queue
  986. */
  987. static int s3c2410_udc_queue(struct usb_ep *_ep, struct usb_request *_req,
  988. gfp_t gfp_flags)
  989. {
  990. struct s3c2410_request *req = to_s3c2410_req(_req);
  991. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  992. struct s3c2410_udc *dev;
  993. u32 ep_csr = 0;
  994. int fifo_count = 0;
  995. unsigned long flags;
  996. if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  997. dprintk(DEBUG_NORMAL, "%s: invalid args\n", __func__);
  998. return -EINVAL;
  999. }
  1000. dev = ep->dev;
  1001. if (unlikely (!dev->driver
  1002. || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
  1003. return -ESHUTDOWN;
  1004. }
  1005. local_irq_save (flags);
  1006. if (unlikely(!_req || !_req->complete
  1007. || !_req->buf || !list_empty(&req->queue))) {
  1008. if (!_req)
  1009. dprintk(DEBUG_NORMAL, "%s: 1 X X X\n", __func__);
  1010. else {
  1011. dprintk(DEBUG_NORMAL, "%s: 0 %01d %01d %01d\n",
  1012. __func__, !_req->complete,!_req->buf,
  1013. !list_empty(&req->queue));
  1014. }
  1015. local_irq_restore(flags);
  1016. return -EINVAL;
  1017. }
  1018. _req->status = -EINPROGRESS;
  1019. _req->actual = 0;
  1020. dprintk(DEBUG_VERBOSE, "%s: ep%x len %d\n",
  1021. __func__, ep->bEndpointAddress, _req->length);
  1022. if (ep->bEndpointAddress) {
  1023. udc_write(ep->bEndpointAddress & 0x7F, S3C2410_UDC_INDEX_REG);
  1024. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1025. ? S3C2410_UDC_IN_CSR1_REG
  1026. : S3C2410_UDC_OUT_CSR1_REG);
  1027. fifo_count = s3c2410_udc_fifo_count_out();
  1028. } else {
  1029. udc_write(0, S3C2410_UDC_INDEX_REG);
  1030. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  1031. fifo_count = s3c2410_udc_fifo_count_out();
  1032. }
  1033. /* kickstart this i/o queue? */
  1034. if (list_empty(&ep->queue) && !ep->halted) {
  1035. if (ep->bEndpointAddress == 0 /* ep0 */) {
  1036. switch (dev->ep0state) {
  1037. case EP0_IN_DATA_PHASE:
  1038. if (!(ep_csr&S3C2410_UDC_EP0_CSR_IPKRDY)
  1039. && s3c2410_udc_write_fifo(ep,
  1040. req)) {
  1041. dev->ep0state = EP0_IDLE;
  1042. req = NULL;
  1043. }
  1044. break;
  1045. case EP0_OUT_DATA_PHASE:
  1046. if ((!_req->length)
  1047. || ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1048. && s3c2410_udc_read_fifo(ep,
  1049. req))) {
  1050. dev->ep0state = EP0_IDLE;
  1051. req = NULL;
  1052. }
  1053. break;
  1054. default:
  1055. local_irq_restore(flags);
  1056. return -EL2HLT;
  1057. }
  1058. } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
  1059. && (!(ep_csr&S3C2410_UDC_OCSR1_PKTRDY))
  1060. && s3c2410_udc_write_fifo(ep, req)) {
  1061. req = NULL;
  1062. } else if ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1063. && fifo_count
  1064. && s3c2410_udc_read_fifo(ep, req)) {
  1065. req = NULL;
  1066. }
  1067. }
  1068. /* pio or dma irq handler advances the queue. */
  1069. if (likely (req != 0))
  1070. list_add_tail(&req->queue, &ep->queue);
  1071. local_irq_restore(flags);
  1072. dprintk(DEBUG_VERBOSE, "%s ok\n", __func__);
  1073. return 0;
  1074. }
  1075. /*
  1076. * s3c2410_udc_dequeue
  1077. */
  1078. static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1079. {
  1080. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1081. struct s3c2410_udc *udc;
  1082. int retval = -EINVAL;
  1083. unsigned long flags;
  1084. struct s3c2410_request *req = NULL;
  1085. dprintk(DEBUG_VERBOSE, "%s(%pK,%pK)\n", __func__, _ep, _req);
  1086. if (!the_controller->driver)
  1087. return -ESHUTDOWN;
  1088. if (!_ep || !_req)
  1089. return retval;
  1090. udc = to_s3c2410_udc(ep->gadget);
  1091. local_irq_save (flags);
  1092. list_for_each_entry (req, &ep->queue, queue) {
  1093. if (&req->req == _req) {
  1094. list_del_init (&req->queue);
  1095. _req->status = -ECONNRESET;
  1096. retval = 0;
  1097. break;
  1098. }
  1099. }
  1100. if (retval == 0) {
  1101. dprintk(DEBUG_VERBOSE,
  1102. "dequeued req %pK from %s, len %d buf %pK\n",
  1103. req, _ep->name, _req->length, _req->buf);
  1104. s3c2410_udc_done(ep, req, -ECONNRESET);
  1105. }
  1106. local_irq_restore (flags);
  1107. return retval;
  1108. }
  1109. /*
  1110. * s3c2410_udc_set_halt
  1111. */
  1112. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value)
  1113. {
  1114. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1115. u32 ep_csr = 0;
  1116. unsigned long flags;
  1117. u32 idx;
  1118. if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  1119. dprintk(DEBUG_NORMAL, "%s: inval 2\n", __func__);
  1120. return -EINVAL;
  1121. }
  1122. local_irq_save (flags);
  1123. idx = ep->bEndpointAddress & 0x7F;
  1124. if (idx == 0) {
  1125. s3c2410_udc_set_ep0_ss(base_addr);
  1126. s3c2410_udc_set_ep0_de_out(base_addr);
  1127. } else {
  1128. udc_write(idx, S3C2410_UDC_INDEX_REG);
  1129. ep_csr = udc_read((ep->bEndpointAddress &USB_DIR_IN)
  1130. ? S3C2410_UDC_IN_CSR1_REG
  1131. : S3C2410_UDC_OUT_CSR1_REG);
  1132. if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
  1133. if (value)
  1134. udc_write(ep_csr | S3C2410_UDC_ICSR1_SENDSTL,
  1135. S3C2410_UDC_IN_CSR1_REG);
  1136. else {
  1137. ep_csr &= ~S3C2410_UDC_ICSR1_SENDSTL;
  1138. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1139. ep_csr |= S3C2410_UDC_ICSR1_CLRDT;
  1140. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1141. }
  1142. } else {
  1143. if (value)
  1144. udc_write(ep_csr | S3C2410_UDC_OCSR1_SENDSTL,
  1145. S3C2410_UDC_OUT_CSR1_REG);
  1146. else {
  1147. ep_csr &= ~S3C2410_UDC_OCSR1_SENDSTL;
  1148. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1149. ep_csr |= S3C2410_UDC_OCSR1_CLRDT;
  1150. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1151. }
  1152. }
  1153. }
  1154. ep->halted = value ? 1 : 0;
  1155. local_irq_restore (flags);
  1156. return 0;
  1157. }
  1158. static const struct usb_ep_ops s3c2410_ep_ops = {
  1159. .enable = s3c2410_udc_ep_enable,
  1160. .disable = s3c2410_udc_ep_disable,
  1161. .alloc_request = s3c2410_udc_alloc_request,
  1162. .free_request = s3c2410_udc_free_request,
  1163. .queue = s3c2410_udc_queue,
  1164. .dequeue = s3c2410_udc_dequeue,
  1165. .set_halt = s3c2410_udc_set_halt,
  1166. };
  1167. /*------------------------- usb_gadget_ops ----------------------------------*/
  1168. /*
  1169. * s3c2410_udc_get_frame
  1170. */
  1171. static int s3c2410_udc_get_frame(struct usb_gadget *_gadget)
  1172. {
  1173. int tmp;
  1174. dprintk(DEBUG_VERBOSE, "%s()\n", __func__);
  1175. tmp = udc_read(S3C2410_UDC_FRAME_NUM2_REG) << 8;
  1176. tmp |= udc_read(S3C2410_UDC_FRAME_NUM1_REG);
  1177. return tmp;
  1178. }
  1179. /*
  1180. * s3c2410_udc_wakeup
  1181. */
  1182. static int s3c2410_udc_wakeup(struct usb_gadget *_gadget)
  1183. {
  1184. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1185. return 0;
  1186. }
  1187. /*
  1188. * s3c2410_udc_set_selfpowered
  1189. */
  1190. static int s3c2410_udc_set_selfpowered(struct usb_gadget *gadget, int value)
  1191. {
  1192. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1193. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1194. if (value)
  1195. udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
  1196. else
  1197. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1198. return 0;
  1199. }
  1200. static void s3c2410_udc_disable(struct s3c2410_udc *dev);
  1201. static void s3c2410_udc_enable(struct s3c2410_udc *dev);
  1202. static int s3c2410_udc_set_pullup(struct s3c2410_udc *udc, int is_on)
  1203. {
  1204. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1205. if (udc_info && (udc_info->udc_command ||
  1206. gpio_is_valid(udc_info->pullup_pin))) {
  1207. if (is_on)
  1208. s3c2410_udc_enable(udc);
  1209. else {
  1210. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1211. if (udc->driver && udc->driver->disconnect)
  1212. udc->driver->disconnect(&udc->gadget);
  1213. }
  1214. s3c2410_udc_disable(udc);
  1215. }
  1216. }
  1217. else
  1218. return -EOPNOTSUPP;
  1219. return 0;
  1220. }
  1221. static int s3c2410_udc_vbus_session(struct usb_gadget *gadget, int is_active)
  1222. {
  1223. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1224. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1225. udc->vbus = (is_active != 0);
  1226. s3c2410_udc_set_pullup(udc, is_active);
  1227. return 0;
  1228. }
  1229. static int s3c2410_udc_pullup(struct usb_gadget *gadget, int is_on)
  1230. {
  1231. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1232. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1233. s3c2410_udc_set_pullup(udc, is_on ? 0 : 1);
  1234. return 0;
  1235. }
  1236. static irqreturn_t s3c2410_udc_vbus_irq(int irq, void *_dev)
  1237. {
  1238. struct s3c2410_udc *dev = _dev;
  1239. unsigned int value;
  1240. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1241. value = gpio_get_value(udc_info->vbus_pin) ? 1 : 0;
  1242. if (udc_info->vbus_pin_inverted)
  1243. value = !value;
  1244. if (value != dev->vbus)
  1245. s3c2410_udc_vbus_session(&dev->gadget, value);
  1246. return IRQ_HANDLED;
  1247. }
  1248. static int s3c2410_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1249. {
  1250. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1251. if (udc_info && udc_info->vbus_draw) {
  1252. udc_info->vbus_draw(ma);
  1253. return 0;
  1254. }
  1255. return -ENOTSUPP;
  1256. }
  1257. static int s3c2410_udc_start(struct usb_gadget_driver *driver,
  1258. int (*bind)(struct usb_gadget *));
  1259. static int s3c2410_udc_stop(struct usb_gadget_driver *driver);
  1260. static const struct usb_gadget_ops s3c2410_ops = {
  1261. .get_frame = s3c2410_udc_get_frame,
  1262. .wakeup = s3c2410_udc_wakeup,
  1263. .set_selfpowered = s3c2410_udc_set_selfpowered,
  1264. .pullup = s3c2410_udc_pullup,
  1265. .vbus_session = s3c2410_udc_vbus_session,
  1266. .vbus_draw = s3c2410_vbus_draw,
  1267. .start = s3c2410_udc_start,
  1268. .stop = s3c2410_udc_stop,
  1269. };
  1270. static void s3c2410_udc_command(enum s3c2410_udc_cmd_e cmd)
  1271. {
  1272. if (!udc_info)
  1273. return;
  1274. if (udc_info->udc_command) {
  1275. udc_info->udc_command(cmd);
  1276. } else if (gpio_is_valid(udc_info->pullup_pin)) {
  1277. int value;
  1278. switch (cmd) {
  1279. case S3C2410_UDC_P_ENABLE:
  1280. value = 1;
  1281. break;
  1282. case S3C2410_UDC_P_DISABLE:
  1283. value = 0;
  1284. break;
  1285. default:
  1286. return;
  1287. }
  1288. value ^= udc_info->pullup_pin_inverted;
  1289. gpio_set_value(udc_info->pullup_pin, value);
  1290. }
  1291. }
  1292. /*------------------------- gadget driver handling---------------------------*/
  1293. /*
  1294. * s3c2410_udc_disable
  1295. */
  1296. static void s3c2410_udc_disable(struct s3c2410_udc *dev)
  1297. {
  1298. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1299. /* Disable all interrupts */
  1300. udc_write(0x00, S3C2410_UDC_USB_INT_EN_REG);
  1301. udc_write(0x00, S3C2410_UDC_EP_INT_EN_REG);
  1302. /* Clear the interrupt registers */
  1303. udc_write(S3C2410_UDC_USBINT_RESET
  1304. | S3C2410_UDC_USBINT_RESUME
  1305. | S3C2410_UDC_USBINT_SUSPEND,
  1306. S3C2410_UDC_USB_INT_REG);
  1307. udc_write(0x1F, S3C2410_UDC_EP_INT_REG);
  1308. /* Good bye, cruel world */
  1309. s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
  1310. /* Set speed to unknown */
  1311. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1312. }
  1313. /*
  1314. * s3c2410_udc_reinit
  1315. */
  1316. static void s3c2410_udc_reinit(struct s3c2410_udc *dev)
  1317. {
  1318. u32 i;
  1319. /* device/ep0 records init */
  1320. INIT_LIST_HEAD (&dev->gadget.ep_list);
  1321. INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
  1322. dev->ep0state = EP0_IDLE;
  1323. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1324. struct s3c2410_ep *ep = &dev->ep[i];
  1325. if (i != 0)
  1326. list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
  1327. ep->dev = dev;
  1328. ep->desc = NULL;
  1329. ep->ep.desc = NULL;
  1330. ep->halted = 0;
  1331. INIT_LIST_HEAD (&ep->queue);
  1332. }
  1333. }
  1334. /*
  1335. * s3c2410_udc_enable
  1336. */
  1337. static void s3c2410_udc_enable(struct s3c2410_udc *dev)
  1338. {
  1339. int i;
  1340. dprintk(DEBUG_NORMAL, "s3c2410_udc_enable called\n");
  1341. /* dev->gadget.speed = USB_SPEED_UNKNOWN; */
  1342. dev->gadget.speed = USB_SPEED_FULL;
  1343. /* Set MAXP for all endpoints */
  1344. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1345. udc_write(i, S3C2410_UDC_INDEX_REG);
  1346. udc_write((dev->ep[i].ep.maxpacket & 0x7ff) >> 3,
  1347. S3C2410_UDC_MAXP_REG);
  1348. }
  1349. /* Set default power state */
  1350. udc_write(DEFAULT_POWER_STATE, S3C2410_UDC_PWR_REG);
  1351. /* Enable reset and suspend interrupt interrupts */
  1352. udc_write(S3C2410_UDC_USBINT_RESET | S3C2410_UDC_USBINT_SUSPEND,
  1353. S3C2410_UDC_USB_INT_EN_REG);
  1354. /* Enable ep0 interrupt */
  1355. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG);
  1356. /* time to say "hello, world" */
  1357. s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
  1358. }
  1359. static int s3c2410_udc_start(struct usb_gadget_driver *driver,
  1360. int (*bind)(struct usb_gadget *))
  1361. {
  1362. struct s3c2410_udc *udc = the_controller;
  1363. int retval;
  1364. dprintk(DEBUG_NORMAL, "%s() '%s'\n", __func__, driver->driver.name);
  1365. /* Sanity checks */
  1366. if (!udc)
  1367. return -ENODEV;
  1368. if (udc->driver)
  1369. return -EBUSY;
  1370. if (!bind || !driver->setup || driver->max_speed < USB_SPEED_FULL) {
  1371. printk(KERN_ERR "Invalid driver: bind %pK setup %pK speed %d\n",
  1372. bind, driver->setup, driver->max_speed);
  1373. return -EINVAL;
  1374. }
  1375. #if defined(MODULE)
  1376. if (!driver->unbind) {
  1377. printk(KERN_ERR "Invalid driver: no unbind method\n");
  1378. return -EINVAL;
  1379. }
  1380. #endif
  1381. /* Hook the driver */
  1382. udc->driver = driver;
  1383. udc->gadget.dev.driver = &driver->driver;
  1384. /* Bind the driver */
  1385. if ((retval = device_add(&udc->gadget.dev)) != 0) {
  1386. printk(KERN_ERR "Error in device_add() : %d\n",retval);
  1387. goto register_error;
  1388. }
  1389. dprintk(DEBUG_NORMAL, "binding gadget driver '%s'\n",
  1390. driver->driver.name);
  1391. if ((retval = bind(&udc->gadget)) != 0) {
  1392. device_del(&udc->gadget.dev);
  1393. goto register_error;
  1394. }
  1395. /* Enable udc */
  1396. s3c2410_udc_enable(udc);
  1397. return 0;
  1398. register_error:
  1399. udc->driver = NULL;
  1400. udc->gadget.dev.driver = NULL;
  1401. return retval;
  1402. }
  1403. static int s3c2410_udc_stop(struct usb_gadget_driver *driver)
  1404. {
  1405. struct s3c2410_udc *udc = the_controller;
  1406. if (!udc)
  1407. return -ENODEV;
  1408. if (!driver || driver != udc->driver || !driver->unbind)
  1409. return -EINVAL;
  1410. dprintk(DEBUG_NORMAL, "usb_gadget_unregister_driver() '%s'\n",
  1411. driver->driver.name);
  1412. /* report disconnect */
  1413. if (driver->disconnect)
  1414. driver->disconnect(&udc->gadget);
  1415. driver->unbind(&udc->gadget);
  1416. device_del(&udc->gadget.dev);
  1417. udc->driver = NULL;
  1418. /* Disable udc */
  1419. s3c2410_udc_disable(udc);
  1420. return 0;
  1421. }
  1422. /*---------------------------------------------------------------------------*/
  1423. static struct s3c2410_udc memory = {
  1424. .gadget = {
  1425. .ops = &s3c2410_ops,
  1426. .ep0 = &memory.ep[0].ep,
  1427. .name = gadget_name,
  1428. .dev = {
  1429. .init_name = "gadget",
  1430. },
  1431. },
  1432. /* control endpoint */
  1433. .ep[0] = {
  1434. .num = 0,
  1435. .ep = {
  1436. .name = ep0name,
  1437. .ops = &s3c2410_ep_ops,
  1438. .maxpacket = EP0_FIFO_SIZE,
  1439. },
  1440. .dev = &memory,
  1441. },
  1442. /* first group of endpoints */
  1443. .ep[1] = {
  1444. .num = 1,
  1445. .ep = {
  1446. .name = "ep1-bulk",
  1447. .ops = &s3c2410_ep_ops,
  1448. .maxpacket = EP_FIFO_SIZE,
  1449. },
  1450. .dev = &memory,
  1451. .fifo_size = EP_FIFO_SIZE,
  1452. .bEndpointAddress = 1,
  1453. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1454. },
  1455. .ep[2] = {
  1456. .num = 2,
  1457. .ep = {
  1458. .name = "ep2-bulk",
  1459. .ops = &s3c2410_ep_ops,
  1460. .maxpacket = EP_FIFO_SIZE,
  1461. },
  1462. .dev = &memory,
  1463. .fifo_size = EP_FIFO_SIZE,
  1464. .bEndpointAddress = 2,
  1465. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1466. },
  1467. .ep[3] = {
  1468. .num = 3,
  1469. .ep = {
  1470. .name = "ep3-bulk",
  1471. .ops = &s3c2410_ep_ops,
  1472. .maxpacket = EP_FIFO_SIZE,
  1473. },
  1474. .dev = &memory,
  1475. .fifo_size = EP_FIFO_SIZE,
  1476. .bEndpointAddress = 3,
  1477. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1478. },
  1479. .ep[4] = {
  1480. .num = 4,
  1481. .ep = {
  1482. .name = "ep4-bulk",
  1483. .ops = &s3c2410_ep_ops,
  1484. .maxpacket = EP_FIFO_SIZE,
  1485. },
  1486. .dev = &memory,
  1487. .fifo_size = EP_FIFO_SIZE,
  1488. .bEndpointAddress = 4,
  1489. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1490. }
  1491. };
  1492. /*
  1493. * probe - binds to the platform device
  1494. */
  1495. static int s3c2410_udc_probe(struct platform_device *pdev)
  1496. {
  1497. struct s3c2410_udc *udc = &memory;
  1498. struct device *dev = &pdev->dev;
  1499. int retval;
  1500. int irq;
  1501. dev_dbg(dev, "%s()\n", __func__);
  1502. usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
  1503. if (IS_ERR(usb_bus_clock)) {
  1504. dev_err(dev, "failed to get usb bus clock source\n");
  1505. return PTR_ERR(usb_bus_clock);
  1506. }
  1507. clk_enable(usb_bus_clock);
  1508. udc_clock = clk_get(NULL, "usb-device");
  1509. if (IS_ERR(udc_clock)) {
  1510. dev_err(dev, "failed to get udc clock source\n");
  1511. return PTR_ERR(udc_clock);
  1512. }
  1513. clk_enable(udc_clock);
  1514. mdelay(10);
  1515. dev_dbg(dev, "got and enabled clocks\n");
  1516. if (strncmp(pdev->name, "s3c2440", 7) == 0) {
  1517. dev_info(dev, "S3C2440: increasing FIFO to 128 bytes\n");
  1518. memory.ep[1].fifo_size = S3C2440_EP_FIFO_SIZE;
  1519. memory.ep[2].fifo_size = S3C2440_EP_FIFO_SIZE;
  1520. memory.ep[3].fifo_size = S3C2440_EP_FIFO_SIZE;
  1521. memory.ep[4].fifo_size = S3C2440_EP_FIFO_SIZE;
  1522. }
  1523. spin_lock_init (&udc->lock);
  1524. udc_info = pdev->dev.platform_data;
  1525. rsrc_start = S3C2410_PA_USBDEV;
  1526. rsrc_len = S3C24XX_SZ_USBDEV;
  1527. if (!request_mem_region(rsrc_start, rsrc_len, gadget_name))
  1528. return -EBUSY;
  1529. base_addr = ioremap(rsrc_start, rsrc_len);
  1530. if (!base_addr) {
  1531. retval = -ENOMEM;
  1532. goto err_mem;
  1533. }
  1534. device_initialize(&udc->gadget.dev);
  1535. udc->gadget.dev.parent = &pdev->dev;
  1536. udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1537. the_controller = udc;
  1538. platform_set_drvdata(pdev, udc);
  1539. s3c2410_udc_disable(udc);
  1540. s3c2410_udc_reinit(udc);
  1541. /* irq setup after old hardware state is cleaned up */
  1542. retval = request_irq(IRQ_USBD, s3c2410_udc_irq,
  1543. 0, gadget_name, udc);
  1544. if (retval != 0) {
  1545. dev_err(dev, "cannot get irq %i, err %d\n", IRQ_USBD, retval);
  1546. retval = -EBUSY;
  1547. goto err_map;
  1548. }
  1549. dev_dbg(dev, "got irq %i\n", IRQ_USBD);
  1550. if (udc_info && udc_info->vbus_pin > 0) {
  1551. retval = gpio_request(udc_info->vbus_pin, "udc vbus");
  1552. if (retval < 0) {
  1553. dev_err(dev, "cannot claim vbus pin\n");
  1554. goto err_int;
  1555. }
  1556. irq = gpio_to_irq(udc_info->vbus_pin);
  1557. if (irq < 0) {
  1558. dev_err(dev, "no irq for gpio vbus pin\n");
  1559. goto err_gpio_claim;
  1560. }
  1561. retval = request_irq(irq, s3c2410_udc_vbus_irq,
  1562. IRQF_TRIGGER_RISING
  1563. | IRQF_TRIGGER_FALLING | IRQF_SHARED,
  1564. gadget_name, udc);
  1565. if (retval != 0) {
  1566. dev_err(dev, "can't get vbus irq %d, err %d\n",
  1567. irq, retval);
  1568. retval = -EBUSY;
  1569. goto err_gpio_claim;
  1570. }
  1571. dev_dbg(dev, "got irq %i\n", irq);
  1572. } else {
  1573. udc->vbus = 1;
  1574. }
  1575. if (udc_info && !udc_info->udc_command &&
  1576. gpio_is_valid(udc_info->pullup_pin)) {
  1577. retval = gpio_request_one(udc_info->pullup_pin,
  1578. udc_info->vbus_pin_inverted ?
  1579. GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
  1580. "udc pullup");
  1581. if (retval)
  1582. goto err_vbus_irq;
  1583. }
  1584. retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
  1585. if (retval)
  1586. goto err_add_udc;
  1587. if (s3c2410_udc_debugfs_root) {
  1588. udc->regs_info = debugfs_create_file("registers", S_IRUGO,
  1589. s3c2410_udc_debugfs_root,
  1590. udc, &s3c2410_udc_debugfs_fops);
  1591. if (!udc->regs_info)
  1592. dev_warn(dev, "debugfs file creation failed\n");
  1593. }
  1594. dev_dbg(dev, "probe ok\n");
  1595. return 0;
  1596. err_add_udc:
  1597. if (udc_info && !udc_info->udc_command &&
  1598. gpio_is_valid(udc_info->pullup_pin))
  1599. gpio_free(udc_info->pullup_pin);
  1600. err_vbus_irq:
  1601. if (udc_info && udc_info->vbus_pin > 0)
  1602. free_irq(gpio_to_irq(udc_info->vbus_pin), udc);
  1603. err_gpio_claim:
  1604. if (udc_info && udc_info->vbus_pin > 0)
  1605. gpio_free(udc_info->vbus_pin);
  1606. err_int:
  1607. free_irq(IRQ_USBD, udc);
  1608. err_map:
  1609. iounmap(base_addr);
  1610. err_mem:
  1611. release_mem_region(rsrc_start, rsrc_len);
  1612. return retval;
  1613. }
  1614. /*
  1615. * s3c2410_udc_remove
  1616. */
  1617. static int s3c2410_udc_remove(struct platform_device *pdev)
  1618. {
  1619. struct s3c2410_udc *udc = platform_get_drvdata(pdev);
  1620. unsigned int irq;
  1621. dev_dbg(&pdev->dev, "%s()\n", __func__);
  1622. usb_del_gadget_udc(&udc->gadget);
  1623. if (udc->driver)
  1624. return -EBUSY;
  1625. debugfs_remove(udc->regs_info);
  1626. if (udc_info && !udc_info->udc_command &&
  1627. gpio_is_valid(udc_info->pullup_pin))
  1628. gpio_free(udc_info->pullup_pin);
  1629. if (udc_info && udc_info->vbus_pin > 0) {
  1630. irq = gpio_to_irq(udc_info->vbus_pin);
  1631. free_irq(irq, udc);
  1632. }
  1633. free_irq(IRQ_USBD, udc);
  1634. iounmap(base_addr);
  1635. release_mem_region(rsrc_start, rsrc_len);
  1636. platform_set_drvdata(pdev, NULL);
  1637. if (!IS_ERR(udc_clock) && udc_clock != NULL) {
  1638. clk_disable(udc_clock);
  1639. clk_put(udc_clock);
  1640. udc_clock = NULL;
  1641. }
  1642. if (!IS_ERR(usb_bus_clock) && usb_bus_clock != NULL) {
  1643. clk_disable(usb_bus_clock);
  1644. clk_put(usb_bus_clock);
  1645. usb_bus_clock = NULL;
  1646. }
  1647. dev_dbg(&pdev->dev, "%s: remove ok\n", __func__);
  1648. return 0;
  1649. }
  1650. #ifdef CONFIG_PM
  1651. static int s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message)
  1652. {
  1653. s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
  1654. return 0;
  1655. }
  1656. static int s3c2410_udc_resume(struct platform_device *pdev)
  1657. {
  1658. s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
  1659. return 0;
  1660. }
  1661. #else
  1662. #define s3c2410_udc_suspend NULL
  1663. #define s3c2410_udc_resume NULL
  1664. #endif
  1665. static const struct platform_device_id s3c_udc_ids[] = {
  1666. { "s3c2410-usbgadget", },
  1667. { "s3c2440-usbgadget", },
  1668. { }
  1669. };
  1670. MODULE_DEVICE_TABLE(platform, s3c_udc_ids);
  1671. static struct platform_driver udc_driver_24x0 = {
  1672. .driver = {
  1673. .name = "s3c24x0-usbgadget",
  1674. .owner = THIS_MODULE,
  1675. },
  1676. .probe = s3c2410_udc_probe,
  1677. .remove = s3c2410_udc_remove,
  1678. .suspend = s3c2410_udc_suspend,
  1679. .resume = s3c2410_udc_resume,
  1680. .id_table = s3c_udc_ids,
  1681. };
  1682. static int __init udc_init(void)
  1683. {
  1684. int retval;
  1685. dprintk(DEBUG_NORMAL, "%s: version %s\n", gadget_name, DRIVER_VERSION);
  1686. s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name, NULL);
  1687. if (IS_ERR(s3c2410_udc_debugfs_root)) {
  1688. printk(KERN_ERR "%s: debugfs dir creation failed %ld\n",
  1689. gadget_name, PTR_ERR(s3c2410_udc_debugfs_root));
  1690. s3c2410_udc_debugfs_root = NULL;
  1691. }
  1692. retval = platform_driver_register(&udc_driver_24x0);
  1693. if (retval)
  1694. goto err;
  1695. return 0;
  1696. err:
  1697. debugfs_remove(s3c2410_udc_debugfs_root);
  1698. return retval;
  1699. }
  1700. static void __exit udc_exit(void)
  1701. {
  1702. platform_driver_unregister(&udc_driver_24x0);
  1703. debugfs_remove(s3c2410_udc_debugfs_root);
  1704. }
  1705. module_init(udc_init);
  1706. module_exit(udc_exit);
  1707. MODULE_AUTHOR(DRIVER_AUTHOR);
  1708. MODULE_DESCRIPTION(DRIVER_DESC);
  1709. MODULE_VERSION(DRIVER_VERSION);
  1710. MODULE_LICENSE("GPL");