langwell_udc.c 85 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435
  1. /*
  2. * Intel Langwell USB Device Controller driver
  3. * Copyright (C) 2008-2009, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. */
  9. /* #undef DEBUG */
  10. /* #undef VERBOSE_DEBUG */
  11. #include <linux/module.h>
  12. #include <linux/pci.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/kernel.h>
  15. #include <linux/delay.h>
  16. #include <linux/ioport.h>
  17. #include <linux/sched.h>
  18. #include <linux/slab.h>
  19. #include <linux/errno.h>
  20. #include <linux/init.h>
  21. #include <linux/timer.h>
  22. #include <linux/list.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/moduleparam.h>
  25. #include <linux/device.h>
  26. #include <linux/usb/ch9.h>
  27. #include <linux/usb/gadget.h>
  28. #include <linux/usb/otg.h>
  29. #include <linux/pm.h>
  30. #include <linux/io.h>
  31. #include <linux/irq.h>
  32. #include <asm/unaligned.h>
  33. #include "langwell_udc.h"
  34. #define DRIVER_DESC "Intel Langwell USB Device Controller driver"
  35. #define DRIVER_VERSION "16 May 2009"
  36. static const char driver_name[] = "langwell_udc";
  37. static const char driver_desc[] = DRIVER_DESC;
  38. /* for endpoint 0 operations */
  39. static const struct usb_endpoint_descriptor
  40. langwell_ep0_desc = {
  41. .bLength = USB_DT_ENDPOINT_SIZE,
  42. .bDescriptorType = USB_DT_ENDPOINT,
  43. .bEndpointAddress = 0,
  44. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  45. .wMaxPacketSize = EP0_MAX_PKT_SIZE,
  46. };
  47. /*-------------------------------------------------------------------------*/
  48. /* debugging */
  49. #ifdef VERBOSE_DEBUG
  50. static inline void print_all_registers(struct langwell_udc *dev)
  51. {
  52. int i;
  53. /* Capability Registers */
  54. dev_dbg(&dev->pdev->dev,
  55. "Capability Registers (offset: 0x%04x, length: 0x%08x)\n",
  56. CAP_REG_OFFSET, (u32)sizeof(struct langwell_cap_regs));
  57. dev_dbg(&dev->pdev->dev, "caplength=0x%02x\n",
  58. readb(&dev->cap_regs->caplength));
  59. dev_dbg(&dev->pdev->dev, "hciversion=0x%04x\n",
  60. readw(&dev->cap_regs->hciversion));
  61. dev_dbg(&dev->pdev->dev, "hcsparams=0x%08x\n",
  62. readl(&dev->cap_regs->hcsparams));
  63. dev_dbg(&dev->pdev->dev, "hccparams=0x%08x\n",
  64. readl(&dev->cap_regs->hccparams));
  65. dev_dbg(&dev->pdev->dev, "dciversion=0x%04x\n",
  66. readw(&dev->cap_regs->dciversion));
  67. dev_dbg(&dev->pdev->dev, "dccparams=0x%08x\n",
  68. readl(&dev->cap_regs->dccparams));
  69. /* Operational Registers */
  70. dev_dbg(&dev->pdev->dev,
  71. "Operational Registers (offset: 0x%04x, length: 0x%08x)\n",
  72. OP_REG_OFFSET, (u32)sizeof(struct langwell_op_regs));
  73. dev_dbg(&dev->pdev->dev, "extsts=0x%08x\n",
  74. readl(&dev->op_regs->extsts));
  75. dev_dbg(&dev->pdev->dev, "extintr=0x%08x\n",
  76. readl(&dev->op_regs->extintr));
  77. dev_dbg(&dev->pdev->dev, "usbcmd=0x%08x\n",
  78. readl(&dev->op_regs->usbcmd));
  79. dev_dbg(&dev->pdev->dev, "usbsts=0x%08x\n",
  80. readl(&dev->op_regs->usbsts));
  81. dev_dbg(&dev->pdev->dev, "usbintr=0x%08x\n",
  82. readl(&dev->op_regs->usbintr));
  83. dev_dbg(&dev->pdev->dev, "frindex=0x%08x\n",
  84. readl(&dev->op_regs->frindex));
  85. dev_dbg(&dev->pdev->dev, "ctrldssegment=0x%08x\n",
  86. readl(&dev->op_regs->ctrldssegment));
  87. dev_dbg(&dev->pdev->dev, "deviceaddr=0x%08x\n",
  88. readl(&dev->op_regs->deviceaddr));
  89. dev_dbg(&dev->pdev->dev, "endpointlistaddr=0x%08x\n",
  90. readl(&dev->op_regs->endpointlistaddr));
  91. dev_dbg(&dev->pdev->dev, "ttctrl=0x%08x\n",
  92. readl(&dev->op_regs->ttctrl));
  93. dev_dbg(&dev->pdev->dev, "burstsize=0x%08x\n",
  94. readl(&dev->op_regs->burstsize));
  95. dev_dbg(&dev->pdev->dev, "txfilltuning=0x%08x\n",
  96. readl(&dev->op_regs->txfilltuning));
  97. dev_dbg(&dev->pdev->dev, "txttfilltuning=0x%08x\n",
  98. readl(&dev->op_regs->txttfilltuning));
  99. dev_dbg(&dev->pdev->dev, "ic_usb=0x%08x\n",
  100. readl(&dev->op_regs->ic_usb));
  101. dev_dbg(&dev->pdev->dev, "ulpi_viewport=0x%08x\n",
  102. readl(&dev->op_regs->ulpi_viewport));
  103. dev_dbg(&dev->pdev->dev, "configflag=0x%08x\n",
  104. readl(&dev->op_regs->configflag));
  105. dev_dbg(&dev->pdev->dev, "portsc1=0x%08x\n",
  106. readl(&dev->op_regs->portsc1));
  107. dev_dbg(&dev->pdev->dev, "devlc=0x%08x\n",
  108. readl(&dev->op_regs->devlc));
  109. dev_dbg(&dev->pdev->dev, "otgsc=0x%08x\n",
  110. readl(&dev->op_regs->otgsc));
  111. dev_dbg(&dev->pdev->dev, "usbmode=0x%08x\n",
  112. readl(&dev->op_regs->usbmode));
  113. dev_dbg(&dev->pdev->dev, "endptnak=0x%08x\n",
  114. readl(&dev->op_regs->endptnak));
  115. dev_dbg(&dev->pdev->dev, "endptnaken=0x%08x\n",
  116. readl(&dev->op_regs->endptnaken));
  117. dev_dbg(&dev->pdev->dev, "endptsetupstat=0x%08x\n",
  118. readl(&dev->op_regs->endptsetupstat));
  119. dev_dbg(&dev->pdev->dev, "endptprime=0x%08x\n",
  120. readl(&dev->op_regs->endptprime));
  121. dev_dbg(&dev->pdev->dev, "endptflush=0x%08x\n",
  122. readl(&dev->op_regs->endptflush));
  123. dev_dbg(&dev->pdev->dev, "endptstat=0x%08x\n",
  124. readl(&dev->op_regs->endptstat));
  125. dev_dbg(&dev->pdev->dev, "endptcomplete=0x%08x\n",
  126. readl(&dev->op_regs->endptcomplete));
  127. for (i = 0; i < dev->ep_max / 2; i++) {
  128. dev_dbg(&dev->pdev->dev, "endptctrl[%d]=0x%08x\n",
  129. i, readl(&dev->op_regs->endptctrl[i]));
  130. }
  131. }
  132. #else
  133. #define print_all_registers(dev) do { } while (0)
  134. #endif /* VERBOSE_DEBUG */
  135. /*-------------------------------------------------------------------------*/
  136. #define is_in(ep) (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \
  137. USB_DIR_IN) : (usb_endpoint_dir_in((ep)->desc)))
  138. #define DIR_STRING(ep) (is_in(ep) ? "in" : "out")
  139. static char *type_string(const struct usb_endpoint_descriptor *desc)
  140. {
  141. switch (usb_endpoint_type(desc)) {
  142. case USB_ENDPOINT_XFER_BULK:
  143. return "bulk";
  144. case USB_ENDPOINT_XFER_ISOC:
  145. return "iso";
  146. case USB_ENDPOINT_XFER_INT:
  147. return "int";
  148. };
  149. return "control";
  150. }
  151. /* configure endpoint control registers */
  152. static void ep_reset(struct langwell_ep *ep, unsigned char ep_num,
  153. unsigned char is_in, unsigned char ep_type)
  154. {
  155. struct langwell_udc *dev;
  156. u32 endptctrl;
  157. dev = ep->dev;
  158. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  159. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  160. if (is_in) { /* TX */
  161. if (ep_num)
  162. endptctrl |= EPCTRL_TXR;
  163. endptctrl |= EPCTRL_TXE;
  164. endptctrl |= ep_type << EPCTRL_TXT_SHIFT;
  165. } else { /* RX */
  166. if (ep_num)
  167. endptctrl |= EPCTRL_RXR;
  168. endptctrl |= EPCTRL_RXE;
  169. endptctrl |= ep_type << EPCTRL_RXT_SHIFT;
  170. }
  171. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  172. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  173. }
  174. /* reset ep0 dQH and endptctrl */
  175. static void ep0_reset(struct langwell_udc *dev)
  176. {
  177. struct langwell_ep *ep;
  178. int i;
  179. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  180. /* ep0 in and out */
  181. for (i = 0; i < 2; i++) {
  182. ep = &dev->ep[i];
  183. ep->dev = dev;
  184. /* ep0 dQH */
  185. ep->dqh = &dev->ep_dqh[i];
  186. /* configure ep0 endpoint capabilities in dQH */
  187. ep->dqh->dqh_ios = 1;
  188. ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE;
  189. /* enable ep0-in HW zero length termination select */
  190. if (is_in(ep))
  191. ep->dqh->dqh_zlt = 0;
  192. ep->dqh->dqh_mult = 0;
  193. ep->dqh->dtd_next = DTD_TERM;
  194. /* configure ep0 control registers */
  195. ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL);
  196. }
  197. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  198. }
  199. /*-------------------------------------------------------------------------*/
  200. /* endpoints operations */
  201. /* configure endpoint, making it usable */
  202. static int langwell_ep_enable(struct usb_ep *_ep,
  203. const struct usb_endpoint_descriptor *desc)
  204. {
  205. struct langwell_udc *dev;
  206. struct langwell_ep *ep;
  207. u16 max = 0;
  208. unsigned long flags;
  209. int i, retval = 0;
  210. unsigned char zlt, ios = 0, mult = 0;
  211. ep = container_of(_ep, struct langwell_ep, ep);
  212. dev = ep->dev;
  213. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  214. if (!_ep || !desc || ep->desc
  215. || desc->bDescriptorType != USB_DT_ENDPOINT)
  216. return -EINVAL;
  217. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  218. return -ESHUTDOWN;
  219. max = usb_endpoint_maxp(desc);
  220. /*
  221. * disable HW zero length termination select
  222. * driver handles zero length packet through req->req.zero
  223. */
  224. zlt = 1;
  225. /*
  226. * sanity check type, direction, address, and then
  227. * initialize the endpoint capabilities fields in dQH
  228. */
  229. switch (usb_endpoint_type(desc)) {
  230. case USB_ENDPOINT_XFER_CONTROL:
  231. ios = 1;
  232. break;
  233. case USB_ENDPOINT_XFER_BULK:
  234. if ((dev->gadget.speed == USB_SPEED_HIGH
  235. && max != 512)
  236. || (dev->gadget.speed == USB_SPEED_FULL
  237. && max > 64)) {
  238. goto done;
  239. }
  240. break;
  241. case USB_ENDPOINT_XFER_INT:
  242. if (strstr(ep->ep.name, "-iso")) /* bulk is ok */
  243. goto done;
  244. switch (dev->gadget.speed) {
  245. case USB_SPEED_HIGH:
  246. if (max <= 1024)
  247. break;
  248. case USB_SPEED_FULL:
  249. if (max <= 64)
  250. break;
  251. default:
  252. if (max <= 8)
  253. break;
  254. goto done;
  255. }
  256. break;
  257. case USB_ENDPOINT_XFER_ISOC:
  258. if (strstr(ep->ep.name, "-bulk")
  259. || strstr(ep->ep.name, "-int"))
  260. goto done;
  261. switch (dev->gadget.speed) {
  262. case USB_SPEED_HIGH:
  263. if (max <= 1024)
  264. break;
  265. case USB_SPEED_FULL:
  266. if (max <= 1023)
  267. break;
  268. default:
  269. goto done;
  270. }
  271. /*
  272. * FIXME:
  273. * calculate transactions needed for high bandwidth iso
  274. */
  275. mult = (unsigned char)(1 + ((max >> 11) & 0x03));
  276. max = max & 0x8ff; /* bit 0~10 */
  277. /* 3 transactions at most */
  278. if (mult > 3)
  279. goto done;
  280. break;
  281. default:
  282. goto done;
  283. }
  284. spin_lock_irqsave(&dev->lock, flags);
  285. ep->ep.maxpacket = max;
  286. ep->desc = desc;
  287. ep->stopped = 0;
  288. ep->ep_num = usb_endpoint_num(desc);
  289. /* ep_type */
  290. ep->ep_type = usb_endpoint_type(desc);
  291. /* configure endpoint control registers */
  292. ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type);
  293. /* configure endpoint capabilities in dQH */
  294. i = ep->ep_num * 2 + is_in(ep);
  295. ep->dqh = &dev->ep_dqh[i];
  296. ep->dqh->dqh_ios = ios;
  297. ep->dqh->dqh_mpl = cpu_to_le16(max);
  298. ep->dqh->dqh_zlt = zlt;
  299. ep->dqh->dqh_mult = mult;
  300. ep->dqh->dtd_next = DTD_TERM;
  301. dev_dbg(&dev->pdev->dev, "enabled %s (ep%d%s-%s), max %04x\n",
  302. _ep->name,
  303. ep->ep_num,
  304. DIR_STRING(ep),
  305. type_string(desc),
  306. max);
  307. spin_unlock_irqrestore(&dev->lock, flags);
  308. done:
  309. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  310. return retval;
  311. }
  312. /*-------------------------------------------------------------------------*/
  313. /* retire a request */
  314. static void done(struct langwell_ep *ep, struct langwell_request *req,
  315. int status)
  316. {
  317. struct langwell_udc *dev = ep->dev;
  318. unsigned stopped = ep->stopped;
  319. struct langwell_dtd *curr_dtd, *next_dtd;
  320. int i;
  321. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  322. /* remove the req from ep->queue */
  323. list_del_init(&req->queue);
  324. if (req->req.status == -EINPROGRESS)
  325. req->req.status = status;
  326. else
  327. status = req->req.status;
  328. /* free dTD for the request */
  329. next_dtd = req->head;
  330. for (i = 0; i < req->dtd_count; i++) {
  331. curr_dtd = next_dtd;
  332. if (i != req->dtd_count - 1)
  333. next_dtd = curr_dtd->next_dtd_virt;
  334. dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma);
  335. }
  336. usb_gadget_unmap_request(&dev->gadget, &req->req, is_in(ep));
  337. if (status != -ESHUTDOWN)
  338. dev_dbg(&dev->pdev->dev,
  339. "complete %s, req %pK, stat %d, len %u/%u\n",
  340. ep->ep.name, &req->req, status,
  341. req->req.actual, req->req.length);
  342. /* don't modify queue heads during completion callback */
  343. ep->stopped = 1;
  344. spin_unlock(&dev->lock);
  345. /* complete routine from gadget driver */
  346. if (req->req.complete)
  347. req->req.complete(&ep->ep, &req->req);
  348. spin_lock(&dev->lock);
  349. ep->stopped = stopped;
  350. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  351. }
  352. static void langwell_ep_fifo_flush(struct usb_ep *_ep);
  353. /* delete all endpoint requests, called with spinlock held */
  354. static void nuke(struct langwell_ep *ep, int status)
  355. {
  356. /* called with spinlock held */
  357. ep->stopped = 1;
  358. /* endpoint fifo flush */
  359. if (&ep->ep && ep->desc)
  360. langwell_ep_fifo_flush(&ep->ep);
  361. while (!list_empty(&ep->queue)) {
  362. struct langwell_request *req = NULL;
  363. req = list_entry(ep->queue.next, struct langwell_request,
  364. queue);
  365. done(ep, req, status);
  366. }
  367. }
  368. /*-------------------------------------------------------------------------*/
  369. /* endpoint is no longer usable */
  370. static int langwell_ep_disable(struct usb_ep *_ep)
  371. {
  372. struct langwell_ep *ep;
  373. unsigned long flags;
  374. struct langwell_udc *dev;
  375. int ep_num;
  376. u32 endptctrl;
  377. ep = container_of(_ep, struct langwell_ep, ep);
  378. dev = ep->dev;
  379. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  380. if (!_ep || !ep->desc)
  381. return -EINVAL;
  382. spin_lock_irqsave(&dev->lock, flags);
  383. /* disable endpoint control register */
  384. ep_num = ep->ep_num;
  385. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  386. if (is_in(ep))
  387. endptctrl &= ~EPCTRL_TXE;
  388. else
  389. endptctrl &= ~EPCTRL_RXE;
  390. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  391. /* nuke all pending requests (does flush) */
  392. nuke(ep, -ESHUTDOWN);
  393. ep->desc = NULL;
  394. ep->ep.desc = NULL;
  395. ep->stopped = 1;
  396. spin_unlock_irqrestore(&dev->lock, flags);
  397. dev_dbg(&dev->pdev->dev, "disabled %s\n", _ep->name);
  398. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  399. return 0;
  400. }
  401. /* allocate a request object to use with this endpoint */
  402. static struct usb_request *langwell_alloc_request(struct usb_ep *_ep,
  403. gfp_t gfp_flags)
  404. {
  405. struct langwell_ep *ep;
  406. struct langwell_udc *dev;
  407. struct langwell_request *req = NULL;
  408. if (!_ep)
  409. return NULL;
  410. ep = container_of(_ep, struct langwell_ep, ep);
  411. dev = ep->dev;
  412. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  413. req = kzalloc(sizeof(*req), gfp_flags);
  414. if (!req)
  415. return NULL;
  416. req->req.dma = DMA_ADDR_INVALID;
  417. INIT_LIST_HEAD(&req->queue);
  418. dev_vdbg(&dev->pdev->dev, "alloc request for %s\n", _ep->name);
  419. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  420. return &req->req;
  421. }
  422. /* free a request object */
  423. static void langwell_free_request(struct usb_ep *_ep,
  424. struct usb_request *_req)
  425. {
  426. struct langwell_ep *ep;
  427. struct langwell_udc *dev;
  428. struct langwell_request *req = NULL;
  429. ep = container_of(_ep, struct langwell_ep, ep);
  430. dev = ep->dev;
  431. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  432. if (!_ep || !_req)
  433. return;
  434. req = container_of(_req, struct langwell_request, req);
  435. WARN_ON(!list_empty(&req->queue));
  436. if (_req)
  437. kfree(req);
  438. dev_vdbg(&dev->pdev->dev, "free request for %s\n", _ep->name);
  439. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  440. }
  441. /*-------------------------------------------------------------------------*/
  442. /* queue dTD and PRIME endpoint */
  443. static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req)
  444. {
  445. u32 bit_mask, usbcmd, endptstat, dtd_dma;
  446. u8 dtd_status;
  447. int i;
  448. struct langwell_dqh *dqh;
  449. struct langwell_udc *dev;
  450. dev = ep->dev;
  451. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  452. i = ep->ep_num * 2 + is_in(ep);
  453. dqh = &dev->ep_dqh[i];
  454. if (ep->ep_num)
  455. dev_vdbg(&dev->pdev->dev, "%s\n", ep->name);
  456. else
  457. /* ep0 */
  458. dev_vdbg(&dev->pdev->dev, "%s-%s\n", ep->name, DIR_STRING(ep));
  459. dev_vdbg(&dev->pdev->dev, "ep_dqh[%d] addr: 0x%pK\n",
  460. i, &(dev->ep_dqh[i]));
  461. bit_mask = is_in(ep) ?
  462. (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num));
  463. dev_vdbg(&dev->pdev->dev, "bit_mask = 0x%08x\n", bit_mask);
  464. /* check if the pipe is empty */
  465. if (!(list_empty(&ep->queue))) {
  466. /* add dTD to the end of linked list */
  467. struct langwell_request *lastreq;
  468. lastreq = list_entry(ep->queue.prev,
  469. struct langwell_request, queue);
  470. lastreq->tail->dtd_next =
  471. cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK);
  472. /* read prime bit, if 1 goto out */
  473. if (readl(&dev->op_regs->endptprime) & bit_mask)
  474. goto out;
  475. do {
  476. /* set ATDTW bit in USBCMD */
  477. usbcmd = readl(&dev->op_regs->usbcmd);
  478. writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd);
  479. /* read correct status bit */
  480. endptstat = readl(&dev->op_regs->endptstat) & bit_mask;
  481. } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW));
  482. /* write ATDTW bit to 0 */
  483. usbcmd = readl(&dev->op_regs->usbcmd);
  484. writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd);
  485. if (endptstat)
  486. goto out;
  487. }
  488. /* write dQH next pointer and terminate bit to 0 */
  489. dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK;
  490. dqh->dtd_next = cpu_to_le32(dtd_dma);
  491. /* clear active and halt bit */
  492. dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED);
  493. dqh->dtd_status &= dtd_status;
  494. dev_vdbg(&dev->pdev->dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status);
  495. /* ensure that updates to the dQH will occur before priming */
  496. wmb();
  497. /* write 1 to endptprime register to PRIME endpoint */
  498. bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num);
  499. dev_vdbg(&dev->pdev->dev, "endprime bit_mask = 0x%08x\n", bit_mask);
  500. writel(bit_mask, &dev->op_regs->endptprime);
  501. out:
  502. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  503. return 0;
  504. }
  505. /* fill in the dTD structure to build a transfer descriptor */
  506. static struct langwell_dtd *build_dtd(struct langwell_request *req,
  507. unsigned *length, dma_addr_t *dma, int *is_last)
  508. {
  509. u32 buf_ptr;
  510. struct langwell_dtd *dtd;
  511. struct langwell_udc *dev;
  512. int i;
  513. dev = req->ep->dev;
  514. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  515. /* the maximum transfer length, up to 16k bytes */
  516. *length = min(req->req.length - req->req.actual,
  517. (unsigned)DTD_MAX_TRANSFER_LENGTH);
  518. /* create dTD dma_pool resource */
  519. dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma);
  520. if (dtd == NULL)
  521. return dtd;
  522. dtd->dtd_dma = *dma;
  523. /* initialize buffer page pointers */
  524. buf_ptr = (u32)(req->req.dma + req->req.actual);
  525. for (i = 0; i < 5; i++)
  526. dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE);
  527. req->req.actual += *length;
  528. /* fill in total bytes with transfer size */
  529. dtd->dtd_total = cpu_to_le16(*length);
  530. dev_vdbg(&dev->pdev->dev, "dtd->dtd_total = %d\n", dtd->dtd_total);
  531. /* set is_last flag if req->req.zero is set or not */
  532. if (req->req.zero) {
  533. if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
  534. *is_last = 1;
  535. else
  536. *is_last = 0;
  537. } else if (req->req.length == req->req.actual) {
  538. *is_last = 1;
  539. } else
  540. *is_last = 0;
  541. if (*is_last == 0)
  542. dev_vdbg(&dev->pdev->dev, "multi-dtd request!\n");
  543. /* set interrupt on complete bit for the last dTD */
  544. if (*is_last && !req->req.no_interrupt)
  545. dtd->dtd_ioc = 1;
  546. /* set multiplier override 0 for non-ISO and non-TX endpoint */
  547. dtd->dtd_multo = 0;
  548. /* set the active bit of status field to 1 */
  549. dtd->dtd_status = DTD_STS_ACTIVE;
  550. dev_vdbg(&dev->pdev->dev, "dtd->dtd_status = 0x%02x\n",
  551. dtd->dtd_status);
  552. dev_vdbg(&dev->pdev->dev, "length = %d, dma addr= 0x%08x\n",
  553. *length, (int)*dma);
  554. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  555. return dtd;
  556. }
  557. /* generate dTD linked list for a request */
  558. static int req_to_dtd(struct langwell_request *req)
  559. {
  560. unsigned count;
  561. int is_last, is_first = 1;
  562. struct langwell_dtd *dtd, *last_dtd = NULL;
  563. struct langwell_udc *dev;
  564. dma_addr_t dma;
  565. dev = req->ep->dev;
  566. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  567. do {
  568. dtd = build_dtd(req, &count, &dma, &is_last);
  569. if (dtd == NULL)
  570. return -ENOMEM;
  571. if (is_first) {
  572. is_first = 0;
  573. req->head = dtd;
  574. } else {
  575. last_dtd->dtd_next = cpu_to_le32(dma);
  576. last_dtd->next_dtd_virt = dtd;
  577. }
  578. last_dtd = dtd;
  579. req->dtd_count++;
  580. } while (!is_last);
  581. /* set terminate bit to 1 for the last dTD */
  582. dtd->dtd_next = DTD_TERM;
  583. req->tail = dtd;
  584. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  585. return 0;
  586. }
  587. /*-------------------------------------------------------------------------*/
  588. /* queue (submits) an I/O requests to an endpoint */
  589. static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
  590. gfp_t gfp_flags)
  591. {
  592. struct langwell_request *req;
  593. struct langwell_ep *ep;
  594. struct langwell_udc *dev;
  595. unsigned long flags;
  596. int is_iso = 0;
  597. int ret;
  598. /* always require a cpu-view buffer */
  599. req = container_of(_req, struct langwell_request, req);
  600. ep = container_of(_ep, struct langwell_ep, ep);
  601. if (!_req || !_req->complete || !_req->buf
  602. || !list_empty(&req->queue)) {
  603. return -EINVAL;
  604. }
  605. if (unlikely(!_ep || !ep->desc))
  606. return -EINVAL;
  607. dev = ep->dev;
  608. req->ep = ep;
  609. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  610. if (usb_endpoint_xfer_isoc(ep->desc)) {
  611. if (req->req.length > ep->ep.maxpacket)
  612. return -EMSGSIZE;
  613. is_iso = 1;
  614. }
  615. if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN))
  616. return -ESHUTDOWN;
  617. /* set up dma mapping */
  618. ret = usb_gadget_map_request(&dev->gadget, &req->req, is_in(ep));
  619. if (ret)
  620. return ret;
  621. dev_dbg(&dev->pdev->dev,
  622. "%s queue req %pK, len %u, buf %pK, dma 0x%08x\n",
  623. _ep->name,
  624. _req, _req->length, _req->buf, (int)_req->dma);
  625. _req->status = -EINPROGRESS;
  626. _req->actual = 0;
  627. req->dtd_count = 0;
  628. spin_lock_irqsave(&dev->lock, flags);
  629. /* build and put dTDs to endpoint queue */
  630. if (!req_to_dtd(req)) {
  631. queue_dtd(ep, req);
  632. } else {
  633. spin_unlock_irqrestore(&dev->lock, flags);
  634. return -ENOMEM;
  635. }
  636. /* update ep0 state */
  637. if (ep->ep_num == 0)
  638. dev->ep0_state = DATA_STATE_XMIT;
  639. if (likely(req != NULL)) {
  640. list_add_tail(&req->queue, &ep->queue);
  641. dev_vdbg(&dev->pdev->dev, "list_add_tail()\n");
  642. }
  643. spin_unlock_irqrestore(&dev->lock, flags);
  644. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  645. return 0;
  646. }
  647. /* dequeue (cancels, unlinks) an I/O request from an endpoint */
  648. static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  649. {
  650. struct langwell_ep *ep;
  651. struct langwell_udc *dev;
  652. struct langwell_request *req;
  653. unsigned long flags;
  654. int stopped, ep_num, retval = 0;
  655. u32 endptctrl;
  656. ep = container_of(_ep, struct langwell_ep, ep);
  657. dev = ep->dev;
  658. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  659. if (!_ep || !ep->desc || !_req)
  660. return -EINVAL;
  661. if (!dev->driver)
  662. return -ESHUTDOWN;
  663. spin_lock_irqsave(&dev->lock, flags);
  664. stopped = ep->stopped;
  665. /* quiesce dma while we patch the queue */
  666. ep->stopped = 1;
  667. ep_num = ep->ep_num;
  668. /* disable endpoint control register */
  669. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  670. if (is_in(ep))
  671. endptctrl &= ~EPCTRL_TXE;
  672. else
  673. endptctrl &= ~EPCTRL_RXE;
  674. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  675. /* make sure it's still queued on this endpoint */
  676. list_for_each_entry(req, &ep->queue, queue) {
  677. if (&req->req == _req)
  678. break;
  679. }
  680. if (&req->req != _req) {
  681. retval = -EINVAL;
  682. goto done;
  683. }
  684. /* queue head may be partially complete. */
  685. if (ep->queue.next == &req->queue) {
  686. dev_dbg(&dev->pdev->dev, "unlink (%s) dma\n", _ep->name);
  687. _req->status = -ECONNRESET;
  688. langwell_ep_fifo_flush(&ep->ep);
  689. /* not the last request in endpoint queue */
  690. if (likely(ep->queue.next == &req->queue)) {
  691. struct langwell_dqh *dqh;
  692. struct langwell_request *next_req;
  693. dqh = ep->dqh;
  694. next_req = list_entry(req->queue.next,
  695. struct langwell_request, queue);
  696. /* point the dQH to the first dTD of next request */
  697. writel((u32) next_req->head, &dqh->dqh_current);
  698. }
  699. } else {
  700. struct langwell_request *prev_req;
  701. prev_req = list_entry(req->queue.prev,
  702. struct langwell_request, queue);
  703. writel(readl(&req->tail->dtd_next),
  704. &prev_req->tail->dtd_next);
  705. }
  706. done(ep, req, -ECONNRESET);
  707. done:
  708. /* enable endpoint again */
  709. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  710. if (is_in(ep))
  711. endptctrl |= EPCTRL_TXE;
  712. else
  713. endptctrl |= EPCTRL_RXE;
  714. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  715. ep->stopped = stopped;
  716. spin_unlock_irqrestore(&dev->lock, flags);
  717. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  718. return retval;
  719. }
  720. /*-------------------------------------------------------------------------*/
  721. /* endpoint set/clear halt */
  722. static void ep_set_halt(struct langwell_ep *ep, int value)
  723. {
  724. u32 endptctrl = 0;
  725. int ep_num;
  726. struct langwell_udc *dev = ep->dev;
  727. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  728. ep_num = ep->ep_num;
  729. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  730. /* value: 1 - set halt, 0 - clear halt */
  731. if (value) {
  732. /* set the stall bit */
  733. if (is_in(ep))
  734. endptctrl |= EPCTRL_TXS;
  735. else
  736. endptctrl |= EPCTRL_RXS;
  737. } else {
  738. /* clear the stall bit and reset data toggle */
  739. if (is_in(ep)) {
  740. endptctrl &= ~EPCTRL_TXS;
  741. endptctrl |= EPCTRL_TXR;
  742. } else {
  743. endptctrl &= ~EPCTRL_RXS;
  744. endptctrl |= EPCTRL_RXR;
  745. }
  746. }
  747. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  748. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  749. }
  750. /* set the endpoint halt feature */
  751. static int langwell_ep_set_halt(struct usb_ep *_ep, int value)
  752. {
  753. struct langwell_ep *ep;
  754. struct langwell_udc *dev;
  755. unsigned long flags;
  756. int retval = 0;
  757. ep = container_of(_ep, struct langwell_ep, ep);
  758. dev = ep->dev;
  759. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  760. if (!_ep || !ep->desc)
  761. return -EINVAL;
  762. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  763. return -ESHUTDOWN;
  764. if (usb_endpoint_xfer_isoc(ep->desc))
  765. return -EOPNOTSUPP;
  766. spin_lock_irqsave(&dev->lock, flags);
  767. /*
  768. * attempt to halt IN ep will fail if any transfer requests
  769. * are still queue
  770. */
  771. if (!list_empty(&ep->queue) && is_in(ep) && value) {
  772. /* IN endpoint FIFO holds bytes */
  773. dev_dbg(&dev->pdev->dev, "%s FIFO holds bytes\n", _ep->name);
  774. retval = -EAGAIN;
  775. goto done;
  776. }
  777. /* endpoint set/clear halt */
  778. if (ep->ep_num) {
  779. ep_set_halt(ep, value);
  780. } else { /* endpoint 0 */
  781. dev->ep0_state = WAIT_FOR_SETUP;
  782. dev->ep0_dir = USB_DIR_OUT;
  783. }
  784. done:
  785. spin_unlock_irqrestore(&dev->lock, flags);
  786. dev_dbg(&dev->pdev->dev, "%s %s halt\n",
  787. _ep->name, value ? "set" : "clear");
  788. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  789. return retval;
  790. }
  791. /* set the halt feature and ignores clear requests */
  792. static int langwell_ep_set_wedge(struct usb_ep *_ep)
  793. {
  794. struct langwell_ep *ep;
  795. struct langwell_udc *dev;
  796. ep = container_of(_ep, struct langwell_ep, ep);
  797. dev = ep->dev;
  798. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  799. if (!_ep || !ep->desc)
  800. return -EINVAL;
  801. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  802. return usb_ep_set_halt(_ep);
  803. }
  804. /* flush contents of a fifo */
  805. static void langwell_ep_fifo_flush(struct usb_ep *_ep)
  806. {
  807. struct langwell_ep *ep;
  808. struct langwell_udc *dev;
  809. u32 flush_bit;
  810. unsigned long timeout;
  811. ep = container_of(_ep, struct langwell_ep, ep);
  812. dev = ep->dev;
  813. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  814. if (!_ep || !ep->desc) {
  815. dev_vdbg(&dev->pdev->dev, "ep or ep->desc is NULL\n");
  816. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  817. return;
  818. }
  819. dev_vdbg(&dev->pdev->dev, "%s-%s fifo flush\n",
  820. _ep->name, DIR_STRING(ep));
  821. /* flush endpoint buffer */
  822. if (ep->ep_num == 0)
  823. flush_bit = (1 << 16) | 1;
  824. else if (is_in(ep))
  825. flush_bit = 1 << (ep->ep_num + 16); /* TX */
  826. else
  827. flush_bit = 1 << ep->ep_num; /* RX */
  828. /* wait until flush complete */
  829. timeout = jiffies + FLUSH_TIMEOUT;
  830. do {
  831. writel(flush_bit, &dev->op_regs->endptflush);
  832. while (readl(&dev->op_regs->endptflush)) {
  833. if (time_after(jiffies, timeout)) {
  834. dev_err(&dev->pdev->dev, "ep flush timeout\n");
  835. goto done;
  836. }
  837. cpu_relax();
  838. }
  839. } while (readl(&dev->op_regs->endptstat) & flush_bit);
  840. done:
  841. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  842. }
  843. /* endpoints operations structure */
  844. static const struct usb_ep_ops langwell_ep_ops = {
  845. /* configure endpoint, making it usable */
  846. .enable = langwell_ep_enable,
  847. /* endpoint is no longer usable */
  848. .disable = langwell_ep_disable,
  849. /* allocate a request object to use with this endpoint */
  850. .alloc_request = langwell_alloc_request,
  851. /* free a request object */
  852. .free_request = langwell_free_request,
  853. /* queue (submits) an I/O requests to an endpoint */
  854. .queue = langwell_ep_queue,
  855. /* dequeue (cancels, unlinks) an I/O request from an endpoint */
  856. .dequeue = langwell_ep_dequeue,
  857. /* set the endpoint halt feature */
  858. .set_halt = langwell_ep_set_halt,
  859. /* set the halt feature and ignores clear requests */
  860. .set_wedge = langwell_ep_set_wedge,
  861. /* flush contents of a fifo */
  862. .fifo_flush = langwell_ep_fifo_flush,
  863. };
  864. /*-------------------------------------------------------------------------*/
  865. /* device controller usb_gadget_ops structure */
  866. /* returns the current frame number */
  867. static int langwell_get_frame(struct usb_gadget *_gadget)
  868. {
  869. struct langwell_udc *dev;
  870. u16 retval;
  871. if (!_gadget)
  872. return -ENODEV;
  873. dev = container_of(_gadget, struct langwell_udc, gadget);
  874. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  875. retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK;
  876. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  877. return retval;
  878. }
  879. /* enter or exit PHY low power state */
  880. static void langwell_phy_low_power(struct langwell_udc *dev, bool flag)
  881. {
  882. u32 devlc;
  883. u8 devlc_byte2;
  884. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  885. devlc = readl(&dev->op_regs->devlc);
  886. dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
  887. if (flag)
  888. devlc |= LPM_PHCD;
  889. else
  890. devlc &= ~LPM_PHCD;
  891. /* FIXME: workaround for Langwell A1/A2/A3 sighting */
  892. devlc_byte2 = (devlc >> 16) & 0xff;
  893. writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
  894. devlc = readl(&dev->op_regs->devlc);
  895. dev_vdbg(&dev->pdev->dev,
  896. "%s PHY low power suspend, devlc = 0x%08x\n",
  897. flag ? "enter" : "exit", devlc);
  898. }
  899. /* tries to wake up the host connected to this gadget */
  900. static int langwell_wakeup(struct usb_gadget *_gadget)
  901. {
  902. struct langwell_udc *dev;
  903. u32 portsc1;
  904. unsigned long flags;
  905. if (!_gadget)
  906. return 0;
  907. dev = container_of(_gadget, struct langwell_udc, gadget);
  908. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  909. /* remote wakeup feature not enabled by host */
  910. if (!dev->remote_wakeup) {
  911. dev_info(&dev->pdev->dev, "remote wakeup is disabled\n");
  912. return -ENOTSUPP;
  913. }
  914. spin_lock_irqsave(&dev->lock, flags);
  915. portsc1 = readl(&dev->op_regs->portsc1);
  916. if (!(portsc1 & PORTS_SUSP)) {
  917. spin_unlock_irqrestore(&dev->lock, flags);
  918. return 0;
  919. }
  920. /* LPM L1 to L0 or legacy remote wakeup */
  921. if (dev->lpm && dev->lpm_state == LPM_L1)
  922. dev_info(&dev->pdev->dev, "LPM L1 to L0 remote wakeup\n");
  923. else
  924. dev_info(&dev->pdev->dev, "device remote wakeup\n");
  925. /* exit PHY low power suspend */
  926. if (dev->pdev->device != 0x0829)
  927. langwell_phy_low_power(dev, 0);
  928. /* force port resume */
  929. portsc1 |= PORTS_FPR;
  930. writel(portsc1, &dev->op_regs->portsc1);
  931. spin_unlock_irqrestore(&dev->lock, flags);
  932. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  933. return 0;
  934. }
  935. /* notify controller that VBUS is powered or not */
  936. static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active)
  937. {
  938. struct langwell_udc *dev;
  939. unsigned long flags;
  940. u32 usbcmd;
  941. if (!_gadget)
  942. return -ENODEV;
  943. dev = container_of(_gadget, struct langwell_udc, gadget);
  944. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  945. spin_lock_irqsave(&dev->lock, flags);
  946. dev_vdbg(&dev->pdev->dev, "VBUS status: %s\n",
  947. is_active ? "on" : "off");
  948. dev->vbus_active = (is_active != 0);
  949. if (dev->driver && dev->softconnected && dev->vbus_active) {
  950. usbcmd = readl(&dev->op_regs->usbcmd);
  951. usbcmd |= CMD_RUNSTOP;
  952. writel(usbcmd, &dev->op_regs->usbcmd);
  953. } else {
  954. usbcmd = readl(&dev->op_regs->usbcmd);
  955. usbcmd &= ~CMD_RUNSTOP;
  956. writel(usbcmd, &dev->op_regs->usbcmd);
  957. }
  958. spin_unlock_irqrestore(&dev->lock, flags);
  959. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  960. return 0;
  961. }
  962. /* constrain controller's VBUS power usage */
  963. static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  964. {
  965. struct langwell_udc *dev;
  966. if (!_gadget)
  967. return -ENODEV;
  968. dev = container_of(_gadget, struct langwell_udc, gadget);
  969. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  970. if (dev->transceiver) {
  971. dev_vdbg(&dev->pdev->dev, "usb_phy_set_power\n");
  972. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  973. return usb_phy_set_power(dev->transceiver, mA);
  974. }
  975. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  976. return -ENOTSUPP;
  977. }
  978. /* D+ pullup, software-controlled connect/disconnect to USB host */
  979. static int langwell_pullup(struct usb_gadget *_gadget, int is_on)
  980. {
  981. struct langwell_udc *dev;
  982. u32 usbcmd;
  983. unsigned long flags;
  984. if (!_gadget)
  985. return -ENODEV;
  986. dev = container_of(_gadget, struct langwell_udc, gadget);
  987. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  988. spin_lock_irqsave(&dev->lock, flags);
  989. dev->softconnected = (is_on != 0);
  990. if (dev->driver && dev->softconnected && dev->vbus_active) {
  991. usbcmd = readl(&dev->op_regs->usbcmd);
  992. usbcmd |= CMD_RUNSTOP;
  993. writel(usbcmd, &dev->op_regs->usbcmd);
  994. } else {
  995. usbcmd = readl(&dev->op_regs->usbcmd);
  996. usbcmd &= ~CMD_RUNSTOP;
  997. writel(usbcmd, &dev->op_regs->usbcmd);
  998. }
  999. spin_unlock_irqrestore(&dev->lock, flags);
  1000. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1001. return 0;
  1002. }
  1003. static int langwell_start(struct usb_gadget *g,
  1004. struct usb_gadget_driver *driver);
  1005. static int langwell_stop(struct usb_gadget *g,
  1006. struct usb_gadget_driver *driver);
  1007. /* device controller usb_gadget_ops structure */
  1008. static const struct usb_gadget_ops langwell_ops = {
  1009. /* returns the current frame number */
  1010. .get_frame = langwell_get_frame,
  1011. /* tries to wake up the host connected to this gadget */
  1012. .wakeup = langwell_wakeup,
  1013. /* set the device selfpowered feature, always selfpowered */
  1014. /* .set_selfpowered = langwell_set_selfpowered, */
  1015. /* notify controller that VBUS is powered or not */
  1016. .vbus_session = langwell_vbus_session,
  1017. /* constrain controller's VBUS power usage */
  1018. .vbus_draw = langwell_vbus_draw,
  1019. /* D+ pullup, software-controlled connect/disconnect to USB host */
  1020. .pullup = langwell_pullup,
  1021. .udc_start = langwell_start,
  1022. .udc_stop = langwell_stop,
  1023. };
  1024. /*-------------------------------------------------------------------------*/
  1025. /* device controller operations */
  1026. /* reset device controller */
  1027. static int langwell_udc_reset(struct langwell_udc *dev)
  1028. {
  1029. u32 usbcmd, usbmode, devlc, endpointlistaddr;
  1030. u8 devlc_byte0, devlc_byte2;
  1031. unsigned long timeout;
  1032. if (!dev)
  1033. return -EINVAL;
  1034. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1035. /* set controller to stop state */
  1036. usbcmd = readl(&dev->op_regs->usbcmd);
  1037. usbcmd &= ~CMD_RUNSTOP;
  1038. writel(usbcmd, &dev->op_regs->usbcmd);
  1039. /* reset device controller */
  1040. usbcmd = readl(&dev->op_regs->usbcmd);
  1041. usbcmd |= CMD_RST;
  1042. writel(usbcmd, &dev->op_regs->usbcmd);
  1043. /* wait for reset to complete */
  1044. timeout = jiffies + RESET_TIMEOUT;
  1045. while (readl(&dev->op_regs->usbcmd) & CMD_RST) {
  1046. if (time_after(jiffies, timeout)) {
  1047. dev_err(&dev->pdev->dev, "device reset timeout\n");
  1048. return -ETIMEDOUT;
  1049. }
  1050. cpu_relax();
  1051. }
  1052. /* set controller to device mode */
  1053. usbmode = readl(&dev->op_regs->usbmode);
  1054. usbmode |= MODE_DEVICE;
  1055. /* turn setup lockout off, require setup tripwire in usbcmd */
  1056. usbmode |= MODE_SLOM;
  1057. writel(usbmode, &dev->op_regs->usbmode);
  1058. usbmode = readl(&dev->op_regs->usbmode);
  1059. dev_vdbg(&dev->pdev->dev, "usbmode=0x%08x\n", usbmode);
  1060. /* Write-Clear setup status */
  1061. writel(0, &dev->op_regs->usbsts);
  1062. /* if support USB LPM, ACK all LPM token */
  1063. if (dev->lpm) {
  1064. devlc = readl(&dev->op_regs->devlc);
  1065. dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
  1066. /* FIXME: workaround for Langwell A1/A2/A3 sighting */
  1067. devlc &= ~LPM_STL; /* don't STALL LPM token */
  1068. devlc &= ~LPM_NYT_ACK; /* ACK LPM token */
  1069. devlc_byte0 = devlc & 0xff;
  1070. devlc_byte2 = (devlc >> 16) & 0xff;
  1071. writeb(devlc_byte0, (u8 *)&dev->op_regs->devlc);
  1072. writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
  1073. devlc = readl(&dev->op_regs->devlc);
  1074. dev_vdbg(&dev->pdev->dev,
  1075. "ACK LPM token, devlc = 0x%08x\n", devlc);
  1076. }
  1077. /* fill endpointlistaddr register */
  1078. endpointlistaddr = dev->ep_dqh_dma;
  1079. endpointlistaddr &= ENDPOINTLISTADDR_MASK;
  1080. writel(endpointlistaddr, &dev->op_regs->endpointlistaddr);
  1081. dev_vdbg(&dev->pdev->dev,
  1082. "dQH base (vir: %pK, phy: 0x%08x), endpointlistaddr=0x%08x\n",
  1083. dev->ep_dqh, endpointlistaddr,
  1084. readl(&dev->op_regs->endpointlistaddr));
  1085. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1086. return 0;
  1087. }
  1088. /* reinitialize device controller endpoints */
  1089. static int eps_reinit(struct langwell_udc *dev)
  1090. {
  1091. struct langwell_ep *ep;
  1092. char name[14];
  1093. int i;
  1094. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1095. /* initialize ep0 */
  1096. ep = &dev->ep[0];
  1097. ep->dev = dev;
  1098. strncpy(ep->name, "ep0", sizeof(ep->name));
  1099. ep->ep.name = ep->name;
  1100. ep->ep.ops = &langwell_ep_ops;
  1101. ep->stopped = 0;
  1102. ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
  1103. ep->ep_num = 0;
  1104. ep->desc = &langwell_ep0_desc;
  1105. INIT_LIST_HEAD(&ep->queue);
  1106. ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
  1107. /* initialize other endpoints */
  1108. for (i = 2; i < dev->ep_max; i++) {
  1109. ep = &dev->ep[i];
  1110. if (i % 2)
  1111. snprintf(name, sizeof(name), "ep%din", i / 2);
  1112. else
  1113. snprintf(name, sizeof(name), "ep%dout", i / 2);
  1114. ep->dev = dev;
  1115. strncpy(ep->name, name, sizeof(ep->name));
  1116. ep->ep.name = ep->name;
  1117. ep->ep.ops = &langwell_ep_ops;
  1118. ep->stopped = 0;
  1119. ep->ep.maxpacket = (unsigned short) ~0;
  1120. ep->ep_num = i / 2;
  1121. INIT_LIST_HEAD(&ep->queue);
  1122. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  1123. }
  1124. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1125. return 0;
  1126. }
  1127. /* enable interrupt and set controller to run state */
  1128. static void langwell_udc_start(struct langwell_udc *dev)
  1129. {
  1130. u32 usbintr, usbcmd;
  1131. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1132. /* enable interrupts */
  1133. usbintr = INTR_ULPIE /* ULPI */
  1134. | INTR_SLE /* suspend */
  1135. /* | INTR_SRE SOF received */
  1136. | INTR_URE /* USB reset */
  1137. | INTR_AAE /* async advance */
  1138. | INTR_SEE /* system error */
  1139. | INTR_FRE /* frame list rollover */
  1140. | INTR_PCE /* port change detect */
  1141. | INTR_UEE /* USB error interrupt */
  1142. | INTR_UE; /* USB interrupt */
  1143. writel(usbintr, &dev->op_regs->usbintr);
  1144. /* clear stopped bit */
  1145. dev->stopped = 0;
  1146. /* set controller to run */
  1147. usbcmd = readl(&dev->op_regs->usbcmd);
  1148. usbcmd |= CMD_RUNSTOP;
  1149. writel(usbcmd, &dev->op_regs->usbcmd);
  1150. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1151. }
  1152. /* disable interrupt and set controller to stop state */
  1153. static void langwell_udc_stop(struct langwell_udc *dev)
  1154. {
  1155. u32 usbcmd;
  1156. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1157. /* disable all interrupts */
  1158. writel(0, &dev->op_regs->usbintr);
  1159. /* set stopped bit */
  1160. dev->stopped = 1;
  1161. /* set controller to stop state */
  1162. usbcmd = readl(&dev->op_regs->usbcmd);
  1163. usbcmd &= ~CMD_RUNSTOP;
  1164. writel(usbcmd, &dev->op_regs->usbcmd);
  1165. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1166. }
  1167. /* stop all USB activities */
  1168. static void stop_activity(struct langwell_udc *dev)
  1169. {
  1170. struct langwell_ep *ep;
  1171. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1172. nuke(&dev->ep[0], -ESHUTDOWN);
  1173. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1174. nuke(ep, -ESHUTDOWN);
  1175. }
  1176. /* report disconnect; the driver is already quiesced */
  1177. if (dev->driver) {
  1178. spin_unlock(&dev->lock);
  1179. dev->driver->disconnect(&dev->gadget);
  1180. spin_lock(&dev->lock);
  1181. }
  1182. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1183. }
  1184. /*-------------------------------------------------------------------------*/
  1185. /* device "function" sysfs attribute file */
  1186. static ssize_t show_function(struct device *_dev,
  1187. struct device_attribute *attr, char *buf)
  1188. {
  1189. struct langwell_udc *dev = dev_get_drvdata(_dev);
  1190. if (!dev->driver || !dev->driver->function
  1191. || strlen(dev->driver->function) > PAGE_SIZE)
  1192. return 0;
  1193. return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function);
  1194. }
  1195. static DEVICE_ATTR(function, S_IRUGO, show_function, NULL);
  1196. static inline enum usb_device_speed lpm_device_speed(u32 reg)
  1197. {
  1198. switch (LPM_PSPD(reg)) {
  1199. case LPM_SPEED_HIGH:
  1200. return USB_SPEED_HIGH;
  1201. case LPM_SPEED_FULL:
  1202. return USB_SPEED_FULL;
  1203. case LPM_SPEED_LOW:
  1204. return USB_SPEED_LOW;
  1205. default:
  1206. return USB_SPEED_UNKNOWN;
  1207. }
  1208. }
  1209. /* device "langwell_udc" sysfs attribute file */
  1210. static ssize_t show_langwell_udc(struct device *_dev,
  1211. struct device_attribute *attr, char *buf)
  1212. {
  1213. struct langwell_udc *dev = dev_get_drvdata(_dev);
  1214. struct langwell_request *req;
  1215. struct langwell_ep *ep = NULL;
  1216. char *next;
  1217. unsigned size;
  1218. unsigned t;
  1219. unsigned i;
  1220. unsigned long flags;
  1221. u32 tmp_reg;
  1222. next = buf;
  1223. size = PAGE_SIZE;
  1224. spin_lock_irqsave(&dev->lock, flags);
  1225. /* driver basic information */
  1226. t = scnprintf(next, size,
  1227. DRIVER_DESC "\n"
  1228. "%s version: %s\n"
  1229. "Gadget driver: %s\n\n",
  1230. driver_name, DRIVER_VERSION,
  1231. dev->driver ? dev->driver->driver.name : "(none)");
  1232. size -= t;
  1233. next += t;
  1234. /* device registers */
  1235. tmp_reg = readl(&dev->op_regs->usbcmd);
  1236. t = scnprintf(next, size,
  1237. "USBCMD reg:\n"
  1238. "SetupTW: %d\n"
  1239. "Run/Stop: %s\n\n",
  1240. (tmp_reg & CMD_SUTW) ? 1 : 0,
  1241. (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop");
  1242. size -= t;
  1243. next += t;
  1244. tmp_reg = readl(&dev->op_regs->usbsts);
  1245. t = scnprintf(next, size,
  1246. "USB Status Reg:\n"
  1247. "Device Suspend: %d\n"
  1248. "Reset Received: %d\n"
  1249. "System Error: %s\n"
  1250. "USB Error Interrupt: %s\n\n",
  1251. (tmp_reg & STS_SLI) ? 1 : 0,
  1252. (tmp_reg & STS_URI) ? 1 : 0,
  1253. (tmp_reg & STS_SEI) ? "Error" : "No error",
  1254. (tmp_reg & STS_UEI) ? "Error detected" : "No error");
  1255. size -= t;
  1256. next += t;
  1257. tmp_reg = readl(&dev->op_regs->usbintr);
  1258. t = scnprintf(next, size,
  1259. "USB Intrrupt Enable Reg:\n"
  1260. "Sleep Enable: %d\n"
  1261. "SOF Received Enable: %d\n"
  1262. "Reset Enable: %d\n"
  1263. "System Error Enable: %d\n"
  1264. "Port Change Dectected Enable: %d\n"
  1265. "USB Error Intr Enable: %d\n"
  1266. "USB Intr Enable: %d\n\n",
  1267. (tmp_reg & INTR_SLE) ? 1 : 0,
  1268. (tmp_reg & INTR_SRE) ? 1 : 0,
  1269. (tmp_reg & INTR_URE) ? 1 : 0,
  1270. (tmp_reg & INTR_SEE) ? 1 : 0,
  1271. (tmp_reg & INTR_PCE) ? 1 : 0,
  1272. (tmp_reg & INTR_UEE) ? 1 : 0,
  1273. (tmp_reg & INTR_UE) ? 1 : 0);
  1274. size -= t;
  1275. next += t;
  1276. tmp_reg = readl(&dev->op_regs->frindex);
  1277. t = scnprintf(next, size,
  1278. "USB Frame Index Reg:\n"
  1279. "Frame Number is 0x%08x\n\n",
  1280. (tmp_reg & FRINDEX_MASK));
  1281. size -= t;
  1282. next += t;
  1283. tmp_reg = readl(&dev->op_regs->deviceaddr);
  1284. t = scnprintf(next, size,
  1285. "USB Device Address Reg:\n"
  1286. "Device Addr is 0x%x\n\n",
  1287. USBADR(tmp_reg));
  1288. size -= t;
  1289. next += t;
  1290. tmp_reg = readl(&dev->op_regs->endpointlistaddr);
  1291. t = scnprintf(next, size,
  1292. "USB Endpoint List Address Reg:\n"
  1293. "Endpoint List Pointer is 0x%x\n\n",
  1294. EPBASE(tmp_reg));
  1295. size -= t;
  1296. next += t;
  1297. tmp_reg = readl(&dev->op_regs->portsc1);
  1298. t = scnprintf(next, size,
  1299. "USB Port Status & Control Reg:\n"
  1300. "Port Reset: %s\n"
  1301. "Port Suspend Mode: %s\n"
  1302. "Over-current Change: %s\n"
  1303. "Port Enable/Disable Change: %s\n"
  1304. "Port Enabled/Disabled: %s\n"
  1305. "Current Connect Status: %s\n"
  1306. "LPM Suspend Status: %s\n\n",
  1307. (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset",
  1308. (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend",
  1309. (tmp_reg & PORTS_OCC) ? "Detected" : "No",
  1310. (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed",
  1311. (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct",
  1312. (tmp_reg & PORTS_CCS) ? "Attached" : "Not Attached",
  1313. (tmp_reg & PORTS_SLP) ? "LPM L1" : "LPM L0");
  1314. size -= t;
  1315. next += t;
  1316. tmp_reg = readl(&dev->op_regs->devlc);
  1317. t = scnprintf(next, size,
  1318. "Device LPM Control Reg:\n"
  1319. "Parallel Transceiver : %d\n"
  1320. "Serial Transceiver : %d\n"
  1321. "Port Speed: %s\n"
  1322. "Port Force Full Speed Connenct: %s\n"
  1323. "PHY Low Power Suspend Clock: %s\n"
  1324. "BmAttributes: %d\n\n",
  1325. LPM_PTS(tmp_reg),
  1326. (tmp_reg & LPM_STS) ? 1 : 0,
  1327. usb_speed_string(lpm_device_speed(tmp_reg)),
  1328. (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force",
  1329. (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled",
  1330. LPM_BA(tmp_reg));
  1331. size -= t;
  1332. next += t;
  1333. tmp_reg = readl(&dev->op_regs->usbmode);
  1334. t = scnprintf(next, size,
  1335. "USB Mode Reg:\n"
  1336. "Controller Mode is : %s\n\n", ({
  1337. char *s;
  1338. switch (MODE_CM(tmp_reg)) {
  1339. case MODE_IDLE:
  1340. s = "Idle"; break;
  1341. case MODE_DEVICE:
  1342. s = "Device Controller"; break;
  1343. case MODE_HOST:
  1344. s = "Host Controller"; break;
  1345. default:
  1346. s = "None"; break;
  1347. }
  1348. s;
  1349. }));
  1350. size -= t;
  1351. next += t;
  1352. tmp_reg = readl(&dev->op_regs->endptsetupstat);
  1353. t = scnprintf(next, size,
  1354. "Endpoint Setup Status Reg:\n"
  1355. "SETUP on ep 0x%04x\n\n",
  1356. tmp_reg & SETUPSTAT_MASK);
  1357. size -= t;
  1358. next += t;
  1359. for (i = 0; i < dev->ep_max / 2; i++) {
  1360. tmp_reg = readl(&dev->op_regs->endptctrl[i]);
  1361. t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n",
  1362. i, tmp_reg);
  1363. size -= t;
  1364. next += t;
  1365. }
  1366. tmp_reg = readl(&dev->op_regs->endptprime);
  1367. t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg);
  1368. size -= t;
  1369. next += t;
  1370. /* langwell_udc, langwell_ep, langwell_request structure information */
  1371. ep = &dev->ep[0];
  1372. t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n",
  1373. ep->ep.name, ep->ep.maxpacket, ep->ep_num);
  1374. size -= t;
  1375. next += t;
  1376. if (list_empty(&ep->queue)) {
  1377. t = scnprintf(next, size, "its req queue is empty\n\n");
  1378. size -= t;
  1379. next += t;
  1380. } else {
  1381. list_for_each_entry(req, &ep->queue, queue) {
  1382. t = scnprintf(next, size,
  1383. "req %pK actual 0x%x length 0x%x buf %pK\n",
  1384. &req->req, req->req.actual,
  1385. req->req.length, req->req.buf);
  1386. size -= t;
  1387. next += t;
  1388. }
  1389. }
  1390. /* other gadget->eplist ep */
  1391. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1392. if (ep->desc) {
  1393. t = scnprintf(next, size,
  1394. "\n%s MaxPacketSize: 0x%x, "
  1395. "ep_num: %d\n",
  1396. ep->ep.name, ep->ep.maxpacket,
  1397. ep->ep_num);
  1398. size -= t;
  1399. next += t;
  1400. if (list_empty(&ep->queue)) {
  1401. t = scnprintf(next, size,
  1402. "its req queue is empty\n\n");
  1403. size -= t;
  1404. next += t;
  1405. } else {
  1406. list_for_each_entry(req, &ep->queue, queue) {
  1407. t = scnprintf(next, size,
  1408. "req %pK actual 0x%x length "
  1409. "0x%x buf %pK\n",
  1410. &req->req, req->req.actual,
  1411. req->req.length, req->req.buf);
  1412. size -= t;
  1413. next += t;
  1414. }
  1415. }
  1416. }
  1417. }
  1418. spin_unlock_irqrestore(&dev->lock, flags);
  1419. return PAGE_SIZE - size;
  1420. }
  1421. static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL);
  1422. /* device "remote_wakeup" sysfs attribute file */
  1423. static ssize_t store_remote_wakeup(struct device *_dev,
  1424. struct device_attribute *attr, const char *buf, size_t count)
  1425. {
  1426. struct langwell_udc *dev = dev_get_drvdata(_dev);
  1427. unsigned long flags;
  1428. ssize_t rc = count;
  1429. if (count > 2)
  1430. return -EINVAL;
  1431. if (count > 0 && buf[count-1] == '\n')
  1432. ((char *) buf)[count-1] = 0;
  1433. if (buf[0] != '1')
  1434. return -EINVAL;
  1435. /* force remote wakeup enabled in case gadget driver doesn't support */
  1436. spin_lock_irqsave(&dev->lock, flags);
  1437. dev->remote_wakeup = 1;
  1438. dev->dev_status |= (1 << USB_DEVICE_REMOTE_WAKEUP);
  1439. spin_unlock_irqrestore(&dev->lock, flags);
  1440. langwell_wakeup(&dev->gadget);
  1441. return rc;
  1442. }
  1443. static DEVICE_ATTR(remote_wakeup, S_IWUSR, NULL, store_remote_wakeup);
  1444. /*-------------------------------------------------------------------------*/
  1445. /*
  1446. * when a driver is successfully registered, it will receive
  1447. * control requests including set_configuration(), which enables
  1448. * non-control requests. then usb traffic follows until a
  1449. * disconnect is reported. then a host may connect again, or
  1450. * the driver might get unbound.
  1451. */
  1452. static int langwell_start(struct usb_gadget *g,
  1453. struct usb_gadget_driver *driver)
  1454. {
  1455. struct langwell_udc *dev = gadget_to_langwell(g);
  1456. unsigned long flags;
  1457. int retval;
  1458. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1459. spin_lock_irqsave(&dev->lock, flags);
  1460. /* hook up the driver ... */
  1461. driver->driver.bus = NULL;
  1462. dev->driver = driver;
  1463. dev->gadget.dev.driver = &driver->driver;
  1464. spin_unlock_irqrestore(&dev->lock, flags);
  1465. retval = device_create_file(&dev->pdev->dev, &dev_attr_function);
  1466. if (retval)
  1467. goto err;
  1468. dev->usb_state = USB_STATE_ATTACHED;
  1469. dev->ep0_state = WAIT_FOR_SETUP;
  1470. dev->ep0_dir = USB_DIR_OUT;
  1471. /* enable interrupt and set controller to run state */
  1472. if (dev->got_irq)
  1473. langwell_udc_start(dev);
  1474. dev_vdbg(&dev->pdev->dev,
  1475. "After langwell_udc_start(), print all registers:\n");
  1476. print_all_registers(dev);
  1477. dev_info(&dev->pdev->dev, "register driver: %s\n",
  1478. driver->driver.name);
  1479. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1480. return 0;
  1481. err:
  1482. dev->gadget.dev.driver = NULL;
  1483. dev->driver = NULL;
  1484. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1485. return retval;
  1486. }
  1487. /* unregister gadget driver */
  1488. static int langwell_stop(struct usb_gadget *g,
  1489. struct usb_gadget_driver *driver)
  1490. {
  1491. struct langwell_udc *dev = gadget_to_langwell(g);
  1492. unsigned long flags;
  1493. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1494. /* exit PHY low power suspend */
  1495. if (dev->pdev->device != 0x0829)
  1496. langwell_phy_low_power(dev, 0);
  1497. /* unbind OTG transceiver */
  1498. if (dev->transceiver)
  1499. (void)otg_set_peripheral(dev->transceiver->otg, 0);
  1500. /* disable interrupt and set controller to stop state */
  1501. langwell_udc_stop(dev);
  1502. dev->usb_state = USB_STATE_ATTACHED;
  1503. dev->ep0_state = WAIT_FOR_SETUP;
  1504. dev->ep0_dir = USB_DIR_OUT;
  1505. spin_lock_irqsave(&dev->lock, flags);
  1506. /* stop all usb activities */
  1507. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1508. dev->gadget.dev.driver = NULL;
  1509. dev->driver = NULL;
  1510. stop_activity(dev);
  1511. spin_unlock_irqrestore(&dev->lock, flags);
  1512. device_remove_file(&dev->pdev->dev, &dev_attr_function);
  1513. dev_info(&dev->pdev->dev, "unregistered driver '%s'\n",
  1514. driver->driver.name);
  1515. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1516. return 0;
  1517. }
  1518. /*-------------------------------------------------------------------------*/
  1519. /*
  1520. * setup tripwire is used as a semaphore to ensure that the setup data
  1521. * payload is extracted from a dQH without being corrupted
  1522. */
  1523. static void setup_tripwire(struct langwell_udc *dev)
  1524. {
  1525. u32 usbcmd,
  1526. endptsetupstat;
  1527. unsigned long timeout;
  1528. struct langwell_dqh *dqh;
  1529. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1530. /* ep0 OUT dQH */
  1531. dqh = &dev->ep_dqh[EP_DIR_OUT];
  1532. /* Write-Clear endptsetupstat */
  1533. endptsetupstat = readl(&dev->op_regs->endptsetupstat);
  1534. writel(endptsetupstat, &dev->op_regs->endptsetupstat);
  1535. /* wait until endptsetupstat is cleared */
  1536. timeout = jiffies + SETUPSTAT_TIMEOUT;
  1537. while (readl(&dev->op_regs->endptsetupstat)) {
  1538. if (time_after(jiffies, timeout)) {
  1539. dev_err(&dev->pdev->dev, "setup_tripwire timeout\n");
  1540. break;
  1541. }
  1542. cpu_relax();
  1543. }
  1544. /* while a hazard exists when setup packet arrives */
  1545. do {
  1546. /* set setup tripwire bit */
  1547. usbcmd = readl(&dev->op_regs->usbcmd);
  1548. writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd);
  1549. /* copy the setup packet to local buffer */
  1550. memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8);
  1551. } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW));
  1552. /* Write-Clear setup tripwire bit */
  1553. usbcmd = readl(&dev->op_regs->usbcmd);
  1554. writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd);
  1555. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1556. }
  1557. /* protocol ep0 stall, will automatically be cleared on new transaction */
  1558. static void ep0_stall(struct langwell_udc *dev)
  1559. {
  1560. u32 endptctrl;
  1561. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1562. /* set TX and RX to stall */
  1563. endptctrl = readl(&dev->op_regs->endptctrl[0]);
  1564. endptctrl |= EPCTRL_TXS | EPCTRL_RXS;
  1565. writel(endptctrl, &dev->op_regs->endptctrl[0]);
  1566. /* update ep0 state */
  1567. dev->ep0_state = WAIT_FOR_SETUP;
  1568. dev->ep0_dir = USB_DIR_OUT;
  1569. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1570. }
  1571. /* PRIME a status phase for ep0 */
  1572. static int prime_status_phase(struct langwell_udc *dev, int dir)
  1573. {
  1574. struct langwell_request *req;
  1575. struct langwell_ep *ep;
  1576. int status = 0;
  1577. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1578. if (dir == EP_DIR_IN)
  1579. dev->ep0_dir = USB_DIR_IN;
  1580. else
  1581. dev->ep0_dir = USB_DIR_OUT;
  1582. ep = &dev->ep[0];
  1583. dev->ep0_state = WAIT_FOR_OUT_STATUS;
  1584. req = dev->status_req;
  1585. req->ep = ep;
  1586. req->req.length = 0;
  1587. req->req.status = -EINPROGRESS;
  1588. req->req.actual = 0;
  1589. req->req.complete = NULL;
  1590. req->dtd_count = 0;
  1591. if (!req_to_dtd(req))
  1592. status = queue_dtd(ep, req);
  1593. else
  1594. return -ENOMEM;
  1595. if (status)
  1596. dev_err(&dev->pdev->dev, "can't queue ep0 status request\n");
  1597. list_add_tail(&req->queue, &ep->queue);
  1598. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1599. return status;
  1600. }
  1601. /* SET_ADDRESS request routine */
  1602. static void set_address(struct langwell_udc *dev, u16 value,
  1603. u16 index, u16 length)
  1604. {
  1605. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1606. /* save the new address to device struct */
  1607. dev->dev_addr = (u8) value;
  1608. dev_vdbg(&dev->pdev->dev, "dev->dev_addr = %d\n", dev->dev_addr);
  1609. /* update usb state */
  1610. dev->usb_state = USB_STATE_ADDRESS;
  1611. /* STATUS phase */
  1612. if (prime_status_phase(dev, EP_DIR_IN))
  1613. ep0_stall(dev);
  1614. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1615. }
  1616. /* return endpoint by windex */
  1617. static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev,
  1618. u16 wIndex)
  1619. {
  1620. struct langwell_ep *ep;
  1621. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1622. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  1623. return &dev->ep[0];
  1624. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1625. u8 bEndpointAddress;
  1626. if (!ep->desc)
  1627. continue;
  1628. bEndpointAddress = ep->desc->bEndpointAddress;
  1629. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  1630. continue;
  1631. if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
  1632. == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
  1633. return ep;
  1634. }
  1635. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1636. return NULL;
  1637. }
  1638. /* return whether endpoint is stalled, 0: not stalled; 1: stalled */
  1639. static int ep_is_stall(struct langwell_ep *ep)
  1640. {
  1641. struct langwell_udc *dev = ep->dev;
  1642. u32 endptctrl;
  1643. int retval;
  1644. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1645. endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]);
  1646. if (is_in(ep))
  1647. retval = endptctrl & EPCTRL_TXS ? 1 : 0;
  1648. else
  1649. retval = endptctrl & EPCTRL_RXS ? 1 : 0;
  1650. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1651. return retval;
  1652. }
  1653. /* GET_STATUS request routine */
  1654. static void get_status(struct langwell_udc *dev, u8 request_type, u16 value,
  1655. u16 index, u16 length)
  1656. {
  1657. struct langwell_request *req;
  1658. struct langwell_ep *ep;
  1659. u16 status_data = 0; /* 16 bits cpu view status data */
  1660. int status = 0;
  1661. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1662. ep = &dev->ep[0];
  1663. if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1664. /* get device status */
  1665. status_data = dev->dev_status;
  1666. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
  1667. /* get interface status */
  1668. status_data = 0;
  1669. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
  1670. /* get endpoint status */
  1671. struct langwell_ep *epn;
  1672. epn = get_ep_by_windex(dev, index);
  1673. /* stall if endpoint doesn't exist */
  1674. if (!epn)
  1675. goto stall;
  1676. status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT;
  1677. }
  1678. dev_dbg(&dev->pdev->dev, "get status data: 0x%04x\n", status_data);
  1679. dev->ep0_dir = USB_DIR_IN;
  1680. /* borrow the per device status_req */
  1681. req = dev->status_req;
  1682. /* fill in the reqest structure */
  1683. *((u16 *) req->req.buf) = cpu_to_le16(status_data);
  1684. req->ep = ep;
  1685. req->req.length = 2;
  1686. req->req.status = -EINPROGRESS;
  1687. req->req.actual = 0;
  1688. req->req.complete = NULL;
  1689. req->dtd_count = 0;
  1690. /* prime the data phase */
  1691. if (!req_to_dtd(req))
  1692. status = queue_dtd(ep, req);
  1693. else /* no mem */
  1694. goto stall;
  1695. if (status) {
  1696. dev_err(&dev->pdev->dev,
  1697. "response error on GET_STATUS request\n");
  1698. goto stall;
  1699. }
  1700. list_add_tail(&req->queue, &ep->queue);
  1701. dev->ep0_state = DATA_STATE_XMIT;
  1702. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1703. return;
  1704. stall:
  1705. ep0_stall(dev);
  1706. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1707. }
  1708. /* setup packet interrupt handler */
  1709. static void handle_setup_packet(struct langwell_udc *dev,
  1710. struct usb_ctrlrequest *setup)
  1711. {
  1712. u16 wValue = le16_to_cpu(setup->wValue);
  1713. u16 wIndex = le16_to_cpu(setup->wIndex);
  1714. u16 wLength = le16_to_cpu(setup->wLength);
  1715. u32 portsc1;
  1716. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1717. /* ep0 fifo flush */
  1718. nuke(&dev->ep[0], -ESHUTDOWN);
  1719. dev_dbg(&dev->pdev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
  1720. setup->bRequestType, setup->bRequest,
  1721. wValue, wIndex, wLength);
  1722. /* RNDIS gadget delegate */
  1723. if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) {
  1724. /* USB_CDC_SEND_ENCAPSULATED_COMMAND */
  1725. goto delegate;
  1726. }
  1727. /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
  1728. if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) {
  1729. /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
  1730. goto delegate;
  1731. }
  1732. /* We process some stardard setup requests here */
  1733. switch (setup->bRequest) {
  1734. case USB_REQ_GET_STATUS:
  1735. dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_GET_STATUS\n");
  1736. /* get status, DATA and STATUS phase */
  1737. if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
  1738. != (USB_DIR_IN | USB_TYPE_STANDARD))
  1739. break;
  1740. get_status(dev, setup->bRequestType, wValue, wIndex, wLength);
  1741. goto end;
  1742. case USB_REQ_SET_ADDRESS:
  1743. dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_SET_ADDRESS\n");
  1744. /* STATUS phase */
  1745. if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
  1746. | USB_RECIP_DEVICE))
  1747. break;
  1748. set_address(dev, wValue, wIndex, wLength);
  1749. goto end;
  1750. case USB_REQ_CLEAR_FEATURE:
  1751. case USB_REQ_SET_FEATURE:
  1752. /* STATUS phase */
  1753. {
  1754. int rc = -EOPNOTSUPP;
  1755. if (setup->bRequest == USB_REQ_SET_FEATURE)
  1756. dev_dbg(&dev->pdev->dev,
  1757. "SETUP: USB_REQ_SET_FEATURE\n");
  1758. else if (setup->bRequest == USB_REQ_CLEAR_FEATURE)
  1759. dev_dbg(&dev->pdev->dev,
  1760. "SETUP: USB_REQ_CLEAR_FEATURE\n");
  1761. if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
  1762. == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
  1763. struct langwell_ep *epn;
  1764. epn = get_ep_by_windex(dev, wIndex);
  1765. /* stall if endpoint doesn't exist */
  1766. if (!epn) {
  1767. ep0_stall(dev);
  1768. goto end;
  1769. }
  1770. if (wValue != 0 || wLength != 0
  1771. || epn->ep_num > dev->ep_max)
  1772. break;
  1773. spin_unlock(&dev->lock);
  1774. rc = langwell_ep_set_halt(&epn->ep,
  1775. (setup->bRequest == USB_REQ_SET_FEATURE)
  1776. ? 1 : 0);
  1777. spin_lock(&dev->lock);
  1778. } else if ((setup->bRequestType & (USB_RECIP_MASK
  1779. | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
  1780. | USB_TYPE_STANDARD)) {
  1781. rc = 0;
  1782. switch (wValue) {
  1783. case USB_DEVICE_REMOTE_WAKEUP:
  1784. if (setup->bRequest == USB_REQ_SET_FEATURE) {
  1785. dev->remote_wakeup = 1;
  1786. dev->dev_status |= (1 << wValue);
  1787. } else {
  1788. dev->remote_wakeup = 0;
  1789. dev->dev_status &= ~(1 << wValue);
  1790. }
  1791. break;
  1792. case USB_DEVICE_TEST_MODE:
  1793. dev_dbg(&dev->pdev->dev, "SETUP: TEST MODE\n");
  1794. if ((wIndex & 0xff) ||
  1795. (dev->gadget.speed != USB_SPEED_HIGH))
  1796. ep0_stall(dev);
  1797. switch (wIndex >> 8) {
  1798. case TEST_J:
  1799. case TEST_K:
  1800. case TEST_SE0_NAK:
  1801. case TEST_PACKET:
  1802. case TEST_FORCE_EN:
  1803. if (prime_status_phase(dev, EP_DIR_IN))
  1804. ep0_stall(dev);
  1805. portsc1 = readl(&dev->op_regs->portsc1);
  1806. portsc1 |= (wIndex & 0xf00) << 8;
  1807. writel(portsc1, &dev->op_regs->portsc1);
  1808. goto end;
  1809. default:
  1810. rc = -EOPNOTSUPP;
  1811. }
  1812. break;
  1813. default:
  1814. rc = -EOPNOTSUPP;
  1815. break;
  1816. }
  1817. if (!gadget_is_otg(&dev->gadget))
  1818. break;
  1819. else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE)
  1820. dev->gadget.b_hnp_enable = 1;
  1821. else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
  1822. dev->gadget.a_hnp_support = 1;
  1823. else if (setup->bRequest ==
  1824. USB_DEVICE_A_ALT_HNP_SUPPORT)
  1825. dev->gadget.a_alt_hnp_support = 1;
  1826. else
  1827. break;
  1828. } else
  1829. break;
  1830. if (rc == 0) {
  1831. if (prime_status_phase(dev, EP_DIR_IN))
  1832. ep0_stall(dev);
  1833. }
  1834. goto end;
  1835. }
  1836. case USB_REQ_GET_DESCRIPTOR:
  1837. dev_dbg(&dev->pdev->dev,
  1838. "SETUP: USB_REQ_GET_DESCRIPTOR\n");
  1839. goto delegate;
  1840. case USB_REQ_SET_DESCRIPTOR:
  1841. dev_dbg(&dev->pdev->dev,
  1842. "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n");
  1843. goto delegate;
  1844. case USB_REQ_GET_CONFIGURATION:
  1845. dev_dbg(&dev->pdev->dev,
  1846. "SETUP: USB_REQ_GET_CONFIGURATION\n");
  1847. goto delegate;
  1848. case USB_REQ_SET_CONFIGURATION:
  1849. dev_dbg(&dev->pdev->dev,
  1850. "SETUP: USB_REQ_SET_CONFIGURATION\n");
  1851. goto delegate;
  1852. case USB_REQ_GET_INTERFACE:
  1853. dev_dbg(&dev->pdev->dev,
  1854. "SETUP: USB_REQ_GET_INTERFACE\n");
  1855. goto delegate;
  1856. case USB_REQ_SET_INTERFACE:
  1857. dev_dbg(&dev->pdev->dev,
  1858. "SETUP: USB_REQ_SET_INTERFACE\n");
  1859. goto delegate;
  1860. case USB_REQ_SYNCH_FRAME:
  1861. dev_dbg(&dev->pdev->dev,
  1862. "SETUP: USB_REQ_SYNCH_FRAME unsupported\n");
  1863. goto delegate;
  1864. default:
  1865. /* delegate USB standard requests to the gadget driver */
  1866. goto delegate;
  1867. delegate:
  1868. /* USB requests handled by gadget */
  1869. if (wLength) {
  1870. /* DATA phase from gadget, STATUS phase from udc */
  1871. dev->ep0_dir = (setup->bRequestType & USB_DIR_IN)
  1872. ? USB_DIR_IN : USB_DIR_OUT;
  1873. dev_vdbg(&dev->pdev->dev,
  1874. "dev->ep0_dir = 0x%x, wLength = %d\n",
  1875. dev->ep0_dir, wLength);
  1876. spin_unlock(&dev->lock);
  1877. if (dev->driver->setup(&dev->gadget,
  1878. &dev->local_setup_buff) < 0)
  1879. ep0_stall(dev);
  1880. spin_lock(&dev->lock);
  1881. dev->ep0_state = (setup->bRequestType & USB_DIR_IN)
  1882. ? DATA_STATE_XMIT : DATA_STATE_RECV;
  1883. } else {
  1884. /* no DATA phase, IN STATUS phase from gadget */
  1885. dev->ep0_dir = USB_DIR_IN;
  1886. dev_vdbg(&dev->pdev->dev,
  1887. "dev->ep0_dir = 0x%x, wLength = %d\n",
  1888. dev->ep0_dir, wLength);
  1889. spin_unlock(&dev->lock);
  1890. if (dev->driver->setup(&dev->gadget,
  1891. &dev->local_setup_buff) < 0)
  1892. ep0_stall(dev);
  1893. spin_lock(&dev->lock);
  1894. dev->ep0_state = WAIT_FOR_OUT_STATUS;
  1895. }
  1896. break;
  1897. }
  1898. end:
  1899. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1900. }
  1901. /* transfer completion, process endpoint request and free the completed dTDs
  1902. * for this request
  1903. */
  1904. static int process_ep_req(struct langwell_udc *dev, int index,
  1905. struct langwell_request *curr_req)
  1906. {
  1907. struct langwell_dtd *curr_dtd;
  1908. struct langwell_dqh *curr_dqh;
  1909. int td_complete, actual, remaining_length;
  1910. int i, dir;
  1911. u8 dtd_status = 0;
  1912. int retval = 0;
  1913. curr_dqh = &dev->ep_dqh[index];
  1914. dir = index % 2;
  1915. curr_dtd = curr_req->head;
  1916. td_complete = 0;
  1917. actual = curr_req->req.length;
  1918. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1919. for (i = 0; i < curr_req->dtd_count; i++) {
  1920. /* command execution states by dTD */
  1921. dtd_status = curr_dtd->dtd_status;
  1922. barrier();
  1923. remaining_length = le16_to_cpu(curr_dtd->dtd_total);
  1924. actual -= remaining_length;
  1925. if (!dtd_status) {
  1926. /* transfers completed successfully */
  1927. if (!remaining_length) {
  1928. td_complete++;
  1929. dev_vdbg(&dev->pdev->dev,
  1930. "dTD transmitted successfully\n");
  1931. } else {
  1932. if (dir) {
  1933. dev_vdbg(&dev->pdev->dev,
  1934. "TX dTD remains data\n");
  1935. retval = -EPROTO;
  1936. break;
  1937. } else {
  1938. td_complete++;
  1939. break;
  1940. }
  1941. }
  1942. } else {
  1943. /* transfers completed with errors */
  1944. if (dtd_status & DTD_STS_ACTIVE) {
  1945. dev_dbg(&dev->pdev->dev,
  1946. "dTD status ACTIVE dQH[%d]\n", index);
  1947. retval = 1;
  1948. return retval;
  1949. } else if (dtd_status & DTD_STS_HALTED) {
  1950. dev_err(&dev->pdev->dev,
  1951. "dTD error %08x dQH[%d]\n",
  1952. dtd_status, index);
  1953. /* clear the errors and halt condition */
  1954. curr_dqh->dtd_status = 0;
  1955. retval = -EPIPE;
  1956. break;
  1957. } else if (dtd_status & DTD_STS_DBE) {
  1958. dev_dbg(&dev->pdev->dev,
  1959. "data buffer (overflow) error\n");
  1960. retval = -EPROTO;
  1961. break;
  1962. } else if (dtd_status & DTD_STS_TRE) {
  1963. dev_dbg(&dev->pdev->dev,
  1964. "transaction(ISO) error\n");
  1965. retval = -EILSEQ;
  1966. break;
  1967. } else
  1968. dev_err(&dev->pdev->dev,
  1969. "unknown error (0x%x)!\n",
  1970. dtd_status);
  1971. }
  1972. if (i != curr_req->dtd_count - 1)
  1973. curr_dtd = (struct langwell_dtd *)
  1974. curr_dtd->next_dtd_virt;
  1975. }
  1976. if (retval)
  1977. return retval;
  1978. curr_req->req.actual = actual;
  1979. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1980. return 0;
  1981. }
  1982. /* complete DATA or STATUS phase of ep0 prime status phase if needed */
  1983. static void ep0_req_complete(struct langwell_udc *dev,
  1984. struct langwell_ep *ep0, struct langwell_request *req)
  1985. {
  1986. u32 new_addr;
  1987. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1988. if (dev->usb_state == USB_STATE_ADDRESS) {
  1989. /* set the new address */
  1990. new_addr = (u32)dev->dev_addr;
  1991. writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr);
  1992. new_addr = USBADR(readl(&dev->op_regs->deviceaddr));
  1993. dev_vdbg(&dev->pdev->dev, "new_addr = %d\n", new_addr);
  1994. }
  1995. done(ep0, req, 0);
  1996. switch (dev->ep0_state) {
  1997. case DATA_STATE_XMIT:
  1998. /* receive status phase */
  1999. if (prime_status_phase(dev, EP_DIR_OUT))
  2000. ep0_stall(dev);
  2001. break;
  2002. case DATA_STATE_RECV:
  2003. /* send status phase */
  2004. if (prime_status_phase(dev, EP_DIR_IN))
  2005. ep0_stall(dev);
  2006. break;
  2007. case WAIT_FOR_OUT_STATUS:
  2008. dev->ep0_state = WAIT_FOR_SETUP;
  2009. break;
  2010. case WAIT_FOR_SETUP:
  2011. dev_err(&dev->pdev->dev, "unexpect ep0 packets\n");
  2012. break;
  2013. default:
  2014. ep0_stall(dev);
  2015. break;
  2016. }
  2017. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2018. }
  2019. /* USB transfer completion interrupt */
  2020. static void handle_trans_complete(struct langwell_udc *dev)
  2021. {
  2022. u32 complete_bits;
  2023. int i, ep_num, dir, bit_mask, status;
  2024. struct langwell_ep *epn;
  2025. struct langwell_request *curr_req, *temp_req;
  2026. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2027. complete_bits = readl(&dev->op_regs->endptcomplete);
  2028. dev_vdbg(&dev->pdev->dev, "endptcomplete register: 0x%08x\n",
  2029. complete_bits);
  2030. /* Write-Clear the bits in endptcomplete register */
  2031. writel(complete_bits, &dev->op_regs->endptcomplete);
  2032. if (!complete_bits) {
  2033. dev_dbg(&dev->pdev->dev, "complete_bits = 0\n");
  2034. goto done;
  2035. }
  2036. for (i = 0; i < dev->ep_max; i++) {
  2037. ep_num = i / 2;
  2038. dir = i % 2;
  2039. bit_mask = 1 << (ep_num + 16 * dir);
  2040. if (!(complete_bits & bit_mask))
  2041. continue;
  2042. /* ep0 */
  2043. if (i == 1)
  2044. epn = &dev->ep[0];
  2045. else
  2046. epn = &dev->ep[i];
  2047. if (epn->name == NULL) {
  2048. dev_warn(&dev->pdev->dev, "invalid endpoint\n");
  2049. continue;
  2050. }
  2051. if (i < 2)
  2052. /* ep0 in and out */
  2053. dev_dbg(&dev->pdev->dev, "%s-%s transfer completed\n",
  2054. epn->name,
  2055. is_in(epn) ? "in" : "out");
  2056. else
  2057. dev_dbg(&dev->pdev->dev, "%s transfer completed\n",
  2058. epn->name);
  2059. /* process the req queue until an uncomplete request */
  2060. list_for_each_entry_safe(curr_req, temp_req,
  2061. &epn->queue, queue) {
  2062. status = process_ep_req(dev, i, curr_req);
  2063. dev_vdbg(&dev->pdev->dev, "%s req status: %d\n",
  2064. epn->name, status);
  2065. if (status)
  2066. break;
  2067. /* write back status to req */
  2068. curr_req->req.status = status;
  2069. /* ep0 request completion */
  2070. if (ep_num == 0) {
  2071. ep0_req_complete(dev, epn, curr_req);
  2072. break;
  2073. } else {
  2074. done(epn, curr_req, status);
  2075. }
  2076. }
  2077. }
  2078. done:
  2079. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2080. }
  2081. /* port change detect interrupt handler */
  2082. static void handle_port_change(struct langwell_udc *dev)
  2083. {
  2084. u32 portsc1, devlc;
  2085. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2086. if (dev->bus_reset)
  2087. dev->bus_reset = 0;
  2088. portsc1 = readl(&dev->op_regs->portsc1);
  2089. devlc = readl(&dev->op_regs->devlc);
  2090. dev_vdbg(&dev->pdev->dev, "portsc1 = 0x%08x, devlc = 0x%08x\n",
  2091. portsc1, devlc);
  2092. /* bus reset is finished */
  2093. if (!(portsc1 & PORTS_PR)) {
  2094. /* get the speed */
  2095. dev->gadget.speed = lpm_device_speed(devlc);
  2096. dev_vdbg(&dev->pdev->dev, "dev->gadget.speed = %d\n",
  2097. dev->gadget.speed);
  2098. }
  2099. /* LPM L0 to L1 */
  2100. if (dev->lpm && dev->lpm_state == LPM_L0)
  2101. if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) {
  2102. dev_info(&dev->pdev->dev, "LPM L0 to L1\n");
  2103. dev->lpm_state = LPM_L1;
  2104. }
  2105. /* LPM L1 to L0, force resume or remote wakeup finished */
  2106. if (dev->lpm && dev->lpm_state == LPM_L1)
  2107. if (!(portsc1 & PORTS_SUSP)) {
  2108. dev_info(&dev->pdev->dev, "LPM L1 to L0\n");
  2109. dev->lpm_state = LPM_L0;
  2110. }
  2111. /* update USB state */
  2112. if (!dev->resume_state)
  2113. dev->usb_state = USB_STATE_DEFAULT;
  2114. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2115. }
  2116. /* USB reset interrupt handler */
  2117. static void handle_usb_reset(struct langwell_udc *dev)
  2118. {
  2119. u32 deviceaddr,
  2120. endptsetupstat,
  2121. endptcomplete;
  2122. unsigned long timeout;
  2123. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2124. /* Write-Clear the device address */
  2125. deviceaddr = readl(&dev->op_regs->deviceaddr);
  2126. writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr);
  2127. dev->dev_addr = 0;
  2128. /* clear usb state */
  2129. dev->resume_state = 0;
  2130. /* LPM L1 to L0, reset */
  2131. if (dev->lpm)
  2132. dev->lpm_state = LPM_L0;
  2133. dev->ep0_dir = USB_DIR_OUT;
  2134. dev->ep0_state = WAIT_FOR_SETUP;
  2135. /* remote wakeup reset to 0 when the device is reset */
  2136. dev->remote_wakeup = 0;
  2137. dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
  2138. dev->gadget.b_hnp_enable = 0;
  2139. dev->gadget.a_hnp_support = 0;
  2140. dev->gadget.a_alt_hnp_support = 0;
  2141. /* Write-Clear all the setup token semaphores */
  2142. endptsetupstat = readl(&dev->op_regs->endptsetupstat);
  2143. writel(endptsetupstat, &dev->op_regs->endptsetupstat);
  2144. /* Write-Clear all the endpoint complete status bits */
  2145. endptcomplete = readl(&dev->op_regs->endptcomplete);
  2146. writel(endptcomplete, &dev->op_regs->endptcomplete);
  2147. /* wait until all endptprime bits cleared */
  2148. timeout = jiffies + PRIME_TIMEOUT;
  2149. while (readl(&dev->op_regs->endptprime)) {
  2150. if (time_after(jiffies, timeout)) {
  2151. dev_err(&dev->pdev->dev, "USB reset timeout\n");
  2152. break;
  2153. }
  2154. cpu_relax();
  2155. }
  2156. /* write 1s to endptflush register to clear any primed buffers */
  2157. writel((u32) ~0, &dev->op_regs->endptflush);
  2158. if (readl(&dev->op_regs->portsc1) & PORTS_PR) {
  2159. dev_vdbg(&dev->pdev->dev, "USB bus reset\n");
  2160. /* bus is reseting */
  2161. dev->bus_reset = 1;
  2162. /* reset all the queues, stop all USB activities */
  2163. stop_activity(dev);
  2164. dev->usb_state = USB_STATE_DEFAULT;
  2165. } else {
  2166. dev_vdbg(&dev->pdev->dev, "device controller reset\n");
  2167. /* controller reset */
  2168. langwell_udc_reset(dev);
  2169. /* reset all the queues, stop all USB activities */
  2170. stop_activity(dev);
  2171. /* reset ep0 dQH and endptctrl */
  2172. ep0_reset(dev);
  2173. /* enable interrupt and set controller to run state */
  2174. langwell_udc_start(dev);
  2175. dev->usb_state = USB_STATE_ATTACHED;
  2176. }
  2177. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2178. }
  2179. /* USB bus suspend/resume interrupt */
  2180. static void handle_bus_suspend(struct langwell_udc *dev)
  2181. {
  2182. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2183. dev->resume_state = dev->usb_state;
  2184. dev->usb_state = USB_STATE_SUSPENDED;
  2185. /* report suspend to the driver */
  2186. if (dev->driver) {
  2187. if (dev->driver->suspend) {
  2188. spin_unlock(&dev->lock);
  2189. dev->driver->suspend(&dev->gadget);
  2190. spin_lock(&dev->lock);
  2191. dev_dbg(&dev->pdev->dev, "suspend %s\n",
  2192. dev->driver->driver.name);
  2193. }
  2194. }
  2195. /* enter PHY low power suspend */
  2196. if (dev->pdev->device != 0x0829)
  2197. langwell_phy_low_power(dev, 0);
  2198. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2199. }
  2200. static void handle_bus_resume(struct langwell_udc *dev)
  2201. {
  2202. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2203. dev->usb_state = dev->resume_state;
  2204. dev->resume_state = 0;
  2205. /* exit PHY low power suspend */
  2206. if (dev->pdev->device != 0x0829)
  2207. langwell_phy_low_power(dev, 0);
  2208. /* report resume to the driver */
  2209. if (dev->driver) {
  2210. if (dev->driver->resume) {
  2211. spin_unlock(&dev->lock);
  2212. dev->driver->resume(&dev->gadget);
  2213. spin_lock(&dev->lock);
  2214. dev_dbg(&dev->pdev->dev, "resume %s\n",
  2215. dev->driver->driver.name);
  2216. }
  2217. }
  2218. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2219. }
  2220. /* USB device controller interrupt handler */
  2221. static irqreturn_t langwell_irq(int irq, void *_dev)
  2222. {
  2223. struct langwell_udc *dev = _dev;
  2224. u32 usbsts,
  2225. usbintr,
  2226. irq_sts,
  2227. portsc1;
  2228. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2229. if (dev->stopped) {
  2230. dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
  2231. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2232. return IRQ_NONE;
  2233. }
  2234. spin_lock(&dev->lock);
  2235. /* USB status */
  2236. usbsts = readl(&dev->op_regs->usbsts);
  2237. /* USB interrupt enable */
  2238. usbintr = readl(&dev->op_regs->usbintr);
  2239. irq_sts = usbsts & usbintr;
  2240. dev_vdbg(&dev->pdev->dev,
  2241. "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n",
  2242. usbsts, usbintr, irq_sts);
  2243. if (!irq_sts) {
  2244. dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
  2245. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2246. spin_unlock(&dev->lock);
  2247. return IRQ_NONE;
  2248. }
  2249. /* Write-Clear interrupt status bits */
  2250. writel(irq_sts, &dev->op_regs->usbsts);
  2251. /* resume from suspend */
  2252. portsc1 = readl(&dev->op_regs->portsc1);
  2253. if (dev->usb_state == USB_STATE_SUSPENDED)
  2254. if (!(portsc1 & PORTS_SUSP))
  2255. handle_bus_resume(dev);
  2256. /* USB interrupt */
  2257. if (irq_sts & STS_UI) {
  2258. dev_vdbg(&dev->pdev->dev, "USB interrupt\n");
  2259. /* setup packet received from ep0 */
  2260. if (readl(&dev->op_regs->endptsetupstat)
  2261. & EP0SETUPSTAT_MASK) {
  2262. dev_vdbg(&dev->pdev->dev,
  2263. "USB SETUP packet received interrupt\n");
  2264. /* setup tripwire semaphone */
  2265. setup_tripwire(dev);
  2266. handle_setup_packet(dev, &dev->local_setup_buff);
  2267. }
  2268. /* USB transfer completion */
  2269. if (readl(&dev->op_regs->endptcomplete)) {
  2270. dev_vdbg(&dev->pdev->dev,
  2271. "USB transfer completion interrupt\n");
  2272. handle_trans_complete(dev);
  2273. }
  2274. }
  2275. /* SOF received interrupt (for ISO transfer) */
  2276. if (irq_sts & STS_SRI) {
  2277. /* FIXME */
  2278. /* dev_vdbg(&dev->pdev->dev, "SOF received interrupt\n"); */
  2279. }
  2280. /* port change detect interrupt */
  2281. if (irq_sts & STS_PCI) {
  2282. dev_vdbg(&dev->pdev->dev, "port change detect interrupt\n");
  2283. handle_port_change(dev);
  2284. }
  2285. /* suspend interrupt */
  2286. if (irq_sts & STS_SLI) {
  2287. dev_vdbg(&dev->pdev->dev, "suspend interrupt\n");
  2288. handle_bus_suspend(dev);
  2289. }
  2290. /* USB reset interrupt */
  2291. if (irq_sts & STS_URI) {
  2292. dev_vdbg(&dev->pdev->dev, "USB reset interrupt\n");
  2293. handle_usb_reset(dev);
  2294. }
  2295. /* USB error or system error interrupt */
  2296. if (irq_sts & (STS_UEI | STS_SEI)) {
  2297. /* FIXME */
  2298. dev_warn(&dev->pdev->dev, "error IRQ, irq_sts: %x\n", irq_sts);
  2299. }
  2300. spin_unlock(&dev->lock);
  2301. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2302. return IRQ_HANDLED;
  2303. }
  2304. /*-------------------------------------------------------------------------*/
  2305. /* release device structure */
  2306. static void gadget_release(struct device *_dev)
  2307. {
  2308. struct langwell_udc *dev = dev_get_drvdata(_dev);
  2309. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2310. complete(dev->done);
  2311. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2312. kfree(dev);
  2313. }
  2314. /* enable SRAM caching if SRAM detected */
  2315. static void sram_init(struct langwell_udc *dev)
  2316. {
  2317. struct pci_dev *pdev = dev->pdev;
  2318. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2319. dev->sram_addr = pci_resource_start(pdev, 1);
  2320. dev->sram_size = pci_resource_len(pdev, 1);
  2321. dev_info(&dev->pdev->dev, "Found private SRAM at %x size:%x\n",
  2322. dev->sram_addr, dev->sram_size);
  2323. dev->got_sram = 1;
  2324. if (pci_request_region(pdev, 1, kobject_name(&pdev->dev.kobj))) {
  2325. dev_warn(&dev->pdev->dev, "SRAM request failed\n");
  2326. dev->got_sram = 0;
  2327. } else if (!dma_declare_coherent_memory(&pdev->dev, dev->sram_addr,
  2328. dev->sram_addr, dev->sram_size, DMA_MEMORY_MAP)) {
  2329. dev_warn(&dev->pdev->dev, "SRAM DMA declare failed\n");
  2330. pci_release_region(pdev, 1);
  2331. dev->got_sram = 0;
  2332. }
  2333. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2334. }
  2335. /* release SRAM caching */
  2336. static void sram_deinit(struct langwell_udc *dev)
  2337. {
  2338. struct pci_dev *pdev = dev->pdev;
  2339. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2340. dma_release_declared_memory(&pdev->dev);
  2341. pci_release_region(pdev, 1);
  2342. dev->got_sram = 0;
  2343. dev_info(&dev->pdev->dev, "release SRAM caching\n");
  2344. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2345. }
  2346. /* tear down the binding between this driver and the pci device */
  2347. static void langwell_udc_remove(struct pci_dev *pdev)
  2348. {
  2349. struct langwell_udc *dev = pci_get_drvdata(pdev);
  2350. DECLARE_COMPLETION(done);
  2351. BUG_ON(dev->driver);
  2352. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2353. dev->done = &done;
  2354. /* free dTD dma_pool and dQH */
  2355. if (dev->dtd_pool)
  2356. dma_pool_destroy(dev->dtd_pool);
  2357. if (dev->ep_dqh)
  2358. dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
  2359. dev->ep_dqh, dev->ep_dqh_dma);
  2360. /* release SRAM caching */
  2361. if (dev->has_sram && dev->got_sram)
  2362. sram_deinit(dev);
  2363. if (dev->status_req) {
  2364. kfree(dev->status_req->req.buf);
  2365. kfree(dev->status_req);
  2366. }
  2367. kfree(dev->ep);
  2368. /* disable IRQ handler */
  2369. if (dev->got_irq)
  2370. free_irq(pdev->irq, dev);
  2371. if (dev->cap_regs)
  2372. iounmap(dev->cap_regs);
  2373. if (dev->region)
  2374. release_mem_region(pci_resource_start(pdev, 0),
  2375. pci_resource_len(pdev, 0));
  2376. if (dev->enabled)
  2377. pci_disable_device(pdev);
  2378. dev->cap_regs = NULL;
  2379. dev_info(&dev->pdev->dev, "unbind\n");
  2380. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2381. device_unregister(&dev->gadget.dev);
  2382. device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
  2383. device_remove_file(&pdev->dev, &dev_attr_remote_wakeup);
  2384. pci_set_drvdata(pdev, NULL);
  2385. /* free dev, wait for the release() finished */
  2386. wait_for_completion(&done);
  2387. }
  2388. /*
  2389. * wrap this driver around the specified device, but
  2390. * don't respond over USB until a gadget driver binds to us.
  2391. */
  2392. static int langwell_udc_probe(struct pci_dev *pdev,
  2393. const struct pci_device_id *id)
  2394. {
  2395. struct langwell_udc *dev;
  2396. unsigned long resource, len;
  2397. void __iomem *base = NULL;
  2398. size_t size;
  2399. int retval;
  2400. /* alloc, and start init */
  2401. dev = kzalloc(sizeof *dev, GFP_KERNEL);
  2402. if (dev == NULL) {
  2403. retval = -ENOMEM;
  2404. goto error;
  2405. }
  2406. /* initialize device spinlock */
  2407. spin_lock_init(&dev->lock);
  2408. dev->pdev = pdev;
  2409. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2410. pci_set_drvdata(pdev, dev);
  2411. /* now all the pci goodies ... */
  2412. if (pci_enable_device(pdev) < 0) {
  2413. retval = -ENODEV;
  2414. goto error;
  2415. }
  2416. dev->enabled = 1;
  2417. /* control register: BAR 0 */
  2418. resource = pci_resource_start(pdev, 0);
  2419. len = pci_resource_len(pdev, 0);
  2420. if (!request_mem_region(resource, len, driver_name)) {
  2421. dev_err(&dev->pdev->dev, "controller already in use\n");
  2422. retval = -EBUSY;
  2423. goto error;
  2424. }
  2425. dev->region = 1;
  2426. base = ioremap_nocache(resource, len);
  2427. if (base == NULL) {
  2428. dev_err(&dev->pdev->dev, "can't map memory\n");
  2429. retval = -EFAULT;
  2430. goto error;
  2431. }
  2432. dev->cap_regs = (struct langwell_cap_regs __iomem *) base;
  2433. dev_vdbg(&dev->pdev->dev, "dev->cap_regs: %pK\n", dev->cap_regs);
  2434. dev->op_regs = (struct langwell_op_regs __iomem *)
  2435. (base + OP_REG_OFFSET);
  2436. dev_vdbg(&dev->pdev->dev, "dev->op_regs: %pK\n", dev->op_regs);
  2437. /* irq setup after old hardware is cleaned up */
  2438. if (!pdev->irq) {
  2439. dev_err(&dev->pdev->dev, "No IRQ. Check PCI setup!\n");
  2440. retval = -ENODEV;
  2441. goto error;
  2442. }
  2443. dev->has_sram = 1;
  2444. dev->got_sram = 0;
  2445. dev_vdbg(&dev->pdev->dev, "dev->has_sram: %d\n", dev->has_sram);
  2446. /* enable SRAM caching if detected */
  2447. if (dev->has_sram && !dev->got_sram)
  2448. sram_init(dev);
  2449. dev_info(&dev->pdev->dev,
  2450. "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%pK\n",
  2451. pdev->irq, resource, len, base);
  2452. /* enables bus-mastering for device dev */
  2453. pci_set_master(pdev);
  2454. if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
  2455. driver_name, dev) != 0) {
  2456. dev_err(&dev->pdev->dev,
  2457. "request interrupt %d failed\n", pdev->irq);
  2458. retval = -EBUSY;
  2459. goto error;
  2460. }
  2461. dev->got_irq = 1;
  2462. /* set stopped bit */
  2463. dev->stopped = 1;
  2464. /* capabilities and endpoint number */
  2465. dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0;
  2466. dev->dciversion = readw(&dev->cap_regs->dciversion);
  2467. dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0;
  2468. dev_vdbg(&dev->pdev->dev, "dev->lpm: %d\n", dev->lpm);
  2469. dev_vdbg(&dev->pdev->dev, "dev->dciversion: 0x%04x\n",
  2470. dev->dciversion);
  2471. dev_vdbg(&dev->pdev->dev, "dccparams: 0x%08x\n",
  2472. readl(&dev->cap_regs->dccparams));
  2473. dev_vdbg(&dev->pdev->dev, "dev->devcap: %d\n", dev->devcap);
  2474. if (!dev->devcap) {
  2475. dev_err(&dev->pdev->dev, "can't support device mode\n");
  2476. retval = -ENODEV;
  2477. goto error;
  2478. }
  2479. /* a pair of endpoints (out/in) for each address */
  2480. dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2;
  2481. dev_vdbg(&dev->pdev->dev, "dev->ep_max: %d\n", dev->ep_max);
  2482. /* allocate endpoints memory */
  2483. dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max,
  2484. GFP_KERNEL);
  2485. if (!dev->ep) {
  2486. dev_err(&dev->pdev->dev, "allocate endpoints memory failed\n");
  2487. retval = -ENOMEM;
  2488. goto error;
  2489. }
  2490. /* allocate device dQH memory */
  2491. size = dev->ep_max * sizeof(struct langwell_dqh);
  2492. dev_vdbg(&dev->pdev->dev, "orig size = %zd\n", size);
  2493. if (size < DQH_ALIGNMENT)
  2494. size = DQH_ALIGNMENT;
  2495. else if ((size % DQH_ALIGNMENT) != 0) {
  2496. size += DQH_ALIGNMENT + 1;
  2497. size &= ~(DQH_ALIGNMENT - 1);
  2498. }
  2499. dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
  2500. &dev->ep_dqh_dma, GFP_KERNEL);
  2501. if (!dev->ep_dqh) {
  2502. dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
  2503. retval = -ENOMEM;
  2504. goto error;
  2505. }
  2506. dev->ep_dqh_size = size;
  2507. dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %zd\n", dev->ep_dqh_size);
  2508. /* initialize ep0 status request structure */
  2509. dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL);
  2510. if (!dev->status_req) {
  2511. dev_err(&dev->pdev->dev,
  2512. "allocate status_req memory failed\n");
  2513. retval = -ENOMEM;
  2514. goto error;
  2515. }
  2516. INIT_LIST_HEAD(&dev->status_req->queue);
  2517. /* allocate a small amount of memory to get valid address */
  2518. dev->status_req->req.buf = kmalloc(8, GFP_KERNEL);
  2519. dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf);
  2520. dev->resume_state = USB_STATE_NOTATTACHED;
  2521. dev->usb_state = USB_STATE_POWERED;
  2522. dev->ep0_dir = USB_DIR_OUT;
  2523. /* remote wakeup reset to 0 when the device is reset */
  2524. dev->remote_wakeup = 0;
  2525. dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
  2526. /* reset device controller */
  2527. langwell_udc_reset(dev);
  2528. /* initialize gadget structure */
  2529. dev->gadget.ops = &langwell_ops; /* usb_gadget_ops */
  2530. dev->gadget.ep0 = &dev->ep[0].ep; /* gadget ep0 */
  2531. INIT_LIST_HEAD(&dev->gadget.ep_list); /* ep_list */
  2532. dev->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
  2533. dev->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
  2534. /* the "gadget" abstracts/virtualizes the controller */
  2535. dev_set_name(&dev->gadget.dev, "gadget");
  2536. dev->gadget.dev.parent = &pdev->dev;
  2537. dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
  2538. dev->gadget.dev.release = gadget_release;
  2539. dev->gadget.name = driver_name; /* gadget name */
  2540. /* controller endpoints reinit */
  2541. eps_reinit(dev);
  2542. /* reset ep0 dQH and endptctrl */
  2543. ep0_reset(dev);
  2544. /* create dTD dma_pool resource */
  2545. dev->dtd_pool = dma_pool_create("langwell_dtd",
  2546. &dev->pdev->dev,
  2547. sizeof(struct langwell_dtd),
  2548. DTD_ALIGNMENT,
  2549. DMA_BOUNDARY);
  2550. if (!dev->dtd_pool) {
  2551. retval = -ENOMEM;
  2552. goto error;
  2553. }
  2554. /* done */
  2555. dev_info(&dev->pdev->dev, "%s\n", driver_desc);
  2556. dev_info(&dev->pdev->dev, "irq %d, pci mem %pK\n", pdev->irq, base);
  2557. dev_info(&dev->pdev->dev, "Driver version: " DRIVER_VERSION "\n");
  2558. dev_info(&dev->pdev->dev, "Support (max) %d endpoints\n", dev->ep_max);
  2559. dev_info(&dev->pdev->dev, "Device interface version: 0x%04x\n",
  2560. dev->dciversion);
  2561. dev_info(&dev->pdev->dev, "Controller mode: %s\n",
  2562. dev->devcap ? "Device" : "Host");
  2563. dev_info(&dev->pdev->dev, "Support USB LPM: %s\n",
  2564. dev->lpm ? "Yes" : "No");
  2565. dev_vdbg(&dev->pdev->dev,
  2566. "After langwell_udc_probe(), print all registers:\n");
  2567. print_all_registers(dev);
  2568. retval = device_register(&dev->gadget.dev);
  2569. if (retval)
  2570. goto error;
  2571. retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
  2572. if (retval)
  2573. goto error;
  2574. retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc);
  2575. if (retval)
  2576. goto error;
  2577. retval = device_create_file(&pdev->dev, &dev_attr_remote_wakeup);
  2578. if (retval)
  2579. goto error_attr1;
  2580. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2581. return 0;
  2582. error_attr1:
  2583. device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
  2584. error:
  2585. if (dev) {
  2586. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2587. langwell_udc_remove(pdev);
  2588. }
  2589. return retval;
  2590. }
  2591. /* device controller suspend */
  2592. static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
  2593. {
  2594. struct langwell_udc *dev = pci_get_drvdata(pdev);
  2595. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2596. usb_del_gadget_udc(&dev->gadget);
  2597. /* disable interrupt and set controller to stop state */
  2598. langwell_udc_stop(dev);
  2599. /* disable IRQ handler */
  2600. if (dev->got_irq)
  2601. free_irq(pdev->irq, dev);
  2602. dev->got_irq = 0;
  2603. /* save PCI state */
  2604. pci_save_state(pdev);
  2605. spin_lock_irq(&dev->lock);
  2606. /* stop all usb activities */
  2607. stop_activity(dev);
  2608. spin_unlock_irq(&dev->lock);
  2609. /* free dTD dma_pool and dQH */
  2610. if (dev->dtd_pool)
  2611. dma_pool_destroy(dev->dtd_pool);
  2612. if (dev->ep_dqh)
  2613. dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
  2614. dev->ep_dqh, dev->ep_dqh_dma);
  2615. /* release SRAM caching */
  2616. if (dev->has_sram && dev->got_sram)
  2617. sram_deinit(dev);
  2618. /* set device power state */
  2619. pci_set_power_state(pdev, PCI_D3hot);
  2620. /* enter PHY low power suspend */
  2621. if (dev->pdev->device != 0x0829)
  2622. langwell_phy_low_power(dev, 1);
  2623. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2624. return 0;
  2625. }
  2626. /* device controller resume */
  2627. static int langwell_udc_resume(struct pci_dev *pdev)
  2628. {
  2629. struct langwell_udc *dev = pci_get_drvdata(pdev);
  2630. size_t size;
  2631. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2632. /* exit PHY low power suspend */
  2633. if (dev->pdev->device != 0x0829)
  2634. langwell_phy_low_power(dev, 0);
  2635. /* set device D0 power state */
  2636. pci_set_power_state(pdev, PCI_D0);
  2637. /* enable SRAM caching if detected */
  2638. if (dev->has_sram && !dev->got_sram)
  2639. sram_init(dev);
  2640. /* allocate device dQH memory */
  2641. size = dev->ep_max * sizeof(struct langwell_dqh);
  2642. dev_vdbg(&dev->pdev->dev, "orig size = %zd\n", size);
  2643. if (size < DQH_ALIGNMENT)
  2644. size = DQH_ALIGNMENT;
  2645. else if ((size % DQH_ALIGNMENT) != 0) {
  2646. size += DQH_ALIGNMENT + 1;
  2647. size &= ~(DQH_ALIGNMENT - 1);
  2648. }
  2649. dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
  2650. &dev->ep_dqh_dma, GFP_KERNEL);
  2651. if (!dev->ep_dqh) {
  2652. dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
  2653. return -ENOMEM;
  2654. }
  2655. dev->ep_dqh_size = size;
  2656. dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %zd\n", dev->ep_dqh_size);
  2657. /* create dTD dma_pool resource */
  2658. dev->dtd_pool = dma_pool_create("langwell_dtd",
  2659. &dev->pdev->dev,
  2660. sizeof(struct langwell_dtd),
  2661. DTD_ALIGNMENT,
  2662. DMA_BOUNDARY);
  2663. if (!dev->dtd_pool)
  2664. return -ENOMEM;
  2665. /* restore PCI state */
  2666. pci_restore_state(pdev);
  2667. /* enable IRQ handler */
  2668. if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
  2669. driver_name, dev) != 0) {
  2670. dev_err(&dev->pdev->dev, "request interrupt %d failed\n",
  2671. pdev->irq);
  2672. return -EBUSY;
  2673. }
  2674. dev->got_irq = 1;
  2675. /* reset and start controller to run state */
  2676. if (dev->stopped) {
  2677. /* reset device controller */
  2678. langwell_udc_reset(dev);
  2679. /* reset ep0 dQH and endptctrl */
  2680. ep0_reset(dev);
  2681. /* start device if gadget is loaded */
  2682. if (dev->driver)
  2683. langwell_udc_start(dev);
  2684. }
  2685. /* reset USB status */
  2686. dev->usb_state = USB_STATE_ATTACHED;
  2687. dev->ep0_state = WAIT_FOR_SETUP;
  2688. dev->ep0_dir = USB_DIR_OUT;
  2689. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2690. return 0;
  2691. }
  2692. /* pci driver shutdown */
  2693. static void langwell_udc_shutdown(struct pci_dev *pdev)
  2694. {
  2695. struct langwell_udc *dev = pci_get_drvdata(pdev);
  2696. u32 usbmode;
  2697. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2698. /* reset controller mode to IDLE */
  2699. usbmode = readl(&dev->op_regs->usbmode);
  2700. dev_dbg(&dev->pdev->dev, "usbmode = 0x%08x\n", usbmode);
  2701. usbmode &= (~3 | MODE_IDLE);
  2702. writel(usbmode, &dev->op_regs->usbmode);
  2703. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2704. }
  2705. /*-------------------------------------------------------------------------*/
  2706. static const struct pci_device_id pci_ids[] = { {
  2707. .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
  2708. .class_mask = ~0,
  2709. .vendor = 0x8086,
  2710. .device = 0x0811,
  2711. .subvendor = PCI_ANY_ID,
  2712. .subdevice = PCI_ANY_ID,
  2713. }, { /* end: all zeroes */ }
  2714. };
  2715. MODULE_DEVICE_TABLE(pci, pci_ids);
  2716. static struct pci_driver langwell_pci_driver = {
  2717. .name = (char *) driver_name,
  2718. .id_table = pci_ids,
  2719. .probe = langwell_udc_probe,
  2720. .remove = langwell_udc_remove,
  2721. /* device controller suspend/resume */
  2722. .suspend = langwell_udc_suspend,
  2723. .resume = langwell_udc_resume,
  2724. .shutdown = langwell_udc_shutdown,
  2725. };
  2726. static int __init init(void)
  2727. {
  2728. return pci_register_driver(&langwell_pci_driver);
  2729. }
  2730. module_init(init);
  2731. static void __exit cleanup(void)
  2732. {
  2733. pci_unregister_driver(&langwell_pci_driver);
  2734. }
  2735. module_exit(cleanup);
  2736. MODULE_DESCRIPTION(DRIVER_DESC);
  2737. MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>");
  2738. MODULE_VERSION(DRIVER_VERSION);
  2739. MODULE_LICENSE("GPL");