sc26xx.c 16 KB

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  1. /*
  2. * SC268xx.c: Serial driver for Philiphs SC2681/SC2692 devices.
  3. *
  4. * Copyright (C) 2006,2007 Thomas Bogendörfer (tsbogend@alpha.franken.de)
  5. */
  6. #include <linux/module.h>
  7. #include <linux/kernel.h>
  8. #include <linux/errno.h>
  9. #include <linux/tty.h>
  10. #include <linux/tty_flip.h>
  11. #include <linux/major.h>
  12. #include <linux/circ_buf.h>
  13. #include <linux/serial.h>
  14. #include <linux/sysrq.h>
  15. #include <linux/console.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/slab.h>
  18. #include <linux/delay.h>
  19. #include <linux/init.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/irq.h>
  22. #if defined(CONFIG_MAGIC_SYSRQ)
  23. #define SUPPORT_SYSRQ
  24. #endif
  25. #include <linux/serial_core.h>
  26. #define SC26XX_MAJOR 204
  27. #define SC26XX_MINOR_START 205
  28. #define SC26XX_NR 2
  29. struct uart_sc26xx_port {
  30. struct uart_port port[2];
  31. u8 dsr_mask[2];
  32. u8 cts_mask[2];
  33. u8 dcd_mask[2];
  34. u8 ri_mask[2];
  35. u8 dtr_mask[2];
  36. u8 rts_mask[2];
  37. u8 imr;
  38. };
  39. /* register common to both ports */
  40. #define RD_ISR 0x14
  41. #define RD_IPR 0x34
  42. #define WR_ACR 0x10
  43. #define WR_IMR 0x14
  44. #define WR_OPCR 0x34
  45. #define WR_OPR_SET 0x38
  46. #define WR_OPR_CLR 0x3C
  47. /* access common register */
  48. #define READ_SC(p, r) readb((p)->membase + RD_##r)
  49. #define WRITE_SC(p, r, v) writeb((v), (p)->membase + WR_##r)
  50. /* register per port */
  51. #define RD_PORT_MRx 0x00
  52. #define RD_PORT_SR 0x04
  53. #define RD_PORT_RHR 0x0c
  54. #define WR_PORT_MRx 0x00
  55. #define WR_PORT_CSR 0x04
  56. #define WR_PORT_CR 0x08
  57. #define WR_PORT_THR 0x0c
  58. /* SR bits */
  59. #define SR_BREAK (1 << 7)
  60. #define SR_FRAME (1 << 6)
  61. #define SR_PARITY (1 << 5)
  62. #define SR_OVERRUN (1 << 4)
  63. #define SR_TXRDY (1 << 2)
  64. #define SR_RXRDY (1 << 0)
  65. #define CR_RES_MR (1 << 4)
  66. #define CR_RES_RX (2 << 4)
  67. #define CR_RES_TX (3 << 4)
  68. #define CR_STRT_BRK (6 << 4)
  69. #define CR_STOP_BRK (7 << 4)
  70. #define CR_DIS_TX (1 << 3)
  71. #define CR_ENA_TX (1 << 2)
  72. #define CR_DIS_RX (1 << 1)
  73. #define CR_ENA_RX (1 << 0)
  74. /* ISR bits */
  75. #define ISR_RXRDYB (1 << 5)
  76. #define ISR_TXRDYB (1 << 4)
  77. #define ISR_RXRDYA (1 << 1)
  78. #define ISR_TXRDYA (1 << 0)
  79. /* IMR bits */
  80. #define IMR_RXRDY (1 << 1)
  81. #define IMR_TXRDY (1 << 0)
  82. /* access port register */
  83. static inline u8 read_sc_port(struct uart_port *p, u8 reg)
  84. {
  85. return readb(p->membase + p->line * 0x20 + reg);
  86. }
  87. static inline void write_sc_port(struct uart_port *p, u8 reg, u8 val)
  88. {
  89. writeb(val, p->membase + p->line * 0x20 + reg);
  90. }
  91. #define READ_SC_PORT(p, r) read_sc_port(p, RD_PORT_##r)
  92. #define WRITE_SC_PORT(p, r, v) write_sc_port(p, WR_PORT_##r, v)
  93. static void sc26xx_enable_irq(struct uart_port *port, int mask)
  94. {
  95. struct uart_sc26xx_port *up;
  96. int line = port->line;
  97. port -= line;
  98. up = container_of(port, struct uart_sc26xx_port, port[0]);
  99. up->imr |= mask << (line * 4);
  100. WRITE_SC(port, IMR, up->imr);
  101. }
  102. static void sc26xx_disable_irq(struct uart_port *port, int mask)
  103. {
  104. struct uart_sc26xx_port *up;
  105. int line = port->line;
  106. port -= line;
  107. up = container_of(port, struct uart_sc26xx_port, port[0]);
  108. up->imr &= ~(mask << (line * 4));
  109. WRITE_SC(port, IMR, up->imr);
  110. }
  111. static struct tty_struct *receive_chars(struct uart_port *port)
  112. {
  113. struct tty_struct *tty = NULL;
  114. int limit = 10000;
  115. unsigned char ch;
  116. char flag;
  117. u8 status;
  118. if (port->state != NULL) /* Unopened serial console */
  119. tty = port->state->port.tty;
  120. while (limit-- > 0) {
  121. status = READ_SC_PORT(port, SR);
  122. if (!(status & SR_RXRDY))
  123. break;
  124. ch = READ_SC_PORT(port, RHR);
  125. flag = TTY_NORMAL;
  126. port->icount.rx++;
  127. if (unlikely(status & (SR_BREAK | SR_FRAME |
  128. SR_PARITY | SR_OVERRUN))) {
  129. if (status & SR_BREAK) {
  130. status &= ~(SR_PARITY | SR_FRAME);
  131. port->icount.brk++;
  132. if (uart_handle_break(port))
  133. continue;
  134. } else if (status & SR_PARITY)
  135. port->icount.parity++;
  136. else if (status & SR_FRAME)
  137. port->icount.frame++;
  138. if (status & SR_OVERRUN)
  139. port->icount.overrun++;
  140. status &= port->read_status_mask;
  141. if (status & SR_BREAK)
  142. flag = TTY_BREAK;
  143. else if (status & SR_PARITY)
  144. flag = TTY_PARITY;
  145. else if (status & SR_FRAME)
  146. flag = TTY_FRAME;
  147. }
  148. if (uart_handle_sysrq_char(port, ch))
  149. continue;
  150. if (status & port->ignore_status_mask)
  151. continue;
  152. tty_insert_flip_char(tty, ch, flag);
  153. }
  154. return tty;
  155. }
  156. static void transmit_chars(struct uart_port *port)
  157. {
  158. struct circ_buf *xmit;
  159. if (!port->state)
  160. return;
  161. xmit = &port->state->xmit;
  162. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  163. sc26xx_disable_irq(port, IMR_TXRDY);
  164. return;
  165. }
  166. while (!uart_circ_empty(xmit)) {
  167. if (!(READ_SC_PORT(port, SR) & SR_TXRDY))
  168. break;
  169. WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
  170. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  171. port->icount.tx++;
  172. }
  173. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  174. uart_write_wakeup(port);
  175. }
  176. static irqreturn_t sc26xx_interrupt(int irq, void *dev_id)
  177. {
  178. struct uart_sc26xx_port *up = dev_id;
  179. struct tty_struct *tty;
  180. unsigned long flags;
  181. u8 isr;
  182. spin_lock_irqsave(&up->port[0].lock, flags);
  183. tty = NULL;
  184. isr = READ_SC(&up->port[0], ISR);
  185. if (isr & ISR_TXRDYA)
  186. transmit_chars(&up->port[0]);
  187. if (isr & ISR_RXRDYA)
  188. tty = receive_chars(&up->port[0]);
  189. spin_unlock(&up->port[0].lock);
  190. if (tty)
  191. tty_flip_buffer_push(tty);
  192. spin_lock(&up->port[1].lock);
  193. tty = NULL;
  194. if (isr & ISR_TXRDYB)
  195. transmit_chars(&up->port[1]);
  196. if (isr & ISR_RXRDYB)
  197. tty = receive_chars(&up->port[1]);
  198. spin_unlock_irqrestore(&up->port[1].lock, flags);
  199. if (tty)
  200. tty_flip_buffer_push(tty);
  201. return IRQ_HANDLED;
  202. }
  203. /* port->lock is not held. */
  204. static unsigned int sc26xx_tx_empty(struct uart_port *port)
  205. {
  206. return (READ_SC_PORT(port, SR) & SR_TXRDY) ? TIOCSER_TEMT : 0;
  207. }
  208. /* port->lock held by caller. */
  209. static void sc26xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
  210. {
  211. struct uart_sc26xx_port *up;
  212. int line = port->line;
  213. port -= line;
  214. up = container_of(port, struct uart_sc26xx_port, port[0]);
  215. if (up->dtr_mask[line]) {
  216. if (mctrl & TIOCM_DTR)
  217. WRITE_SC(port, OPR_SET, up->dtr_mask[line]);
  218. else
  219. WRITE_SC(port, OPR_CLR, up->dtr_mask[line]);
  220. }
  221. if (up->rts_mask[line]) {
  222. if (mctrl & TIOCM_RTS)
  223. WRITE_SC(port, OPR_SET, up->rts_mask[line]);
  224. else
  225. WRITE_SC(port, OPR_CLR, up->rts_mask[line]);
  226. }
  227. }
  228. /* port->lock is held by caller and interrupts are disabled. */
  229. static unsigned int sc26xx_get_mctrl(struct uart_port *port)
  230. {
  231. struct uart_sc26xx_port *up;
  232. int line = port->line;
  233. unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
  234. u8 ipr;
  235. port -= line;
  236. up = container_of(port, struct uart_sc26xx_port, port[0]);
  237. ipr = READ_SC(port, IPR) ^ 0xff;
  238. if (up->dsr_mask[line]) {
  239. mctrl &= ~TIOCM_DSR;
  240. mctrl |= ipr & up->dsr_mask[line] ? TIOCM_DSR : 0;
  241. }
  242. if (up->cts_mask[line]) {
  243. mctrl &= ~TIOCM_CTS;
  244. mctrl |= ipr & up->cts_mask[line] ? TIOCM_CTS : 0;
  245. }
  246. if (up->dcd_mask[line]) {
  247. mctrl &= ~TIOCM_CAR;
  248. mctrl |= ipr & up->dcd_mask[line] ? TIOCM_CAR : 0;
  249. }
  250. if (up->ri_mask[line]) {
  251. mctrl &= ~TIOCM_RNG;
  252. mctrl |= ipr & up->ri_mask[line] ? TIOCM_RNG : 0;
  253. }
  254. return mctrl;
  255. }
  256. /* port->lock held by caller. */
  257. static void sc26xx_stop_tx(struct uart_port *port)
  258. {
  259. return;
  260. }
  261. /* port->lock held by caller. */
  262. static void sc26xx_start_tx(struct uart_port *port)
  263. {
  264. struct circ_buf *xmit = &port->state->xmit;
  265. while (!uart_circ_empty(xmit)) {
  266. if (!(READ_SC_PORT(port, SR) & SR_TXRDY)) {
  267. sc26xx_enable_irq(port, IMR_TXRDY);
  268. break;
  269. }
  270. WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
  271. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  272. port->icount.tx++;
  273. }
  274. }
  275. /* port->lock held by caller. */
  276. static void sc26xx_stop_rx(struct uart_port *port)
  277. {
  278. }
  279. /* port->lock held by caller. */
  280. static void sc26xx_enable_ms(struct uart_port *port)
  281. {
  282. }
  283. /* port->lock is not held. */
  284. static void sc26xx_break_ctl(struct uart_port *port, int break_state)
  285. {
  286. if (break_state == -1)
  287. WRITE_SC_PORT(port, CR, CR_STRT_BRK);
  288. else
  289. WRITE_SC_PORT(port, CR, CR_STOP_BRK);
  290. }
  291. /* port->lock is not held. */
  292. static int sc26xx_startup(struct uart_port *port)
  293. {
  294. sc26xx_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
  295. WRITE_SC(port, OPCR, 0);
  296. /* reset tx and rx */
  297. WRITE_SC_PORT(port, CR, CR_RES_RX);
  298. WRITE_SC_PORT(port, CR, CR_RES_TX);
  299. /* start rx/tx */
  300. WRITE_SC_PORT(port, CR, CR_ENA_TX | CR_ENA_RX);
  301. /* enable irqs */
  302. sc26xx_enable_irq(port, IMR_RXRDY);
  303. return 0;
  304. }
  305. /* port->lock is not held. */
  306. static void sc26xx_shutdown(struct uart_port *port)
  307. {
  308. /* disable interrupst */
  309. sc26xx_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
  310. /* stop tx/rx */
  311. WRITE_SC_PORT(port, CR, CR_DIS_TX | CR_DIS_RX);
  312. }
  313. /* port->lock is not held. */
  314. static void sc26xx_set_termios(struct uart_port *port, struct ktermios *termios,
  315. struct ktermios *old)
  316. {
  317. unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
  318. unsigned int quot = uart_get_divisor(port, baud);
  319. unsigned int iflag, cflag;
  320. unsigned long flags;
  321. u8 mr1, mr2, csr;
  322. spin_lock_irqsave(&port->lock, flags);
  323. while ((READ_SC_PORT(port, SR) & ((1 << 3) | (1 << 2))) != 0xc)
  324. udelay(2);
  325. WRITE_SC_PORT(port, CR, CR_DIS_TX | CR_DIS_RX);
  326. iflag = termios->c_iflag;
  327. cflag = termios->c_cflag;
  328. port->read_status_mask = SR_OVERRUN;
  329. if (iflag & INPCK)
  330. port->read_status_mask |= SR_PARITY | SR_FRAME;
  331. if (iflag & (BRKINT | PARMRK))
  332. port->read_status_mask |= SR_BREAK;
  333. port->ignore_status_mask = 0;
  334. if (iflag & IGNBRK)
  335. port->ignore_status_mask |= SR_BREAK;
  336. if ((cflag & CREAD) == 0)
  337. port->ignore_status_mask |= SR_BREAK | SR_FRAME |
  338. SR_PARITY | SR_OVERRUN;
  339. switch (cflag & CSIZE) {
  340. case CS5:
  341. mr1 = 0x00;
  342. break;
  343. case CS6:
  344. mr1 = 0x01;
  345. break;
  346. case CS7:
  347. mr1 = 0x02;
  348. break;
  349. default:
  350. case CS8:
  351. mr1 = 0x03;
  352. break;
  353. }
  354. mr2 = 0x07;
  355. if (cflag & CSTOPB)
  356. mr2 = 0x0f;
  357. if (cflag & PARENB) {
  358. if (cflag & PARODD)
  359. mr1 |= (1 << 2);
  360. } else
  361. mr1 |= (2 << 3);
  362. switch (baud) {
  363. case 50:
  364. csr = 0x00;
  365. break;
  366. case 110:
  367. csr = 0x11;
  368. break;
  369. case 134:
  370. csr = 0x22;
  371. break;
  372. case 200:
  373. csr = 0x33;
  374. break;
  375. case 300:
  376. csr = 0x44;
  377. break;
  378. case 600:
  379. csr = 0x55;
  380. break;
  381. case 1200:
  382. csr = 0x66;
  383. break;
  384. case 2400:
  385. csr = 0x88;
  386. break;
  387. case 4800:
  388. csr = 0x99;
  389. break;
  390. default:
  391. case 9600:
  392. csr = 0xbb;
  393. break;
  394. case 19200:
  395. csr = 0xcc;
  396. break;
  397. }
  398. WRITE_SC_PORT(port, CR, CR_RES_MR);
  399. WRITE_SC_PORT(port, MRx, mr1);
  400. WRITE_SC_PORT(port, MRx, mr2);
  401. WRITE_SC(port, ACR, 0x80);
  402. WRITE_SC_PORT(port, CSR, csr);
  403. /* reset tx and rx */
  404. WRITE_SC_PORT(port, CR, CR_RES_RX);
  405. WRITE_SC_PORT(port, CR, CR_RES_TX);
  406. WRITE_SC_PORT(port, CR, CR_ENA_TX | CR_ENA_RX);
  407. while ((READ_SC_PORT(port, SR) & ((1 << 3) | (1 << 2))) != 0xc)
  408. udelay(2);
  409. /* XXX */
  410. uart_update_timeout(port, cflag,
  411. (port->uartclk / (16 * quot)));
  412. spin_unlock_irqrestore(&port->lock, flags);
  413. }
  414. static const char *sc26xx_type(struct uart_port *port)
  415. {
  416. return "SC26XX";
  417. }
  418. static void sc26xx_release_port(struct uart_port *port)
  419. {
  420. }
  421. static int sc26xx_request_port(struct uart_port *port)
  422. {
  423. return 0;
  424. }
  425. static void sc26xx_config_port(struct uart_port *port, int flags)
  426. {
  427. }
  428. static int sc26xx_verify_port(struct uart_port *port, struct serial_struct *ser)
  429. {
  430. return -EINVAL;
  431. }
  432. static struct uart_ops sc26xx_ops = {
  433. .tx_empty = sc26xx_tx_empty,
  434. .set_mctrl = sc26xx_set_mctrl,
  435. .get_mctrl = sc26xx_get_mctrl,
  436. .stop_tx = sc26xx_stop_tx,
  437. .start_tx = sc26xx_start_tx,
  438. .stop_rx = sc26xx_stop_rx,
  439. .enable_ms = sc26xx_enable_ms,
  440. .break_ctl = sc26xx_break_ctl,
  441. .startup = sc26xx_startup,
  442. .shutdown = sc26xx_shutdown,
  443. .set_termios = sc26xx_set_termios,
  444. .type = sc26xx_type,
  445. .release_port = sc26xx_release_port,
  446. .request_port = sc26xx_request_port,
  447. .config_port = sc26xx_config_port,
  448. .verify_port = sc26xx_verify_port,
  449. };
  450. static struct uart_port *sc26xx_port;
  451. #ifdef CONFIG_SERIAL_SC26XX_CONSOLE
  452. static void sc26xx_console_putchar(struct uart_port *port, char c)
  453. {
  454. unsigned long flags;
  455. int limit = 1000000;
  456. spin_lock_irqsave(&port->lock, flags);
  457. while (limit-- > 0) {
  458. if (READ_SC_PORT(port, SR) & SR_TXRDY) {
  459. WRITE_SC_PORT(port, THR, c);
  460. break;
  461. }
  462. udelay(2);
  463. }
  464. spin_unlock_irqrestore(&port->lock, flags);
  465. }
  466. static void sc26xx_console_write(struct console *con, const char *s, unsigned n)
  467. {
  468. struct uart_port *port = sc26xx_port;
  469. int i;
  470. for (i = 0; i < n; i++) {
  471. if (*s == '\n')
  472. sc26xx_console_putchar(port, '\r');
  473. sc26xx_console_putchar(port, *s++);
  474. }
  475. }
  476. static int __init sc26xx_console_setup(struct console *con, char *options)
  477. {
  478. struct uart_port *port = sc26xx_port;
  479. int baud = 9600;
  480. int bits = 8;
  481. int parity = 'n';
  482. int flow = 'n';
  483. if (port->type != PORT_SC26XX)
  484. return -1;
  485. printk(KERN_INFO "Console: ttySC%d (SC26XX)\n", con->index);
  486. if (options)
  487. uart_parse_options(options, &baud, &parity, &bits, &flow);
  488. return uart_set_options(port, con, baud, parity, bits, flow);
  489. }
  490. static struct uart_driver sc26xx_reg;
  491. static struct console sc26xx_console = {
  492. .name = "ttySC",
  493. .write = sc26xx_console_write,
  494. .device = uart_console_device,
  495. .setup = sc26xx_console_setup,
  496. .flags = CON_PRINTBUFFER,
  497. .index = -1,
  498. .data = &sc26xx_reg,
  499. };
  500. #define SC26XX_CONSOLE &sc26xx_console
  501. #else
  502. #define SC26XX_CONSOLE NULL
  503. #endif
  504. static struct uart_driver sc26xx_reg = {
  505. .owner = THIS_MODULE,
  506. .driver_name = "SC26xx",
  507. .dev_name = "ttySC",
  508. .major = SC26XX_MAJOR,
  509. .minor = SC26XX_MINOR_START,
  510. .nr = SC26XX_NR,
  511. .cons = SC26XX_CONSOLE,
  512. };
  513. static u8 sc26xx_flags2mask(unsigned int flags, unsigned int bitpos)
  514. {
  515. unsigned int bit = (flags >> bitpos) & 15;
  516. return bit ? (1 << (bit - 1)) : 0;
  517. }
  518. static void __devinit sc26xx_init_masks(struct uart_sc26xx_port *up,
  519. int line, unsigned int data)
  520. {
  521. up->dtr_mask[line] = sc26xx_flags2mask(data, 0);
  522. up->rts_mask[line] = sc26xx_flags2mask(data, 4);
  523. up->dsr_mask[line] = sc26xx_flags2mask(data, 8);
  524. up->cts_mask[line] = sc26xx_flags2mask(data, 12);
  525. up->dcd_mask[line] = sc26xx_flags2mask(data, 16);
  526. up->ri_mask[line] = sc26xx_flags2mask(data, 20);
  527. }
  528. static int __devinit sc26xx_probe(struct platform_device *dev)
  529. {
  530. struct resource *res;
  531. struct uart_sc26xx_port *up;
  532. unsigned int *sc26xx_data = dev->dev.platform_data;
  533. int err;
  534. res = platform_get_resource(dev, IORESOURCE_MEM, 0);
  535. if (!res)
  536. return -ENODEV;
  537. up = kzalloc(sizeof *up, GFP_KERNEL);
  538. if (unlikely(!up))
  539. return -ENOMEM;
  540. up->port[0].line = 0;
  541. up->port[0].ops = &sc26xx_ops;
  542. up->port[0].type = PORT_SC26XX;
  543. up->port[0].uartclk = (29491200 / 16); /* arbitrary */
  544. up->port[0].mapbase = res->start;
  545. up->port[0].membase = ioremap_nocache(up->port[0].mapbase, 0x40);
  546. up->port[0].iotype = UPIO_MEM;
  547. up->port[0].irq = platform_get_irq(dev, 0);
  548. up->port[0].dev = &dev->dev;
  549. sc26xx_init_masks(up, 0, sc26xx_data[0]);
  550. sc26xx_port = &up->port[0];
  551. up->port[1].line = 1;
  552. up->port[1].ops = &sc26xx_ops;
  553. up->port[1].type = PORT_SC26XX;
  554. up->port[1].uartclk = (29491200 / 16); /* arbitrary */
  555. up->port[1].mapbase = up->port[0].mapbase;
  556. up->port[1].membase = up->port[0].membase;
  557. up->port[1].iotype = UPIO_MEM;
  558. up->port[1].irq = up->port[0].irq;
  559. up->port[1].dev = &dev->dev;
  560. sc26xx_init_masks(up, 1, sc26xx_data[1]);
  561. err = uart_register_driver(&sc26xx_reg);
  562. if (err)
  563. goto out_free_port;
  564. sc26xx_reg.tty_driver->name_base = sc26xx_reg.minor;
  565. err = uart_add_one_port(&sc26xx_reg, &up->port[0]);
  566. if (err)
  567. goto out_unregister_driver;
  568. err = uart_add_one_port(&sc26xx_reg, &up->port[1]);
  569. if (err)
  570. goto out_remove_port0;
  571. err = request_irq(up->port[0].irq, sc26xx_interrupt, 0, "sc26xx", up);
  572. if (err)
  573. goto out_remove_ports;
  574. dev_set_drvdata(&dev->dev, up);
  575. return 0;
  576. out_remove_ports:
  577. uart_remove_one_port(&sc26xx_reg, &up->port[1]);
  578. out_remove_port0:
  579. uart_remove_one_port(&sc26xx_reg, &up->port[0]);
  580. out_unregister_driver:
  581. uart_unregister_driver(&sc26xx_reg);
  582. out_free_port:
  583. kfree(up);
  584. sc26xx_port = NULL;
  585. return err;
  586. }
  587. static int __exit sc26xx_driver_remove(struct platform_device *dev)
  588. {
  589. struct uart_sc26xx_port *up = dev_get_drvdata(&dev->dev);
  590. free_irq(up->port[0].irq, up);
  591. uart_remove_one_port(&sc26xx_reg, &up->port[0]);
  592. uart_remove_one_port(&sc26xx_reg, &up->port[1]);
  593. uart_unregister_driver(&sc26xx_reg);
  594. kfree(up);
  595. sc26xx_port = NULL;
  596. dev_set_drvdata(&dev->dev, NULL);
  597. return 0;
  598. }
  599. static struct platform_driver sc26xx_driver = {
  600. .probe = sc26xx_probe,
  601. .remove = __devexit_p(sc26xx_driver_remove),
  602. .driver = {
  603. .name = "SC26xx",
  604. .owner = THIS_MODULE,
  605. },
  606. };
  607. module_platform_driver(sc26xx_driver);
  608. MODULE_AUTHOR("Thomas Bogendörfer");
  609. MODULE_DESCRIPTION("SC681/SC2692 serial driver");
  610. MODULE_VERSION("1.0");
  611. MODULE_LICENSE("GPL");
  612. MODULE_ALIAS("platform:SC26xx");