spi-rspi.c 12 KB

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  1. /*
  2. * SH RSPI driver
  3. *
  4. * Copyright (C) 2012 Renesas Solutions Corp.
  5. *
  6. * Based on spi-sh.c:
  7. * Copyright (C) 2011 Renesas Solutions Corp.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  21. *
  22. */
  23. #include <linux/module.h>
  24. #include <linux/kernel.h>
  25. #include <linux/sched.h>
  26. #include <linux/errno.h>
  27. #include <linux/list.h>
  28. #include <linux/workqueue.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/io.h>
  32. #include <linux/clk.h>
  33. #include <linux/spi/spi.h>
  34. #define RSPI_SPCR 0x00
  35. #define RSPI_SSLP 0x01
  36. #define RSPI_SPPCR 0x02
  37. #define RSPI_SPSR 0x03
  38. #define RSPI_SPDR 0x04
  39. #define RSPI_SPSCR 0x08
  40. #define RSPI_SPSSR 0x09
  41. #define RSPI_SPBR 0x0a
  42. #define RSPI_SPDCR 0x0b
  43. #define RSPI_SPCKD 0x0c
  44. #define RSPI_SSLND 0x0d
  45. #define RSPI_SPND 0x0e
  46. #define RSPI_SPCR2 0x0f
  47. #define RSPI_SPCMD0 0x10
  48. #define RSPI_SPCMD1 0x12
  49. #define RSPI_SPCMD2 0x14
  50. #define RSPI_SPCMD3 0x16
  51. #define RSPI_SPCMD4 0x18
  52. #define RSPI_SPCMD5 0x1a
  53. #define RSPI_SPCMD6 0x1c
  54. #define RSPI_SPCMD7 0x1e
  55. /* SPCR */
  56. #define SPCR_SPRIE 0x80
  57. #define SPCR_SPE 0x40
  58. #define SPCR_SPTIE 0x20
  59. #define SPCR_SPEIE 0x10
  60. #define SPCR_MSTR 0x08
  61. #define SPCR_MODFEN 0x04
  62. #define SPCR_TXMD 0x02
  63. #define SPCR_SPMS 0x01
  64. /* SSLP */
  65. #define SSLP_SSL1P 0x02
  66. #define SSLP_SSL0P 0x01
  67. /* SPPCR */
  68. #define SPPCR_MOIFE 0x20
  69. #define SPPCR_MOIFV 0x10
  70. #define SPPCR_SPOM 0x04
  71. #define SPPCR_SPLP2 0x02
  72. #define SPPCR_SPLP 0x01
  73. /* SPSR */
  74. #define SPSR_SPRF 0x80
  75. #define SPSR_SPTEF 0x20
  76. #define SPSR_PERF 0x08
  77. #define SPSR_MODF 0x04
  78. #define SPSR_IDLNF 0x02
  79. #define SPSR_OVRF 0x01
  80. /* SPSCR */
  81. #define SPSCR_SPSLN_MASK 0x07
  82. /* SPSSR */
  83. #define SPSSR_SPECM_MASK 0x70
  84. #define SPSSR_SPCP_MASK 0x07
  85. /* SPDCR */
  86. #define SPDCR_SPLW 0x20
  87. #define SPDCR_SPRDTD 0x10
  88. #define SPDCR_SLSEL1 0x08
  89. #define SPDCR_SLSEL0 0x04
  90. #define SPDCR_SLSEL_MASK 0x0c
  91. #define SPDCR_SPFC1 0x02
  92. #define SPDCR_SPFC0 0x01
  93. /* SPCKD */
  94. #define SPCKD_SCKDL_MASK 0x07
  95. /* SSLND */
  96. #define SSLND_SLNDL_MASK 0x07
  97. /* SPND */
  98. #define SPND_SPNDL_MASK 0x07
  99. /* SPCR2 */
  100. #define SPCR2_PTE 0x08
  101. #define SPCR2_SPIE 0x04
  102. #define SPCR2_SPOE 0x02
  103. #define SPCR2_SPPE 0x01
  104. /* SPCMDn */
  105. #define SPCMD_SCKDEN 0x8000
  106. #define SPCMD_SLNDEN 0x4000
  107. #define SPCMD_SPNDEN 0x2000
  108. #define SPCMD_LSBF 0x1000
  109. #define SPCMD_SPB_MASK 0x0f00
  110. #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
  111. #define SPCMD_SPB_20BIT 0x0000
  112. #define SPCMD_SPB_24BIT 0x0100
  113. #define SPCMD_SPB_32BIT 0x0200
  114. #define SPCMD_SSLKP 0x0080
  115. #define SPCMD_SSLA_MASK 0x0030
  116. #define SPCMD_BRDV_MASK 0x000c
  117. #define SPCMD_CPOL 0x0002
  118. #define SPCMD_CPHA 0x0001
  119. struct rspi_data {
  120. void __iomem *addr;
  121. u32 max_speed_hz;
  122. struct spi_master *master;
  123. struct list_head queue;
  124. struct work_struct ws;
  125. wait_queue_head_t wait;
  126. spinlock_t lock;
  127. struct clk *clk;
  128. unsigned char spsr;
  129. };
  130. static void rspi_write8(struct rspi_data *rspi, u8 data, u16 offset)
  131. {
  132. iowrite8(data, rspi->addr + offset);
  133. }
  134. static void rspi_write16(struct rspi_data *rspi, u16 data, u16 offset)
  135. {
  136. iowrite16(data, rspi->addr + offset);
  137. }
  138. static u8 rspi_read8(struct rspi_data *rspi, u16 offset)
  139. {
  140. return ioread8(rspi->addr + offset);
  141. }
  142. static u16 rspi_read16(struct rspi_data *rspi, u16 offset)
  143. {
  144. return ioread16(rspi->addr + offset);
  145. }
  146. static unsigned char rspi_calc_spbr(struct rspi_data *rspi)
  147. {
  148. int tmp;
  149. unsigned char spbr;
  150. tmp = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
  151. spbr = clamp(tmp, 0, 255);
  152. return spbr;
  153. }
  154. static void rspi_enable_irq(struct rspi_data *rspi, u8 enable)
  155. {
  156. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
  157. }
  158. static void rspi_disable_irq(struct rspi_data *rspi, u8 disable)
  159. {
  160. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
  161. }
  162. static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
  163. u8 enable_bit)
  164. {
  165. int ret;
  166. rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
  167. rspi_enable_irq(rspi, enable_bit);
  168. ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
  169. if (ret == 0 && !(rspi->spsr & wait_mask))
  170. return -ETIMEDOUT;
  171. return 0;
  172. }
  173. static void rspi_assert_ssl(struct rspi_data *rspi)
  174. {
  175. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
  176. }
  177. static void rspi_negate_ssl(struct rspi_data *rspi)
  178. {
  179. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
  180. }
  181. static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
  182. {
  183. /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */
  184. rspi_write8(rspi, 0x00, RSPI_SPPCR);
  185. /* Sets transfer bit rate */
  186. rspi_write8(rspi, rspi_calc_spbr(rspi), RSPI_SPBR);
  187. /* Sets number of frames to be used: 1 frame */
  188. rspi_write8(rspi, 0x00, RSPI_SPDCR);
  189. /* Sets RSPCK, SSL, next-access delay value */
  190. rspi_write8(rspi, 0x00, RSPI_SPCKD);
  191. rspi_write8(rspi, 0x00, RSPI_SSLND);
  192. rspi_write8(rspi, 0x00, RSPI_SPND);
  193. /* Sets parity, interrupt mask */
  194. rspi_write8(rspi, 0x00, RSPI_SPCR2);
  195. /* Sets SPCMD */
  196. rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP,
  197. RSPI_SPCMD0);
  198. /* Sets RSPI mode */
  199. rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
  200. return 0;
  201. }
  202. static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
  203. struct spi_transfer *t)
  204. {
  205. int remain = t->len;
  206. u8 *data;
  207. data = (u8 *)t->tx_buf;
  208. while (remain > 0) {
  209. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD,
  210. RSPI_SPCR);
  211. if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
  212. dev_err(&rspi->master->dev,
  213. "%s: tx empty timeout\n", __func__);
  214. return -ETIMEDOUT;
  215. }
  216. rspi_write16(rspi, *data, RSPI_SPDR);
  217. data++;
  218. remain--;
  219. }
  220. /* Waiting for the last transmition */
  221. rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
  222. return 0;
  223. }
  224. static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
  225. struct spi_transfer *t)
  226. {
  227. int remain = t->len;
  228. u8 *data;
  229. unsigned char spsr;
  230. spsr = rspi_read8(rspi, RSPI_SPSR);
  231. if (spsr & SPSR_SPRF)
  232. rspi_read16(rspi, RSPI_SPDR); /* dummy read */
  233. if (spsr & SPSR_OVRF)
  234. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
  235. RSPI_SPCR);
  236. data = (u8 *)t->rx_buf;
  237. while (remain > 0) {
  238. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD,
  239. RSPI_SPCR);
  240. if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
  241. dev_err(&rspi->master->dev,
  242. "%s: tx empty timeout\n", __func__);
  243. return -ETIMEDOUT;
  244. }
  245. /* dummy write for generate clock */
  246. rspi_write16(rspi, 0x00, RSPI_SPDR);
  247. if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
  248. dev_err(&rspi->master->dev,
  249. "%s: receive timeout\n", __func__);
  250. return -ETIMEDOUT;
  251. }
  252. /* SPDR allows 16 or 32-bit access only */
  253. *data = (u8)rspi_read16(rspi, RSPI_SPDR);
  254. data++;
  255. remain--;
  256. }
  257. return 0;
  258. }
  259. static void rspi_work(struct work_struct *work)
  260. {
  261. struct rspi_data *rspi = container_of(work, struct rspi_data, ws);
  262. struct spi_message *mesg;
  263. struct spi_transfer *t;
  264. unsigned long flags;
  265. int ret;
  266. spin_lock_irqsave(&rspi->lock, flags);
  267. while (!list_empty(&rspi->queue)) {
  268. mesg = list_entry(rspi->queue.next, struct spi_message, queue);
  269. list_del_init(&mesg->queue);
  270. spin_unlock_irqrestore(&rspi->lock, flags);
  271. rspi_assert_ssl(rspi);
  272. list_for_each_entry(t, &mesg->transfers, transfer_list) {
  273. if (t->tx_buf) {
  274. ret = rspi_send_pio(rspi, mesg, t);
  275. if (ret < 0)
  276. goto error;
  277. }
  278. if (t->rx_buf) {
  279. ret = rspi_receive_pio(rspi, mesg, t);
  280. if (ret < 0)
  281. goto error;
  282. }
  283. mesg->actual_length += t->len;
  284. }
  285. rspi_negate_ssl(rspi);
  286. mesg->status = 0;
  287. mesg->complete(mesg->context);
  288. spin_lock_irqsave(&rspi->lock, flags);
  289. }
  290. return;
  291. error:
  292. mesg->status = ret;
  293. mesg->complete(mesg->context);
  294. }
  295. static int rspi_setup(struct spi_device *spi)
  296. {
  297. struct rspi_data *rspi = spi_master_get_devdata(spi->master);
  298. if (!spi->bits_per_word)
  299. spi->bits_per_word = 8;
  300. rspi->max_speed_hz = spi->max_speed_hz;
  301. rspi_set_config_register(rspi, 8);
  302. return 0;
  303. }
  304. static int rspi_transfer(struct spi_device *spi, struct spi_message *mesg)
  305. {
  306. struct rspi_data *rspi = spi_master_get_devdata(spi->master);
  307. unsigned long flags;
  308. mesg->actual_length = 0;
  309. mesg->status = -EINPROGRESS;
  310. spin_lock_irqsave(&rspi->lock, flags);
  311. list_add_tail(&mesg->queue, &rspi->queue);
  312. schedule_work(&rspi->ws);
  313. spin_unlock_irqrestore(&rspi->lock, flags);
  314. return 0;
  315. }
  316. static void rspi_cleanup(struct spi_device *spi)
  317. {
  318. }
  319. static irqreturn_t rspi_irq(int irq, void *_sr)
  320. {
  321. struct rspi_data *rspi = (struct rspi_data *)_sr;
  322. unsigned long spsr;
  323. irqreturn_t ret = IRQ_NONE;
  324. unsigned char disable_irq = 0;
  325. rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
  326. if (spsr & SPSR_SPRF)
  327. disable_irq |= SPCR_SPRIE;
  328. if (spsr & SPSR_SPTEF)
  329. disable_irq |= SPCR_SPTIE;
  330. if (disable_irq) {
  331. ret = IRQ_HANDLED;
  332. rspi_disable_irq(rspi, disable_irq);
  333. wake_up(&rspi->wait);
  334. }
  335. return ret;
  336. }
  337. static int __devexit rspi_remove(struct platform_device *pdev)
  338. {
  339. struct rspi_data *rspi = dev_get_drvdata(&pdev->dev);
  340. spi_unregister_master(rspi->master);
  341. free_irq(platform_get_irq(pdev, 0), rspi);
  342. clk_put(rspi->clk);
  343. iounmap(rspi->addr);
  344. spi_master_put(rspi->master);
  345. return 0;
  346. }
  347. static int __devinit rspi_probe(struct platform_device *pdev)
  348. {
  349. struct resource *res;
  350. struct spi_master *master;
  351. struct rspi_data *rspi;
  352. int ret, irq;
  353. char clk_name[16];
  354. /* get base addr */
  355. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  356. if (unlikely(res == NULL)) {
  357. dev_err(&pdev->dev, "invalid resource\n");
  358. return -EINVAL;
  359. }
  360. irq = platform_get_irq(pdev, 0);
  361. if (irq < 0) {
  362. dev_err(&pdev->dev, "platform_get_irq error\n");
  363. return -ENODEV;
  364. }
  365. master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
  366. if (master == NULL) {
  367. dev_err(&pdev->dev, "spi_alloc_master error.\n");
  368. return -ENOMEM;
  369. }
  370. rspi = spi_master_get_devdata(master);
  371. dev_set_drvdata(&pdev->dev, rspi);
  372. rspi->master = master;
  373. rspi->addr = ioremap(res->start, resource_size(res));
  374. if (rspi->addr == NULL) {
  375. dev_err(&pdev->dev, "ioremap error.\n");
  376. ret = -ENOMEM;
  377. goto error1;
  378. }
  379. snprintf(clk_name, sizeof(clk_name), "rspi%d", pdev->id);
  380. rspi->clk = clk_get(&pdev->dev, clk_name);
  381. if (IS_ERR(rspi->clk)) {
  382. dev_err(&pdev->dev, "cannot get clock\n");
  383. ret = PTR_ERR(rspi->clk);
  384. goto error2;
  385. }
  386. clk_enable(rspi->clk);
  387. INIT_LIST_HEAD(&rspi->queue);
  388. spin_lock_init(&rspi->lock);
  389. INIT_WORK(&rspi->ws, rspi_work);
  390. init_waitqueue_head(&rspi->wait);
  391. master->num_chipselect = 2;
  392. master->bus_num = pdev->id;
  393. master->setup = rspi_setup;
  394. master->transfer = rspi_transfer;
  395. master->cleanup = rspi_cleanup;
  396. ret = request_irq(irq, rspi_irq, 0, dev_name(&pdev->dev), rspi);
  397. if (ret < 0) {
  398. dev_err(&pdev->dev, "request_irq error\n");
  399. goto error3;
  400. }
  401. ret = spi_register_master(master);
  402. if (ret < 0) {
  403. dev_err(&pdev->dev, "spi_register_master error.\n");
  404. goto error4;
  405. }
  406. dev_info(&pdev->dev, "probed\n");
  407. return 0;
  408. error4:
  409. free_irq(irq, rspi);
  410. error3:
  411. clk_put(rspi->clk);
  412. error2:
  413. iounmap(rspi->addr);
  414. error1:
  415. spi_master_put(master);
  416. return ret;
  417. }
  418. static struct platform_driver rspi_driver = {
  419. .probe = rspi_probe,
  420. .remove = __devexit_p(rspi_remove),
  421. .driver = {
  422. .name = "rspi",
  423. .owner = THIS_MODULE,
  424. },
  425. };
  426. module_platform_driver(rspi_driver);
  427. MODULE_DESCRIPTION("Renesas RSPI bus driver");
  428. MODULE_LICENSE("GPL v2");
  429. MODULE_AUTHOR("Yoshihiro Shimoda");
  430. MODULE_ALIAS("platform:rspi");