spi-orion.c 13 KB

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  1. /*
  2. * Marvell Orion SPI controller driver
  3. *
  4. * Author: Shadi Ammouri <shadi@marvell.com>
  5. * Copyright (C) 2007-2008 Marvell Ltd.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/delay.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/err.h>
  16. #include <linux/io.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/spi/orion_spi.h>
  19. #include <linux/module.h>
  20. #include <asm/unaligned.h>
  21. #define DRIVER_NAME "orion_spi"
  22. #define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/
  23. #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
  24. #define ORION_SPI_IF_CTRL_REG 0x00
  25. #define ORION_SPI_IF_CONFIG_REG 0x04
  26. #define ORION_SPI_DATA_OUT_REG 0x08
  27. #define ORION_SPI_DATA_IN_REG 0x0c
  28. #define ORION_SPI_INT_CAUSE_REG 0x10
  29. #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
  30. #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
  31. struct orion_spi {
  32. struct work_struct work;
  33. /* Lock access to transfer list. */
  34. spinlock_t lock;
  35. struct list_head msg_queue;
  36. struct spi_master *master;
  37. void __iomem *base;
  38. unsigned int max_speed;
  39. unsigned int min_speed;
  40. struct orion_spi_info *spi_info;
  41. };
  42. static struct workqueue_struct *orion_spi_wq;
  43. static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
  44. {
  45. return orion_spi->base + reg;
  46. }
  47. static inline void
  48. orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
  49. {
  50. void __iomem *reg_addr = spi_reg(orion_spi, reg);
  51. u32 val;
  52. val = readl(reg_addr);
  53. val |= mask;
  54. writel(val, reg_addr);
  55. }
  56. static inline void
  57. orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
  58. {
  59. void __iomem *reg_addr = spi_reg(orion_spi, reg);
  60. u32 val;
  61. val = readl(reg_addr);
  62. val &= ~mask;
  63. writel(val, reg_addr);
  64. }
  65. static int orion_spi_set_transfer_size(struct orion_spi *orion_spi, int size)
  66. {
  67. if (size == 16) {
  68. orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
  69. ORION_SPI_IF_8_16_BIT_MODE);
  70. } else if (size == 8) {
  71. orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
  72. ORION_SPI_IF_8_16_BIT_MODE);
  73. } else {
  74. pr_debug("Bad bits per word value %d (only 8 or 16 are "
  75. "allowed).\n", size);
  76. return -EINVAL;
  77. }
  78. return 0;
  79. }
  80. static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
  81. {
  82. u32 tclk_hz;
  83. u32 rate;
  84. u32 prescale;
  85. u32 reg;
  86. struct orion_spi *orion_spi;
  87. orion_spi = spi_master_get_devdata(spi->master);
  88. tclk_hz = orion_spi->spi_info->tclk;
  89. /*
  90. * the supported rates are: 4,6,8...30
  91. * round up as we look for equal or less speed
  92. */
  93. rate = DIV_ROUND_UP(tclk_hz, speed);
  94. rate = roundup(rate, 2);
  95. /* check if requested speed is too small */
  96. if (rate > 30)
  97. return -EINVAL;
  98. if (rate < 4)
  99. rate = 4;
  100. /* Convert the rate to SPI clock divisor value. */
  101. prescale = 0x10 + rate/2;
  102. reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
  103. reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) | prescale);
  104. writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
  105. return 0;
  106. }
  107. /*
  108. * called only when no transfer is active on the bus
  109. */
  110. static int
  111. orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
  112. {
  113. struct orion_spi *orion_spi;
  114. unsigned int speed = spi->max_speed_hz;
  115. unsigned int bits_per_word = spi->bits_per_word;
  116. int rc;
  117. orion_spi = spi_master_get_devdata(spi->master);
  118. if ((t != NULL) && t->speed_hz)
  119. speed = t->speed_hz;
  120. if ((t != NULL) && t->bits_per_word)
  121. bits_per_word = t->bits_per_word;
  122. rc = orion_spi_baudrate_set(spi, speed);
  123. if (rc)
  124. return rc;
  125. return orion_spi_set_transfer_size(orion_spi, bits_per_word);
  126. }
  127. static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
  128. {
  129. if (enable)
  130. orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
  131. else
  132. orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
  133. }
  134. static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
  135. {
  136. int i;
  137. for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
  138. if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
  139. return 1;
  140. else
  141. udelay(1);
  142. }
  143. return -1;
  144. }
  145. static inline int
  146. orion_spi_write_read_8bit(struct spi_device *spi,
  147. const u8 **tx_buf, u8 **rx_buf)
  148. {
  149. void __iomem *tx_reg, *rx_reg, *int_reg;
  150. struct orion_spi *orion_spi;
  151. orion_spi = spi_master_get_devdata(spi->master);
  152. tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
  153. rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
  154. int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
  155. /* clear the interrupt cause register */
  156. writel(0x0, int_reg);
  157. if (tx_buf && *tx_buf)
  158. writel(*(*tx_buf)++, tx_reg);
  159. else
  160. writel(0, tx_reg);
  161. if (orion_spi_wait_till_ready(orion_spi) < 0) {
  162. dev_err(&spi->dev, "TXS timed out\n");
  163. return -1;
  164. }
  165. if (rx_buf && *rx_buf)
  166. *(*rx_buf)++ = readl(rx_reg);
  167. return 1;
  168. }
  169. static inline int
  170. orion_spi_write_read_16bit(struct spi_device *spi,
  171. const u16 **tx_buf, u16 **rx_buf)
  172. {
  173. void __iomem *tx_reg, *rx_reg, *int_reg;
  174. struct orion_spi *orion_spi;
  175. orion_spi = spi_master_get_devdata(spi->master);
  176. tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
  177. rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
  178. int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
  179. /* clear the interrupt cause register */
  180. writel(0x0, int_reg);
  181. if (tx_buf && *tx_buf)
  182. writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
  183. else
  184. writel(0, tx_reg);
  185. if (orion_spi_wait_till_ready(orion_spi) < 0) {
  186. dev_err(&spi->dev, "TXS timed out\n");
  187. return -1;
  188. }
  189. if (rx_buf && *rx_buf)
  190. put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
  191. return 1;
  192. }
  193. static unsigned int
  194. orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
  195. {
  196. struct orion_spi *orion_spi;
  197. unsigned int count;
  198. int word_len;
  199. orion_spi = spi_master_get_devdata(spi->master);
  200. word_len = spi->bits_per_word;
  201. count = xfer->len;
  202. if (word_len == 8) {
  203. const u8 *tx = xfer->tx_buf;
  204. u8 *rx = xfer->rx_buf;
  205. do {
  206. if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
  207. goto out;
  208. count--;
  209. } while (count);
  210. } else if (word_len == 16) {
  211. const u16 *tx = xfer->tx_buf;
  212. u16 *rx = xfer->rx_buf;
  213. do {
  214. if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
  215. goto out;
  216. count -= 2;
  217. } while (count);
  218. }
  219. out:
  220. return xfer->len - count;
  221. }
  222. static void orion_spi_work(struct work_struct *work)
  223. {
  224. struct orion_spi *orion_spi =
  225. container_of(work, struct orion_spi, work);
  226. spin_lock_irq(&orion_spi->lock);
  227. while (!list_empty(&orion_spi->msg_queue)) {
  228. struct spi_message *m;
  229. struct spi_device *spi;
  230. struct spi_transfer *t = NULL;
  231. int par_override = 0;
  232. int status = 0;
  233. int cs_active = 0;
  234. m = container_of(orion_spi->msg_queue.next, struct spi_message,
  235. queue);
  236. list_del_init(&m->queue);
  237. spin_unlock_irq(&orion_spi->lock);
  238. spi = m->spi;
  239. /* Load defaults */
  240. status = orion_spi_setup_transfer(spi, NULL);
  241. if (status < 0)
  242. goto msg_done;
  243. list_for_each_entry(t, &m->transfers, transfer_list) {
  244. if (par_override || t->speed_hz || t->bits_per_word) {
  245. par_override = 1;
  246. status = orion_spi_setup_transfer(spi, t);
  247. if (status < 0)
  248. break;
  249. if (!t->speed_hz && !t->bits_per_word)
  250. par_override = 0;
  251. }
  252. if (!cs_active) {
  253. orion_spi_set_cs(orion_spi, 1);
  254. cs_active = 1;
  255. }
  256. if (t->len)
  257. m->actual_length +=
  258. orion_spi_write_read(spi, t);
  259. if (t->delay_usecs)
  260. udelay(t->delay_usecs);
  261. if (t->cs_change) {
  262. orion_spi_set_cs(orion_spi, 0);
  263. cs_active = 0;
  264. }
  265. }
  266. msg_done:
  267. if (cs_active)
  268. orion_spi_set_cs(orion_spi, 0);
  269. m->status = status;
  270. m->complete(m->context);
  271. spin_lock_irq(&orion_spi->lock);
  272. }
  273. spin_unlock_irq(&orion_spi->lock);
  274. }
  275. static int __init orion_spi_reset(struct orion_spi *orion_spi)
  276. {
  277. /* Verify that the CS is deasserted */
  278. orion_spi_set_cs(orion_spi, 0);
  279. return 0;
  280. }
  281. static int orion_spi_setup(struct spi_device *spi)
  282. {
  283. struct orion_spi *orion_spi;
  284. orion_spi = spi_master_get_devdata(spi->master);
  285. if ((spi->max_speed_hz == 0)
  286. || (spi->max_speed_hz > orion_spi->max_speed))
  287. spi->max_speed_hz = orion_spi->max_speed;
  288. if (spi->max_speed_hz < orion_spi->min_speed) {
  289. dev_err(&spi->dev, "setup: requested speed too low %d Hz\n",
  290. spi->max_speed_hz);
  291. return -EINVAL;
  292. }
  293. /*
  294. * baudrate & width will be set orion_spi_setup_transfer
  295. */
  296. return 0;
  297. }
  298. static int orion_spi_transfer(struct spi_device *spi, struct spi_message *m)
  299. {
  300. struct orion_spi *orion_spi;
  301. struct spi_transfer *t = NULL;
  302. unsigned long flags;
  303. m->actual_length = 0;
  304. m->status = 0;
  305. /* reject invalid messages and transfers */
  306. if (list_empty(&m->transfers) || !m->complete)
  307. return -EINVAL;
  308. orion_spi = spi_master_get_devdata(spi->master);
  309. list_for_each_entry(t, &m->transfers, transfer_list) {
  310. unsigned int bits_per_word = spi->bits_per_word;
  311. if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
  312. dev_err(&spi->dev,
  313. "message rejected : "
  314. "invalid transfer data buffers\n");
  315. goto msg_rejected;
  316. }
  317. if (t->bits_per_word)
  318. bits_per_word = t->bits_per_word;
  319. if ((bits_per_word != 8) && (bits_per_word != 16)) {
  320. dev_err(&spi->dev,
  321. "message rejected : "
  322. "invalid transfer bits_per_word (%d bits)\n",
  323. bits_per_word);
  324. goto msg_rejected;
  325. }
  326. /*make sure buffer length is even when working in 16 bit mode*/
  327. if ((t->bits_per_word == 16) && (t->len & 1)) {
  328. dev_err(&spi->dev,
  329. "message rejected : "
  330. "odd data length (%d) while in 16 bit mode\n",
  331. t->len);
  332. goto msg_rejected;
  333. }
  334. if (t->speed_hz && t->speed_hz < orion_spi->min_speed) {
  335. dev_err(&spi->dev,
  336. "message rejected : "
  337. "device min speed (%d Hz) exceeds "
  338. "required transfer speed (%d Hz)\n",
  339. orion_spi->min_speed, t->speed_hz);
  340. goto msg_rejected;
  341. }
  342. }
  343. spin_lock_irqsave(&orion_spi->lock, flags);
  344. list_add_tail(&m->queue, &orion_spi->msg_queue);
  345. queue_work(orion_spi_wq, &orion_spi->work);
  346. spin_unlock_irqrestore(&orion_spi->lock, flags);
  347. return 0;
  348. msg_rejected:
  349. /* Message rejected and not queued */
  350. m->status = -EINVAL;
  351. if (m->complete)
  352. m->complete(m->context);
  353. return -EINVAL;
  354. }
  355. static int __init orion_spi_probe(struct platform_device *pdev)
  356. {
  357. struct spi_master *master;
  358. struct orion_spi *spi;
  359. struct resource *r;
  360. struct orion_spi_info *spi_info;
  361. int status = 0;
  362. spi_info = pdev->dev.platform_data;
  363. master = spi_alloc_master(&pdev->dev, sizeof *spi);
  364. if (master == NULL) {
  365. dev_dbg(&pdev->dev, "master allocation failed\n");
  366. return -ENOMEM;
  367. }
  368. if (pdev->id != -1)
  369. master->bus_num = pdev->id;
  370. /* we support only mode 0, and no options */
  371. master->mode_bits = 0;
  372. master->setup = orion_spi_setup;
  373. master->transfer = orion_spi_transfer;
  374. master->num_chipselect = ORION_NUM_CHIPSELECTS;
  375. dev_set_drvdata(&pdev->dev, master);
  376. spi = spi_master_get_devdata(master);
  377. spi->master = master;
  378. spi->spi_info = spi_info;
  379. spi->max_speed = DIV_ROUND_UP(spi_info->tclk, 4);
  380. spi->min_speed = DIV_ROUND_UP(spi_info->tclk, 30);
  381. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  382. if (r == NULL) {
  383. status = -ENODEV;
  384. goto out;
  385. }
  386. if (!request_mem_region(r->start, resource_size(r),
  387. dev_name(&pdev->dev))) {
  388. status = -EBUSY;
  389. goto out;
  390. }
  391. spi->base = ioremap(r->start, SZ_1K);
  392. INIT_WORK(&spi->work, orion_spi_work);
  393. spin_lock_init(&spi->lock);
  394. INIT_LIST_HEAD(&spi->msg_queue);
  395. if (orion_spi_reset(spi) < 0)
  396. goto out_rel_mem;
  397. status = spi_register_master(master);
  398. if (status < 0)
  399. goto out_rel_mem;
  400. return status;
  401. out_rel_mem:
  402. release_mem_region(r->start, resource_size(r));
  403. out:
  404. spi_master_put(master);
  405. return status;
  406. }
  407. static int __exit orion_spi_remove(struct platform_device *pdev)
  408. {
  409. struct spi_master *master;
  410. struct orion_spi *spi;
  411. struct resource *r;
  412. master = dev_get_drvdata(&pdev->dev);
  413. spi = spi_master_get_devdata(master);
  414. cancel_work_sync(&spi->work);
  415. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  416. release_mem_region(r->start, resource_size(r));
  417. spi_unregister_master(master);
  418. return 0;
  419. }
  420. MODULE_ALIAS("platform:" DRIVER_NAME);
  421. static struct platform_driver orion_spi_driver = {
  422. .driver = {
  423. .name = DRIVER_NAME,
  424. .owner = THIS_MODULE,
  425. },
  426. .remove = __exit_p(orion_spi_remove),
  427. };
  428. static int __init orion_spi_init(void)
  429. {
  430. orion_spi_wq = create_singlethread_workqueue(
  431. orion_spi_driver.driver.name);
  432. if (orion_spi_wq == NULL)
  433. return -ENOMEM;
  434. return platform_driver_probe(&orion_spi_driver, orion_spi_probe);
  435. }
  436. module_init(orion_spi_init);
  437. static void __exit orion_spi_exit(void)
  438. {
  439. flush_workqueue(orion_spi_wq);
  440. platform_driver_unregister(&orion_spi_driver);
  441. destroy_workqueue(orion_spi_wq);
  442. }
  443. module_exit(orion_spi_exit);
  444. MODULE_DESCRIPTION("Orion SPI driver");
  445. MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
  446. MODULE_LICENSE("GPL");