resource_tracker.c 67 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include "mlx4.h"
  44. #include "fw.h"
  45. #define MLX4_MAC_VALID (1ull << 63)
  46. #define MLX4_MAC_MASK 0x7fffffffffffffffULL
  47. #define ETH_ALEN 6
  48. struct mac_res {
  49. struct list_head list;
  50. u64 mac;
  51. u8 port;
  52. };
  53. struct res_common {
  54. struct list_head list;
  55. u32 res_id;
  56. int owner;
  57. int state;
  58. int from_state;
  59. int to_state;
  60. int removing;
  61. };
  62. enum {
  63. RES_ANY_BUSY = 1
  64. };
  65. struct res_gid {
  66. struct list_head list;
  67. u8 gid[16];
  68. enum mlx4_protocol prot;
  69. enum mlx4_steer_type steer;
  70. };
  71. enum res_qp_states {
  72. RES_QP_BUSY = RES_ANY_BUSY,
  73. /* QP number was allocated */
  74. RES_QP_RESERVED,
  75. /* ICM memory for QP context was mapped */
  76. RES_QP_MAPPED,
  77. /* QP is in hw ownership */
  78. RES_QP_HW
  79. };
  80. static inline const char *qp_states_str(enum res_qp_states state)
  81. {
  82. switch (state) {
  83. case RES_QP_BUSY: return "RES_QP_BUSY";
  84. case RES_QP_RESERVED: return "RES_QP_RESERVED";
  85. case RES_QP_MAPPED: return "RES_QP_MAPPED";
  86. case RES_QP_HW: return "RES_QP_HW";
  87. default: return "Unknown";
  88. }
  89. }
  90. struct res_qp {
  91. struct res_common com;
  92. struct res_mtt *mtt;
  93. struct res_cq *rcq;
  94. struct res_cq *scq;
  95. struct res_srq *srq;
  96. struct list_head mcg_list;
  97. spinlock_t mcg_spl;
  98. int local_qpn;
  99. };
  100. enum res_mtt_states {
  101. RES_MTT_BUSY = RES_ANY_BUSY,
  102. RES_MTT_ALLOCATED,
  103. };
  104. static inline const char *mtt_states_str(enum res_mtt_states state)
  105. {
  106. switch (state) {
  107. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  108. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  109. default: return "Unknown";
  110. }
  111. }
  112. struct res_mtt {
  113. struct res_common com;
  114. int order;
  115. atomic_t ref_count;
  116. };
  117. enum res_mpt_states {
  118. RES_MPT_BUSY = RES_ANY_BUSY,
  119. RES_MPT_RESERVED,
  120. RES_MPT_MAPPED,
  121. RES_MPT_HW,
  122. };
  123. struct res_mpt {
  124. struct res_common com;
  125. struct res_mtt *mtt;
  126. int key;
  127. };
  128. enum res_eq_states {
  129. RES_EQ_BUSY = RES_ANY_BUSY,
  130. RES_EQ_RESERVED,
  131. RES_EQ_HW,
  132. };
  133. struct res_eq {
  134. struct res_common com;
  135. struct res_mtt *mtt;
  136. };
  137. enum res_cq_states {
  138. RES_CQ_BUSY = RES_ANY_BUSY,
  139. RES_CQ_ALLOCATED,
  140. RES_CQ_HW,
  141. };
  142. struct res_cq {
  143. struct res_common com;
  144. struct res_mtt *mtt;
  145. atomic_t ref_count;
  146. };
  147. enum res_srq_states {
  148. RES_SRQ_BUSY = RES_ANY_BUSY,
  149. RES_SRQ_ALLOCATED,
  150. RES_SRQ_HW,
  151. };
  152. static inline const char *srq_states_str(enum res_srq_states state)
  153. {
  154. switch (state) {
  155. case RES_SRQ_BUSY: return "RES_SRQ_BUSY";
  156. case RES_SRQ_ALLOCATED: return "RES_SRQ_ALLOCATED";
  157. case RES_SRQ_HW: return "RES_SRQ_HW";
  158. default: return "Unknown";
  159. }
  160. }
  161. struct res_srq {
  162. struct res_common com;
  163. struct res_mtt *mtt;
  164. struct res_cq *cq;
  165. atomic_t ref_count;
  166. };
  167. enum res_counter_states {
  168. RES_COUNTER_BUSY = RES_ANY_BUSY,
  169. RES_COUNTER_ALLOCATED,
  170. };
  171. static inline const char *counter_states_str(enum res_counter_states state)
  172. {
  173. switch (state) {
  174. case RES_COUNTER_BUSY: return "RES_COUNTER_BUSY";
  175. case RES_COUNTER_ALLOCATED: return "RES_COUNTER_ALLOCATED";
  176. default: return "Unknown";
  177. }
  178. }
  179. struct res_counter {
  180. struct res_common com;
  181. int port;
  182. };
  183. /* For Debug uses */
  184. static const char *ResourceType(enum mlx4_resource rt)
  185. {
  186. switch (rt) {
  187. case RES_QP: return "RES_QP";
  188. case RES_CQ: return "RES_CQ";
  189. case RES_SRQ: return "RES_SRQ";
  190. case RES_MPT: return "RES_MPT";
  191. case RES_MTT: return "RES_MTT";
  192. case RES_MAC: return "RES_MAC";
  193. case RES_EQ: return "RES_EQ";
  194. case RES_COUNTER: return "RES_COUNTER";
  195. default: return "Unknown resource type !!!";
  196. };
  197. }
  198. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  199. {
  200. struct mlx4_priv *priv = mlx4_priv(dev);
  201. int i;
  202. int t;
  203. priv->mfunc.master.res_tracker.slave_list =
  204. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  205. GFP_KERNEL);
  206. if (!priv->mfunc.master.res_tracker.slave_list)
  207. return -ENOMEM;
  208. for (i = 0 ; i < dev->num_slaves; i++) {
  209. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  210. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  211. slave_list[i].res_list[t]);
  212. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  213. }
  214. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  215. dev->num_slaves);
  216. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  217. INIT_RADIX_TREE(&priv->mfunc.master.res_tracker.res_tree[i],
  218. GFP_ATOMIC|__GFP_NOWARN);
  219. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  220. return 0 ;
  221. }
  222. void mlx4_free_resource_tracker(struct mlx4_dev *dev)
  223. {
  224. struct mlx4_priv *priv = mlx4_priv(dev);
  225. int i;
  226. if (priv->mfunc.master.res_tracker.slave_list) {
  227. for (i = 0 ; i < dev->num_slaves; i++)
  228. mlx4_delete_all_resources_for_slave(dev, i);
  229. kfree(priv->mfunc.master.res_tracker.slave_list);
  230. }
  231. }
  232. static void update_ud_gid(struct mlx4_dev *dev,
  233. struct mlx4_qp_context *qp_ctx, u8 slave)
  234. {
  235. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  236. if (MLX4_QP_ST_UD == ts)
  237. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  238. mlx4_dbg(dev, "slave %d, new gid index: 0x%x ",
  239. slave, qp_ctx->pri_path.mgid_index);
  240. }
  241. static int mpt_mask(struct mlx4_dev *dev)
  242. {
  243. return dev->caps.num_mpts - 1;
  244. }
  245. static void *find_res(struct mlx4_dev *dev, int res_id,
  246. enum mlx4_resource type)
  247. {
  248. struct mlx4_priv *priv = mlx4_priv(dev);
  249. return radix_tree_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  250. res_id);
  251. }
  252. static int get_res(struct mlx4_dev *dev, int slave, int res_id,
  253. enum mlx4_resource type,
  254. void *res)
  255. {
  256. struct res_common *r;
  257. int err = 0;
  258. spin_lock_irq(mlx4_tlock(dev));
  259. r = find_res(dev, res_id, type);
  260. if (!r) {
  261. err = -ENONET;
  262. goto exit;
  263. }
  264. if (r->state == RES_ANY_BUSY) {
  265. err = -EBUSY;
  266. goto exit;
  267. }
  268. if (r->owner != slave) {
  269. err = -EPERM;
  270. goto exit;
  271. }
  272. r->from_state = r->state;
  273. r->state = RES_ANY_BUSY;
  274. mlx4_dbg(dev, "res %s id 0x%x to busy\n",
  275. ResourceType(type), r->res_id);
  276. if (res)
  277. *((struct res_common **)res) = r;
  278. exit:
  279. spin_unlock_irq(mlx4_tlock(dev));
  280. return err;
  281. }
  282. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  283. enum mlx4_resource type,
  284. int res_id, int *slave)
  285. {
  286. struct res_common *r;
  287. int err = -ENOENT;
  288. int id = res_id;
  289. if (type == RES_QP)
  290. id &= 0x7fffff;
  291. spin_lock(mlx4_tlock(dev));
  292. r = find_res(dev, id, type);
  293. if (r) {
  294. *slave = r->owner;
  295. err = 0;
  296. }
  297. spin_unlock(mlx4_tlock(dev));
  298. return err;
  299. }
  300. static void put_res(struct mlx4_dev *dev, int slave, int res_id,
  301. enum mlx4_resource type)
  302. {
  303. struct res_common *r;
  304. spin_lock_irq(mlx4_tlock(dev));
  305. r = find_res(dev, res_id, type);
  306. if (r)
  307. r->state = r->from_state;
  308. spin_unlock_irq(mlx4_tlock(dev));
  309. }
  310. static struct res_common *alloc_qp_tr(int id)
  311. {
  312. struct res_qp *ret;
  313. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  314. if (!ret)
  315. return NULL;
  316. ret->com.res_id = id;
  317. ret->com.state = RES_QP_RESERVED;
  318. ret->local_qpn = id;
  319. INIT_LIST_HEAD(&ret->mcg_list);
  320. spin_lock_init(&ret->mcg_spl);
  321. return &ret->com;
  322. }
  323. static struct res_common *alloc_mtt_tr(int id, int order)
  324. {
  325. struct res_mtt *ret;
  326. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  327. if (!ret)
  328. return NULL;
  329. ret->com.res_id = id;
  330. ret->order = order;
  331. ret->com.state = RES_MTT_ALLOCATED;
  332. atomic_set(&ret->ref_count, 0);
  333. return &ret->com;
  334. }
  335. static struct res_common *alloc_mpt_tr(int id, int key)
  336. {
  337. struct res_mpt *ret;
  338. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  339. if (!ret)
  340. return NULL;
  341. ret->com.res_id = id;
  342. ret->com.state = RES_MPT_RESERVED;
  343. ret->key = key;
  344. return &ret->com;
  345. }
  346. static struct res_common *alloc_eq_tr(int id)
  347. {
  348. struct res_eq *ret;
  349. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  350. if (!ret)
  351. return NULL;
  352. ret->com.res_id = id;
  353. ret->com.state = RES_EQ_RESERVED;
  354. return &ret->com;
  355. }
  356. static struct res_common *alloc_cq_tr(int id)
  357. {
  358. struct res_cq *ret;
  359. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  360. if (!ret)
  361. return NULL;
  362. ret->com.res_id = id;
  363. ret->com.state = RES_CQ_ALLOCATED;
  364. atomic_set(&ret->ref_count, 0);
  365. return &ret->com;
  366. }
  367. static struct res_common *alloc_srq_tr(int id)
  368. {
  369. struct res_srq *ret;
  370. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  371. if (!ret)
  372. return NULL;
  373. ret->com.res_id = id;
  374. ret->com.state = RES_SRQ_ALLOCATED;
  375. atomic_set(&ret->ref_count, 0);
  376. return &ret->com;
  377. }
  378. static struct res_common *alloc_counter_tr(int id)
  379. {
  380. struct res_counter *ret;
  381. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  382. if (!ret)
  383. return NULL;
  384. ret->com.res_id = id;
  385. ret->com.state = RES_COUNTER_ALLOCATED;
  386. return &ret->com;
  387. }
  388. static struct res_common *alloc_tr(int id, enum mlx4_resource type, int slave,
  389. int extra)
  390. {
  391. struct res_common *ret;
  392. switch (type) {
  393. case RES_QP:
  394. ret = alloc_qp_tr(id);
  395. break;
  396. case RES_MPT:
  397. ret = alloc_mpt_tr(id, extra);
  398. break;
  399. case RES_MTT:
  400. ret = alloc_mtt_tr(id, extra);
  401. break;
  402. case RES_EQ:
  403. ret = alloc_eq_tr(id);
  404. break;
  405. case RES_CQ:
  406. ret = alloc_cq_tr(id);
  407. break;
  408. case RES_SRQ:
  409. ret = alloc_srq_tr(id);
  410. break;
  411. case RES_MAC:
  412. printk(KERN_ERR "implementation missing\n");
  413. return NULL;
  414. case RES_COUNTER:
  415. ret = alloc_counter_tr(id);
  416. break;
  417. default:
  418. return NULL;
  419. }
  420. if (ret)
  421. ret->owner = slave;
  422. return ret;
  423. }
  424. static int add_res_range(struct mlx4_dev *dev, int slave, int base, int count,
  425. enum mlx4_resource type, int extra)
  426. {
  427. int i;
  428. int err;
  429. struct mlx4_priv *priv = mlx4_priv(dev);
  430. struct res_common **res_arr;
  431. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  432. struct radix_tree_root *root = &tracker->res_tree[type];
  433. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  434. if (!res_arr)
  435. return -ENOMEM;
  436. for (i = 0; i < count; ++i) {
  437. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  438. if (!res_arr[i]) {
  439. for (--i; i >= 0; --i)
  440. kfree(res_arr[i]);
  441. kfree(res_arr);
  442. return -ENOMEM;
  443. }
  444. }
  445. spin_lock_irq(mlx4_tlock(dev));
  446. for (i = 0; i < count; ++i) {
  447. if (find_res(dev, base + i, type)) {
  448. err = -EEXIST;
  449. goto undo;
  450. }
  451. err = radix_tree_insert(root, base + i, res_arr[i]);
  452. if (err)
  453. goto undo;
  454. list_add_tail(&res_arr[i]->list,
  455. &tracker->slave_list[slave].res_list[type]);
  456. }
  457. spin_unlock_irq(mlx4_tlock(dev));
  458. kfree(res_arr);
  459. return 0;
  460. undo:
  461. for (--i; i >= base; --i)
  462. radix_tree_delete(&tracker->res_tree[type], i);
  463. spin_unlock_irq(mlx4_tlock(dev));
  464. for (i = 0; i < count; ++i)
  465. kfree(res_arr[i]);
  466. kfree(res_arr);
  467. return err;
  468. }
  469. static int remove_qp_ok(struct res_qp *res)
  470. {
  471. if (res->com.state == RES_QP_BUSY)
  472. return -EBUSY;
  473. else if (res->com.state != RES_QP_RESERVED)
  474. return -EPERM;
  475. return 0;
  476. }
  477. static int remove_mtt_ok(struct res_mtt *res, int order)
  478. {
  479. if (res->com.state == RES_MTT_BUSY ||
  480. atomic_read(&res->ref_count)) {
  481. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  482. __func__, __LINE__,
  483. mtt_states_str(res->com.state),
  484. atomic_read(&res->ref_count));
  485. return -EBUSY;
  486. } else if (res->com.state != RES_MTT_ALLOCATED)
  487. return -EPERM;
  488. else if (res->order != order)
  489. return -EINVAL;
  490. return 0;
  491. }
  492. static int remove_mpt_ok(struct res_mpt *res)
  493. {
  494. if (res->com.state == RES_MPT_BUSY)
  495. return -EBUSY;
  496. else if (res->com.state != RES_MPT_RESERVED)
  497. return -EPERM;
  498. return 0;
  499. }
  500. static int remove_eq_ok(struct res_eq *res)
  501. {
  502. if (res->com.state == RES_MPT_BUSY)
  503. return -EBUSY;
  504. else if (res->com.state != RES_MPT_RESERVED)
  505. return -EPERM;
  506. return 0;
  507. }
  508. static int remove_counter_ok(struct res_counter *res)
  509. {
  510. if (res->com.state == RES_COUNTER_BUSY)
  511. return -EBUSY;
  512. else if (res->com.state != RES_COUNTER_ALLOCATED)
  513. return -EPERM;
  514. return 0;
  515. }
  516. static int remove_cq_ok(struct res_cq *res)
  517. {
  518. if (res->com.state == RES_CQ_BUSY)
  519. return -EBUSY;
  520. else if (res->com.state != RES_CQ_ALLOCATED)
  521. return -EPERM;
  522. return 0;
  523. }
  524. static int remove_srq_ok(struct res_srq *res)
  525. {
  526. if (res->com.state == RES_SRQ_BUSY)
  527. return -EBUSY;
  528. else if (res->com.state != RES_SRQ_ALLOCATED)
  529. return -EPERM;
  530. return 0;
  531. }
  532. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  533. {
  534. switch (type) {
  535. case RES_QP:
  536. return remove_qp_ok((struct res_qp *)res);
  537. case RES_CQ:
  538. return remove_cq_ok((struct res_cq *)res);
  539. case RES_SRQ:
  540. return remove_srq_ok((struct res_srq *)res);
  541. case RES_MPT:
  542. return remove_mpt_ok((struct res_mpt *)res);
  543. case RES_MTT:
  544. return remove_mtt_ok((struct res_mtt *)res, extra);
  545. case RES_MAC:
  546. return -ENOSYS;
  547. case RES_EQ:
  548. return remove_eq_ok((struct res_eq *)res);
  549. case RES_COUNTER:
  550. return remove_counter_ok((struct res_counter *)res);
  551. default:
  552. return -EINVAL;
  553. }
  554. }
  555. static int rem_res_range(struct mlx4_dev *dev, int slave, int base, int count,
  556. enum mlx4_resource type, int extra)
  557. {
  558. int i;
  559. int err;
  560. struct mlx4_priv *priv = mlx4_priv(dev);
  561. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  562. struct res_common *r;
  563. spin_lock_irq(mlx4_tlock(dev));
  564. for (i = base; i < base + count; ++i) {
  565. r = radix_tree_lookup(&tracker->res_tree[type], i);
  566. if (!r) {
  567. err = -ENOENT;
  568. goto out;
  569. }
  570. if (r->owner != slave) {
  571. err = -EPERM;
  572. goto out;
  573. }
  574. err = remove_ok(r, type, extra);
  575. if (err)
  576. goto out;
  577. }
  578. for (i = base; i < base + count; ++i) {
  579. r = radix_tree_lookup(&tracker->res_tree[type], i);
  580. radix_tree_delete(&tracker->res_tree[type], i);
  581. list_del(&r->list);
  582. kfree(r);
  583. }
  584. err = 0;
  585. out:
  586. spin_unlock_irq(mlx4_tlock(dev));
  587. return err;
  588. }
  589. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  590. enum res_qp_states state, struct res_qp **qp,
  591. int alloc)
  592. {
  593. struct mlx4_priv *priv = mlx4_priv(dev);
  594. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  595. struct res_qp *r;
  596. int err = 0;
  597. spin_lock_irq(mlx4_tlock(dev));
  598. r = radix_tree_lookup(&tracker->res_tree[RES_QP], qpn);
  599. if (!r)
  600. err = -ENOENT;
  601. else if (r->com.owner != slave)
  602. err = -EPERM;
  603. else {
  604. switch (state) {
  605. case RES_QP_BUSY:
  606. mlx4_dbg(dev, "%s: failed RES_QP, 0x%x\n",
  607. __func__, r->com.res_id);
  608. err = -EBUSY;
  609. break;
  610. case RES_QP_RESERVED:
  611. if (r->com.state == RES_QP_MAPPED && !alloc)
  612. break;
  613. mlx4_dbg(dev, "failed RES_QP, 0x%x\n", r->com.res_id);
  614. err = -EINVAL;
  615. break;
  616. case RES_QP_MAPPED:
  617. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  618. r->com.state == RES_QP_HW)
  619. break;
  620. else {
  621. mlx4_dbg(dev, "failed RES_QP, 0x%x\n",
  622. r->com.res_id);
  623. err = -EINVAL;
  624. }
  625. break;
  626. case RES_QP_HW:
  627. if (r->com.state != RES_QP_MAPPED)
  628. err = -EINVAL;
  629. break;
  630. default:
  631. err = -EINVAL;
  632. }
  633. if (!err) {
  634. r->com.from_state = r->com.state;
  635. r->com.to_state = state;
  636. r->com.state = RES_QP_BUSY;
  637. if (qp)
  638. *qp = r;
  639. }
  640. }
  641. spin_unlock_irq(mlx4_tlock(dev));
  642. return err;
  643. }
  644. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  645. enum res_mpt_states state, struct res_mpt **mpt)
  646. {
  647. struct mlx4_priv *priv = mlx4_priv(dev);
  648. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  649. struct res_mpt *r;
  650. int err = 0;
  651. spin_lock_irq(mlx4_tlock(dev));
  652. r = radix_tree_lookup(&tracker->res_tree[RES_MPT], index);
  653. if (!r)
  654. err = -ENOENT;
  655. else if (r->com.owner != slave)
  656. err = -EPERM;
  657. else {
  658. switch (state) {
  659. case RES_MPT_BUSY:
  660. err = -EINVAL;
  661. break;
  662. case RES_MPT_RESERVED:
  663. if (r->com.state != RES_MPT_MAPPED)
  664. err = -EINVAL;
  665. break;
  666. case RES_MPT_MAPPED:
  667. if (r->com.state != RES_MPT_RESERVED &&
  668. r->com.state != RES_MPT_HW)
  669. err = -EINVAL;
  670. break;
  671. case RES_MPT_HW:
  672. if (r->com.state != RES_MPT_MAPPED)
  673. err = -EINVAL;
  674. break;
  675. default:
  676. err = -EINVAL;
  677. }
  678. if (!err) {
  679. r->com.from_state = r->com.state;
  680. r->com.to_state = state;
  681. r->com.state = RES_MPT_BUSY;
  682. if (mpt)
  683. *mpt = r;
  684. }
  685. }
  686. spin_unlock_irq(mlx4_tlock(dev));
  687. return err;
  688. }
  689. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  690. enum res_eq_states state, struct res_eq **eq)
  691. {
  692. struct mlx4_priv *priv = mlx4_priv(dev);
  693. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  694. struct res_eq *r;
  695. int err = 0;
  696. spin_lock_irq(mlx4_tlock(dev));
  697. r = radix_tree_lookup(&tracker->res_tree[RES_EQ], index);
  698. if (!r)
  699. err = -ENOENT;
  700. else if (r->com.owner != slave)
  701. err = -EPERM;
  702. else {
  703. switch (state) {
  704. case RES_EQ_BUSY:
  705. err = -EINVAL;
  706. break;
  707. case RES_EQ_RESERVED:
  708. if (r->com.state != RES_EQ_HW)
  709. err = -EINVAL;
  710. break;
  711. case RES_EQ_HW:
  712. if (r->com.state != RES_EQ_RESERVED)
  713. err = -EINVAL;
  714. break;
  715. default:
  716. err = -EINVAL;
  717. }
  718. if (!err) {
  719. r->com.from_state = r->com.state;
  720. r->com.to_state = state;
  721. r->com.state = RES_EQ_BUSY;
  722. if (eq)
  723. *eq = r;
  724. }
  725. }
  726. spin_unlock_irq(mlx4_tlock(dev));
  727. return err;
  728. }
  729. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  730. enum res_cq_states state, struct res_cq **cq)
  731. {
  732. struct mlx4_priv *priv = mlx4_priv(dev);
  733. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  734. struct res_cq *r;
  735. int err;
  736. spin_lock_irq(mlx4_tlock(dev));
  737. r = radix_tree_lookup(&tracker->res_tree[RES_CQ], cqn);
  738. if (!r)
  739. err = -ENOENT;
  740. else if (r->com.owner != slave)
  741. err = -EPERM;
  742. else {
  743. switch (state) {
  744. case RES_CQ_BUSY:
  745. err = -EBUSY;
  746. break;
  747. case RES_CQ_ALLOCATED:
  748. if (r->com.state != RES_CQ_HW)
  749. err = -EINVAL;
  750. else if (atomic_read(&r->ref_count))
  751. err = -EBUSY;
  752. else
  753. err = 0;
  754. break;
  755. case RES_CQ_HW:
  756. if (r->com.state != RES_CQ_ALLOCATED)
  757. err = -EINVAL;
  758. else
  759. err = 0;
  760. break;
  761. default:
  762. err = -EINVAL;
  763. }
  764. if (!err) {
  765. r->com.from_state = r->com.state;
  766. r->com.to_state = state;
  767. r->com.state = RES_CQ_BUSY;
  768. if (cq)
  769. *cq = r;
  770. }
  771. }
  772. spin_unlock_irq(mlx4_tlock(dev));
  773. return err;
  774. }
  775. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  776. enum res_cq_states state, struct res_srq **srq)
  777. {
  778. struct mlx4_priv *priv = mlx4_priv(dev);
  779. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  780. struct res_srq *r;
  781. int err = 0;
  782. spin_lock_irq(mlx4_tlock(dev));
  783. r = radix_tree_lookup(&tracker->res_tree[RES_SRQ], index);
  784. if (!r)
  785. err = -ENOENT;
  786. else if (r->com.owner != slave)
  787. err = -EPERM;
  788. else {
  789. switch (state) {
  790. case RES_SRQ_BUSY:
  791. err = -EINVAL;
  792. break;
  793. case RES_SRQ_ALLOCATED:
  794. if (r->com.state != RES_SRQ_HW)
  795. err = -EINVAL;
  796. else if (atomic_read(&r->ref_count))
  797. err = -EBUSY;
  798. break;
  799. case RES_SRQ_HW:
  800. if (r->com.state != RES_SRQ_ALLOCATED)
  801. err = -EINVAL;
  802. break;
  803. default:
  804. err = -EINVAL;
  805. }
  806. if (!err) {
  807. r->com.from_state = r->com.state;
  808. r->com.to_state = state;
  809. r->com.state = RES_SRQ_BUSY;
  810. if (srq)
  811. *srq = r;
  812. }
  813. }
  814. spin_unlock_irq(mlx4_tlock(dev));
  815. return err;
  816. }
  817. static void res_abort_move(struct mlx4_dev *dev, int slave,
  818. enum mlx4_resource type, int id)
  819. {
  820. struct mlx4_priv *priv = mlx4_priv(dev);
  821. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  822. struct res_common *r;
  823. spin_lock_irq(mlx4_tlock(dev));
  824. r = radix_tree_lookup(&tracker->res_tree[type], id);
  825. if (r && (r->owner == slave))
  826. r->state = r->from_state;
  827. spin_unlock_irq(mlx4_tlock(dev));
  828. }
  829. static void res_end_move(struct mlx4_dev *dev, int slave,
  830. enum mlx4_resource type, int id)
  831. {
  832. struct mlx4_priv *priv = mlx4_priv(dev);
  833. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  834. struct res_common *r;
  835. spin_lock_irq(mlx4_tlock(dev));
  836. r = radix_tree_lookup(&tracker->res_tree[type], id);
  837. if (r && (r->owner == slave))
  838. r->state = r->to_state;
  839. spin_unlock_irq(mlx4_tlock(dev));
  840. }
  841. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  842. {
  843. return mlx4_is_qp_reserved(dev, qpn);
  844. }
  845. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  846. u64 in_param, u64 *out_param)
  847. {
  848. int err;
  849. int count;
  850. int align;
  851. int base;
  852. int qpn;
  853. switch (op) {
  854. case RES_OP_RESERVE:
  855. count = get_param_l(&in_param);
  856. align = get_param_h(&in_param);
  857. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  858. if (err)
  859. return err;
  860. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  861. if (err) {
  862. __mlx4_qp_release_range(dev, base, count);
  863. return err;
  864. }
  865. set_param_l(out_param, base);
  866. break;
  867. case RES_OP_MAP_ICM:
  868. qpn = get_param_l(&in_param) & 0x7fffff;
  869. if (valid_reserved(dev, slave, qpn)) {
  870. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  871. if (err)
  872. return err;
  873. }
  874. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  875. NULL, 1);
  876. if (err)
  877. return err;
  878. if (!valid_reserved(dev, slave, qpn)) {
  879. err = __mlx4_qp_alloc_icm(dev, qpn);
  880. if (err) {
  881. res_abort_move(dev, slave, RES_QP, qpn);
  882. return err;
  883. }
  884. }
  885. res_end_move(dev, slave, RES_QP, qpn);
  886. break;
  887. default:
  888. err = -EINVAL;
  889. break;
  890. }
  891. return err;
  892. }
  893. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  894. u64 in_param, u64 *out_param)
  895. {
  896. int err = -EINVAL;
  897. int base;
  898. int order;
  899. if (op != RES_OP_RESERVE_AND_MAP)
  900. return err;
  901. order = get_param_l(&in_param);
  902. base = __mlx4_alloc_mtt_range(dev, order);
  903. if (base == -1)
  904. return -ENOMEM;
  905. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  906. if (err)
  907. __mlx4_free_mtt_range(dev, base, order);
  908. else
  909. set_param_l(out_param, base);
  910. return err;
  911. }
  912. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  913. u64 in_param, u64 *out_param)
  914. {
  915. int err = -EINVAL;
  916. int index;
  917. int id;
  918. struct res_mpt *mpt;
  919. switch (op) {
  920. case RES_OP_RESERVE:
  921. index = __mlx4_mr_reserve(dev);
  922. if (index == -1)
  923. break;
  924. id = index & mpt_mask(dev);
  925. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  926. if (err) {
  927. __mlx4_mr_release(dev, index);
  928. break;
  929. }
  930. set_param_l(out_param, index);
  931. break;
  932. case RES_OP_MAP_ICM:
  933. index = get_param_l(&in_param);
  934. id = index & mpt_mask(dev);
  935. err = mr_res_start_move_to(dev, slave, id,
  936. RES_MPT_MAPPED, &mpt);
  937. if (err)
  938. return err;
  939. err = __mlx4_mr_alloc_icm(dev, mpt->key);
  940. if (err) {
  941. res_abort_move(dev, slave, RES_MPT, id);
  942. return err;
  943. }
  944. res_end_move(dev, slave, RES_MPT, id);
  945. break;
  946. }
  947. return err;
  948. }
  949. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  950. u64 in_param, u64 *out_param)
  951. {
  952. int cqn;
  953. int err;
  954. switch (op) {
  955. case RES_OP_RESERVE_AND_MAP:
  956. err = __mlx4_cq_alloc_icm(dev, &cqn);
  957. if (err)
  958. break;
  959. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  960. if (err) {
  961. __mlx4_cq_free_icm(dev, cqn);
  962. break;
  963. }
  964. set_param_l(out_param, cqn);
  965. break;
  966. default:
  967. err = -EINVAL;
  968. }
  969. return err;
  970. }
  971. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  972. u64 in_param, u64 *out_param)
  973. {
  974. int srqn;
  975. int err;
  976. switch (op) {
  977. case RES_OP_RESERVE_AND_MAP:
  978. err = __mlx4_srq_alloc_icm(dev, &srqn);
  979. if (err)
  980. break;
  981. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  982. if (err) {
  983. __mlx4_srq_free_icm(dev, srqn);
  984. break;
  985. }
  986. set_param_l(out_param, srqn);
  987. break;
  988. default:
  989. err = -EINVAL;
  990. }
  991. return err;
  992. }
  993. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  994. {
  995. struct mlx4_priv *priv = mlx4_priv(dev);
  996. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  997. struct mac_res *res;
  998. res = kzalloc(sizeof *res, GFP_KERNEL);
  999. if (!res)
  1000. return -ENOMEM;
  1001. res->mac = mac;
  1002. res->port = (u8) port;
  1003. list_add_tail(&res->list,
  1004. &tracker->slave_list[slave].res_list[RES_MAC]);
  1005. return 0;
  1006. }
  1007. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1008. int port)
  1009. {
  1010. struct mlx4_priv *priv = mlx4_priv(dev);
  1011. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1012. struct list_head *mac_list =
  1013. &tracker->slave_list[slave].res_list[RES_MAC];
  1014. struct mac_res *res, *tmp;
  1015. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1016. if (res->mac == mac && res->port == (u8) port) {
  1017. list_del(&res->list);
  1018. kfree(res);
  1019. break;
  1020. }
  1021. }
  1022. }
  1023. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1024. {
  1025. struct mlx4_priv *priv = mlx4_priv(dev);
  1026. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1027. struct list_head *mac_list =
  1028. &tracker->slave_list[slave].res_list[RES_MAC];
  1029. struct mac_res *res, *tmp;
  1030. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1031. list_del(&res->list);
  1032. __mlx4_unregister_mac(dev, res->port, res->mac);
  1033. kfree(res);
  1034. }
  1035. }
  1036. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1037. u64 in_param, u64 *out_param)
  1038. {
  1039. int err = -EINVAL;
  1040. int port;
  1041. u64 mac;
  1042. if (op != RES_OP_RESERVE_AND_MAP)
  1043. return err;
  1044. port = get_param_l(out_param);
  1045. mac = in_param;
  1046. err = __mlx4_register_mac(dev, port, mac);
  1047. if (err >= 0) {
  1048. set_param_l(out_param, err);
  1049. err = 0;
  1050. }
  1051. if (!err) {
  1052. err = mac_add_to_slave(dev, slave, mac, port);
  1053. if (err)
  1054. __mlx4_unregister_mac(dev, port, mac);
  1055. }
  1056. return err;
  1057. }
  1058. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1059. u64 in_param, u64 *out_param)
  1060. {
  1061. return 0;
  1062. }
  1063. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1064. struct mlx4_vhcr *vhcr,
  1065. struct mlx4_cmd_mailbox *inbox,
  1066. struct mlx4_cmd_mailbox *outbox,
  1067. struct mlx4_cmd_info *cmd)
  1068. {
  1069. int err;
  1070. int alop = vhcr->op_modifier;
  1071. switch (vhcr->in_modifier) {
  1072. case RES_QP:
  1073. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1074. vhcr->in_param, &vhcr->out_param);
  1075. break;
  1076. case RES_MTT:
  1077. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1078. vhcr->in_param, &vhcr->out_param);
  1079. break;
  1080. case RES_MPT:
  1081. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1082. vhcr->in_param, &vhcr->out_param);
  1083. break;
  1084. case RES_CQ:
  1085. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1086. vhcr->in_param, &vhcr->out_param);
  1087. break;
  1088. case RES_SRQ:
  1089. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1090. vhcr->in_param, &vhcr->out_param);
  1091. break;
  1092. case RES_MAC:
  1093. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1094. vhcr->in_param, &vhcr->out_param);
  1095. break;
  1096. case RES_VLAN:
  1097. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1098. vhcr->in_param, &vhcr->out_param);
  1099. break;
  1100. default:
  1101. err = -EINVAL;
  1102. break;
  1103. }
  1104. return err;
  1105. }
  1106. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1107. u64 in_param)
  1108. {
  1109. int err;
  1110. int count;
  1111. int base;
  1112. int qpn;
  1113. switch (op) {
  1114. case RES_OP_RESERVE:
  1115. base = get_param_l(&in_param) & 0x7fffff;
  1116. count = get_param_h(&in_param);
  1117. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1118. if (err)
  1119. break;
  1120. __mlx4_qp_release_range(dev, base, count);
  1121. break;
  1122. case RES_OP_MAP_ICM:
  1123. qpn = get_param_l(&in_param) & 0x7fffff;
  1124. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1125. NULL, 0);
  1126. if (err)
  1127. return err;
  1128. if (!valid_reserved(dev, slave, qpn))
  1129. __mlx4_qp_free_icm(dev, qpn);
  1130. res_end_move(dev, slave, RES_QP, qpn);
  1131. if (valid_reserved(dev, slave, qpn))
  1132. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1133. break;
  1134. default:
  1135. err = -EINVAL;
  1136. break;
  1137. }
  1138. return err;
  1139. }
  1140. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1141. u64 in_param, u64 *out_param)
  1142. {
  1143. int err = -EINVAL;
  1144. int base;
  1145. int order;
  1146. if (op != RES_OP_RESERVE_AND_MAP)
  1147. return err;
  1148. base = get_param_l(&in_param);
  1149. order = get_param_h(&in_param);
  1150. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1151. if (!err)
  1152. __mlx4_free_mtt_range(dev, base, order);
  1153. return err;
  1154. }
  1155. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1156. u64 in_param)
  1157. {
  1158. int err = -EINVAL;
  1159. int index;
  1160. int id;
  1161. struct res_mpt *mpt;
  1162. switch (op) {
  1163. case RES_OP_RESERVE:
  1164. index = get_param_l(&in_param);
  1165. id = index & mpt_mask(dev);
  1166. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1167. if (err)
  1168. break;
  1169. index = mpt->key;
  1170. put_res(dev, slave, id, RES_MPT);
  1171. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1172. if (err)
  1173. break;
  1174. __mlx4_mr_release(dev, index);
  1175. break;
  1176. case RES_OP_MAP_ICM:
  1177. index = get_param_l(&in_param);
  1178. id = index & mpt_mask(dev);
  1179. err = mr_res_start_move_to(dev, slave, id,
  1180. RES_MPT_RESERVED, &mpt);
  1181. if (err)
  1182. return err;
  1183. __mlx4_mr_free_icm(dev, mpt->key);
  1184. res_end_move(dev, slave, RES_MPT, id);
  1185. return err;
  1186. break;
  1187. default:
  1188. err = -EINVAL;
  1189. break;
  1190. }
  1191. return err;
  1192. }
  1193. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1194. u64 in_param, u64 *out_param)
  1195. {
  1196. int cqn;
  1197. int err;
  1198. switch (op) {
  1199. case RES_OP_RESERVE_AND_MAP:
  1200. cqn = get_param_l(&in_param);
  1201. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1202. if (err)
  1203. break;
  1204. __mlx4_cq_free_icm(dev, cqn);
  1205. break;
  1206. default:
  1207. err = -EINVAL;
  1208. break;
  1209. }
  1210. return err;
  1211. }
  1212. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1213. u64 in_param, u64 *out_param)
  1214. {
  1215. int srqn;
  1216. int err;
  1217. switch (op) {
  1218. case RES_OP_RESERVE_AND_MAP:
  1219. srqn = get_param_l(&in_param);
  1220. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1221. if (err)
  1222. break;
  1223. __mlx4_srq_free_icm(dev, srqn);
  1224. break;
  1225. default:
  1226. err = -EINVAL;
  1227. break;
  1228. }
  1229. return err;
  1230. }
  1231. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1232. u64 in_param, u64 *out_param)
  1233. {
  1234. int port;
  1235. int err = 0;
  1236. switch (op) {
  1237. case RES_OP_RESERVE_AND_MAP:
  1238. port = get_param_l(out_param);
  1239. mac_del_from_slave(dev, slave, in_param, port);
  1240. __mlx4_unregister_mac(dev, port, in_param);
  1241. break;
  1242. default:
  1243. err = -EINVAL;
  1244. break;
  1245. }
  1246. return err;
  1247. }
  1248. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1249. u64 in_param, u64 *out_param)
  1250. {
  1251. return 0;
  1252. }
  1253. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1254. struct mlx4_vhcr *vhcr,
  1255. struct mlx4_cmd_mailbox *inbox,
  1256. struct mlx4_cmd_mailbox *outbox,
  1257. struct mlx4_cmd_info *cmd)
  1258. {
  1259. int err = -EINVAL;
  1260. int alop = vhcr->op_modifier;
  1261. switch (vhcr->in_modifier) {
  1262. case RES_QP:
  1263. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1264. vhcr->in_param);
  1265. break;
  1266. case RES_MTT:
  1267. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1268. vhcr->in_param, &vhcr->out_param);
  1269. break;
  1270. case RES_MPT:
  1271. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1272. vhcr->in_param);
  1273. break;
  1274. case RES_CQ:
  1275. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1276. vhcr->in_param, &vhcr->out_param);
  1277. break;
  1278. case RES_SRQ:
  1279. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1280. vhcr->in_param, &vhcr->out_param);
  1281. break;
  1282. case RES_MAC:
  1283. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1284. vhcr->in_param, &vhcr->out_param);
  1285. break;
  1286. case RES_VLAN:
  1287. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1288. vhcr->in_param, &vhcr->out_param);
  1289. break;
  1290. default:
  1291. break;
  1292. }
  1293. return err;
  1294. }
  1295. /* ugly but other choices are uglier */
  1296. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1297. {
  1298. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1299. }
  1300. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1301. {
  1302. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1303. }
  1304. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1305. {
  1306. return be32_to_cpu(mpt->mtt_sz);
  1307. }
  1308. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1309. {
  1310. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1311. }
  1312. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1313. {
  1314. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1315. }
  1316. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1317. {
  1318. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1319. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1320. int log_sq_sride = qpc->sq_size_stride & 7;
  1321. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1322. int log_rq_stride = qpc->rq_size_stride & 7;
  1323. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1324. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1325. int xrc = (be32_to_cpu(qpc->local_qpn) >> 23) & 1;
  1326. int sq_size;
  1327. int rq_size;
  1328. int total_pages;
  1329. int total_mem;
  1330. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1331. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1332. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1333. total_mem = sq_size + rq_size;
  1334. total_pages =
  1335. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  1336. page_shift);
  1337. return total_pages;
  1338. }
  1339. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  1340. int size, struct res_mtt *mtt)
  1341. {
  1342. int res_start = mtt->com.res_id;
  1343. int res_size = (1 << mtt->order);
  1344. if (start < res_start || start + size > res_start + res_size)
  1345. return -EPERM;
  1346. return 0;
  1347. }
  1348. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1349. struct mlx4_vhcr *vhcr,
  1350. struct mlx4_cmd_mailbox *inbox,
  1351. struct mlx4_cmd_mailbox *outbox,
  1352. struct mlx4_cmd_info *cmd)
  1353. {
  1354. int err;
  1355. int index = vhcr->in_modifier;
  1356. struct res_mtt *mtt;
  1357. struct res_mpt *mpt;
  1358. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  1359. int phys;
  1360. int id;
  1361. id = index & mpt_mask(dev);
  1362. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  1363. if (err)
  1364. return err;
  1365. phys = mr_phys_mpt(inbox->buf);
  1366. if (!phys) {
  1367. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1368. if (err)
  1369. goto ex_abort;
  1370. err = check_mtt_range(dev, slave, mtt_base,
  1371. mr_get_mtt_size(inbox->buf), mtt);
  1372. if (err)
  1373. goto ex_put;
  1374. mpt->mtt = mtt;
  1375. }
  1376. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1377. if (err)
  1378. goto ex_put;
  1379. if (!phys) {
  1380. atomic_inc(&mtt->ref_count);
  1381. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1382. }
  1383. res_end_move(dev, slave, RES_MPT, id);
  1384. return 0;
  1385. ex_put:
  1386. if (!phys)
  1387. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1388. ex_abort:
  1389. res_abort_move(dev, slave, RES_MPT, id);
  1390. return err;
  1391. }
  1392. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1393. struct mlx4_vhcr *vhcr,
  1394. struct mlx4_cmd_mailbox *inbox,
  1395. struct mlx4_cmd_mailbox *outbox,
  1396. struct mlx4_cmd_info *cmd)
  1397. {
  1398. int err;
  1399. int index = vhcr->in_modifier;
  1400. struct res_mpt *mpt;
  1401. int id;
  1402. id = index & mpt_mask(dev);
  1403. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  1404. if (err)
  1405. return err;
  1406. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1407. if (err)
  1408. goto ex_abort;
  1409. if (mpt->mtt)
  1410. atomic_dec(&mpt->mtt->ref_count);
  1411. res_end_move(dev, slave, RES_MPT, id);
  1412. return 0;
  1413. ex_abort:
  1414. res_abort_move(dev, slave, RES_MPT, id);
  1415. return err;
  1416. }
  1417. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1418. struct mlx4_vhcr *vhcr,
  1419. struct mlx4_cmd_mailbox *inbox,
  1420. struct mlx4_cmd_mailbox *outbox,
  1421. struct mlx4_cmd_info *cmd)
  1422. {
  1423. int err;
  1424. int index = vhcr->in_modifier;
  1425. struct res_mpt *mpt;
  1426. int id;
  1427. id = index & mpt_mask(dev);
  1428. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1429. if (err)
  1430. return err;
  1431. if (mpt->com.from_state != RES_MPT_HW) {
  1432. err = -EBUSY;
  1433. goto out;
  1434. }
  1435. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1436. out:
  1437. put_res(dev, slave, id, RES_MPT);
  1438. return err;
  1439. }
  1440. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  1441. {
  1442. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  1443. }
  1444. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  1445. {
  1446. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  1447. }
  1448. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  1449. {
  1450. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  1451. }
  1452. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  1453. struct mlx4_vhcr *vhcr,
  1454. struct mlx4_cmd_mailbox *inbox,
  1455. struct mlx4_cmd_mailbox *outbox,
  1456. struct mlx4_cmd_info *cmd)
  1457. {
  1458. int err;
  1459. int qpn = vhcr->in_modifier & 0x7fffff;
  1460. struct res_mtt *mtt;
  1461. struct res_qp *qp;
  1462. struct mlx4_qp_context *qpc = inbox->buf + 8;
  1463. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  1464. int mtt_size = qp_get_mtt_size(qpc);
  1465. struct res_cq *rcq;
  1466. struct res_cq *scq;
  1467. int rcqn = qp_get_rcqn(qpc);
  1468. int scqn = qp_get_scqn(qpc);
  1469. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  1470. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  1471. struct res_srq *srq;
  1472. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  1473. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  1474. if (err)
  1475. return err;
  1476. qp->local_qpn = local_qpn;
  1477. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1478. if (err)
  1479. goto ex_abort;
  1480. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1481. if (err)
  1482. goto ex_put_mtt;
  1483. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  1484. if (err)
  1485. goto ex_put_mtt;
  1486. if (scqn != rcqn) {
  1487. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  1488. if (err)
  1489. goto ex_put_rcq;
  1490. } else
  1491. scq = rcq;
  1492. if (use_srq) {
  1493. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1494. if (err)
  1495. goto ex_put_scq;
  1496. }
  1497. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1498. if (err)
  1499. goto ex_put_srq;
  1500. atomic_inc(&mtt->ref_count);
  1501. qp->mtt = mtt;
  1502. atomic_inc(&rcq->ref_count);
  1503. qp->rcq = rcq;
  1504. atomic_inc(&scq->ref_count);
  1505. qp->scq = scq;
  1506. if (scqn != rcqn)
  1507. put_res(dev, slave, scqn, RES_CQ);
  1508. if (use_srq) {
  1509. atomic_inc(&srq->ref_count);
  1510. put_res(dev, slave, srqn, RES_SRQ);
  1511. qp->srq = srq;
  1512. }
  1513. put_res(dev, slave, rcqn, RES_CQ);
  1514. put_res(dev, slave, mtt_base, RES_MTT);
  1515. res_end_move(dev, slave, RES_QP, qpn);
  1516. return 0;
  1517. ex_put_srq:
  1518. if (use_srq)
  1519. put_res(dev, slave, srqn, RES_SRQ);
  1520. ex_put_scq:
  1521. if (scqn != rcqn)
  1522. put_res(dev, slave, scqn, RES_CQ);
  1523. ex_put_rcq:
  1524. put_res(dev, slave, rcqn, RES_CQ);
  1525. ex_put_mtt:
  1526. put_res(dev, slave, mtt_base, RES_MTT);
  1527. ex_abort:
  1528. res_abort_move(dev, slave, RES_QP, qpn);
  1529. return err;
  1530. }
  1531. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  1532. {
  1533. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  1534. }
  1535. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  1536. {
  1537. int log_eq_size = eqc->log_eq_size & 0x1f;
  1538. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  1539. if (log_eq_size + 5 < page_shift)
  1540. return 1;
  1541. return 1 << (log_eq_size + 5 - page_shift);
  1542. }
  1543. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  1544. {
  1545. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  1546. }
  1547. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  1548. {
  1549. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  1550. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  1551. if (log_cq_size + 5 < page_shift)
  1552. return 1;
  1553. return 1 << (log_cq_size + 5 - page_shift);
  1554. }
  1555. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1556. struct mlx4_vhcr *vhcr,
  1557. struct mlx4_cmd_mailbox *inbox,
  1558. struct mlx4_cmd_mailbox *outbox,
  1559. struct mlx4_cmd_info *cmd)
  1560. {
  1561. int err;
  1562. int eqn = vhcr->in_modifier;
  1563. int res_id = (slave << 8) | eqn;
  1564. struct mlx4_eq_context *eqc = inbox->buf;
  1565. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  1566. int mtt_size = eq_get_mtt_size(eqc);
  1567. struct res_eq *eq;
  1568. struct res_mtt *mtt;
  1569. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1570. if (err)
  1571. return err;
  1572. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  1573. if (err)
  1574. goto out_add;
  1575. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1576. if (err)
  1577. goto out_move;
  1578. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1579. if (err)
  1580. goto out_put;
  1581. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1582. if (err)
  1583. goto out_put;
  1584. atomic_inc(&mtt->ref_count);
  1585. eq->mtt = mtt;
  1586. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1587. res_end_move(dev, slave, RES_EQ, res_id);
  1588. return 0;
  1589. out_put:
  1590. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1591. out_move:
  1592. res_abort_move(dev, slave, RES_EQ, res_id);
  1593. out_add:
  1594. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1595. return err;
  1596. }
  1597. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  1598. int len, struct res_mtt **res)
  1599. {
  1600. struct mlx4_priv *priv = mlx4_priv(dev);
  1601. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1602. struct res_mtt *mtt;
  1603. int err = -EINVAL;
  1604. spin_lock_irq(mlx4_tlock(dev));
  1605. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  1606. com.list) {
  1607. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  1608. *res = mtt;
  1609. mtt->com.from_state = mtt->com.state;
  1610. mtt->com.state = RES_MTT_BUSY;
  1611. err = 0;
  1612. break;
  1613. }
  1614. }
  1615. spin_unlock_irq(mlx4_tlock(dev));
  1616. return err;
  1617. }
  1618. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  1619. struct mlx4_vhcr *vhcr,
  1620. struct mlx4_cmd_mailbox *inbox,
  1621. struct mlx4_cmd_mailbox *outbox,
  1622. struct mlx4_cmd_info *cmd)
  1623. {
  1624. struct mlx4_mtt mtt;
  1625. __be64 *page_list = inbox->buf;
  1626. u64 *pg_list = (u64 *)page_list;
  1627. int i;
  1628. struct res_mtt *rmtt = NULL;
  1629. int start = be64_to_cpu(page_list[0]);
  1630. int npages = vhcr->in_modifier;
  1631. int err;
  1632. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  1633. if (err)
  1634. return err;
  1635. /* Call the SW implementation of write_mtt:
  1636. * - Prepare a dummy mtt struct
  1637. * - Translate inbox contents to simple addresses in host endianess */
  1638. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  1639. we don't really use it */
  1640. mtt.order = 0;
  1641. mtt.page_shift = 0;
  1642. for (i = 0; i < npages; ++i)
  1643. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  1644. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  1645. ((u64 *)page_list + 2));
  1646. if (rmtt)
  1647. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  1648. return err;
  1649. }
  1650. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1651. struct mlx4_vhcr *vhcr,
  1652. struct mlx4_cmd_mailbox *inbox,
  1653. struct mlx4_cmd_mailbox *outbox,
  1654. struct mlx4_cmd_info *cmd)
  1655. {
  1656. int eqn = vhcr->in_modifier;
  1657. int res_id = eqn | (slave << 8);
  1658. struct res_eq *eq;
  1659. int err;
  1660. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  1661. if (err)
  1662. return err;
  1663. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  1664. if (err)
  1665. goto ex_abort;
  1666. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1667. if (err)
  1668. goto ex_put;
  1669. atomic_dec(&eq->mtt->ref_count);
  1670. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1671. res_end_move(dev, slave, RES_EQ, res_id);
  1672. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1673. return 0;
  1674. ex_put:
  1675. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1676. ex_abort:
  1677. res_abort_move(dev, slave, RES_EQ, res_id);
  1678. return err;
  1679. }
  1680. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  1681. {
  1682. struct mlx4_priv *priv = mlx4_priv(dev);
  1683. struct mlx4_slave_event_eq_info *event_eq;
  1684. struct mlx4_cmd_mailbox *mailbox;
  1685. u32 in_modifier = 0;
  1686. int err;
  1687. int res_id;
  1688. struct res_eq *req;
  1689. if (!priv->mfunc.master.slave_state)
  1690. return -EINVAL;
  1691. event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
  1692. /* Create the event only if the slave is registered */
  1693. if (event_eq->eqn < 0)
  1694. return 0;
  1695. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1696. res_id = (slave << 8) | event_eq->eqn;
  1697. err = get_res(dev, slave, res_id, RES_EQ, &req);
  1698. if (err)
  1699. goto unlock;
  1700. if (req->com.from_state != RES_EQ_HW) {
  1701. err = -EINVAL;
  1702. goto put;
  1703. }
  1704. mailbox = mlx4_alloc_cmd_mailbox(dev);
  1705. if (IS_ERR(mailbox)) {
  1706. err = PTR_ERR(mailbox);
  1707. goto put;
  1708. }
  1709. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  1710. ++event_eq->token;
  1711. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  1712. }
  1713. memcpy(mailbox->buf, (u8 *) eqe, 28);
  1714. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  1715. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  1716. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  1717. MLX4_CMD_NATIVE);
  1718. put_res(dev, slave, res_id, RES_EQ);
  1719. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1720. mlx4_free_cmd_mailbox(dev, mailbox);
  1721. return err;
  1722. put:
  1723. put_res(dev, slave, res_id, RES_EQ);
  1724. unlock:
  1725. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1726. return err;
  1727. }
  1728. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1729. struct mlx4_vhcr *vhcr,
  1730. struct mlx4_cmd_mailbox *inbox,
  1731. struct mlx4_cmd_mailbox *outbox,
  1732. struct mlx4_cmd_info *cmd)
  1733. {
  1734. int eqn = vhcr->in_modifier;
  1735. int res_id = eqn | (slave << 8);
  1736. struct res_eq *eq;
  1737. int err;
  1738. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  1739. if (err)
  1740. return err;
  1741. if (eq->com.from_state != RES_EQ_HW) {
  1742. err = -EINVAL;
  1743. goto ex_put;
  1744. }
  1745. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1746. ex_put:
  1747. put_res(dev, slave, res_id, RES_EQ);
  1748. return err;
  1749. }
  1750. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1751. struct mlx4_vhcr *vhcr,
  1752. struct mlx4_cmd_mailbox *inbox,
  1753. struct mlx4_cmd_mailbox *outbox,
  1754. struct mlx4_cmd_info *cmd)
  1755. {
  1756. int err;
  1757. int cqn = vhcr->in_modifier;
  1758. struct mlx4_cq_context *cqc = inbox->buf;
  1759. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1760. struct res_cq *cq;
  1761. struct res_mtt *mtt;
  1762. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  1763. if (err)
  1764. return err;
  1765. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1766. if (err)
  1767. goto out_move;
  1768. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1769. if (err)
  1770. goto out_put;
  1771. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1772. if (err)
  1773. goto out_put;
  1774. atomic_inc(&mtt->ref_count);
  1775. cq->mtt = mtt;
  1776. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1777. res_end_move(dev, slave, RES_CQ, cqn);
  1778. return 0;
  1779. out_put:
  1780. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1781. out_move:
  1782. res_abort_move(dev, slave, RES_CQ, cqn);
  1783. return err;
  1784. }
  1785. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1786. struct mlx4_vhcr *vhcr,
  1787. struct mlx4_cmd_mailbox *inbox,
  1788. struct mlx4_cmd_mailbox *outbox,
  1789. struct mlx4_cmd_info *cmd)
  1790. {
  1791. int err;
  1792. int cqn = vhcr->in_modifier;
  1793. struct res_cq *cq;
  1794. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  1795. if (err)
  1796. return err;
  1797. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1798. if (err)
  1799. goto out_move;
  1800. atomic_dec(&cq->mtt->ref_count);
  1801. res_end_move(dev, slave, RES_CQ, cqn);
  1802. return 0;
  1803. out_move:
  1804. res_abort_move(dev, slave, RES_CQ, cqn);
  1805. return err;
  1806. }
  1807. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1808. struct mlx4_vhcr *vhcr,
  1809. struct mlx4_cmd_mailbox *inbox,
  1810. struct mlx4_cmd_mailbox *outbox,
  1811. struct mlx4_cmd_info *cmd)
  1812. {
  1813. int cqn = vhcr->in_modifier;
  1814. struct res_cq *cq;
  1815. int err;
  1816. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  1817. if (err)
  1818. return err;
  1819. if (cq->com.from_state != RES_CQ_HW)
  1820. goto ex_put;
  1821. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1822. ex_put:
  1823. put_res(dev, slave, cqn, RES_CQ);
  1824. return err;
  1825. }
  1826. static int handle_resize(struct mlx4_dev *dev, int slave,
  1827. struct mlx4_vhcr *vhcr,
  1828. struct mlx4_cmd_mailbox *inbox,
  1829. struct mlx4_cmd_mailbox *outbox,
  1830. struct mlx4_cmd_info *cmd,
  1831. struct res_cq *cq)
  1832. {
  1833. int err;
  1834. struct res_mtt *orig_mtt;
  1835. struct res_mtt *mtt;
  1836. struct mlx4_cq_context *cqc = inbox->buf;
  1837. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1838. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  1839. if (err)
  1840. return err;
  1841. if (orig_mtt != cq->mtt) {
  1842. err = -EINVAL;
  1843. goto ex_put;
  1844. }
  1845. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1846. if (err)
  1847. goto ex_put;
  1848. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1849. if (err)
  1850. goto ex_put1;
  1851. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1852. if (err)
  1853. goto ex_put1;
  1854. atomic_dec(&orig_mtt->ref_count);
  1855. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  1856. atomic_inc(&mtt->ref_count);
  1857. cq->mtt = mtt;
  1858. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1859. return 0;
  1860. ex_put1:
  1861. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1862. ex_put:
  1863. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  1864. return err;
  1865. }
  1866. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1867. struct mlx4_vhcr *vhcr,
  1868. struct mlx4_cmd_mailbox *inbox,
  1869. struct mlx4_cmd_mailbox *outbox,
  1870. struct mlx4_cmd_info *cmd)
  1871. {
  1872. int cqn = vhcr->in_modifier;
  1873. struct res_cq *cq;
  1874. int err;
  1875. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  1876. if (err)
  1877. return err;
  1878. if (cq->com.from_state != RES_CQ_HW)
  1879. goto ex_put;
  1880. if (vhcr->op_modifier == 0) {
  1881. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  1882. goto ex_put;
  1883. }
  1884. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1885. ex_put:
  1886. put_res(dev, slave, cqn, RES_CQ);
  1887. return err;
  1888. }
  1889. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  1890. {
  1891. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  1892. int log_rq_stride = srqc->logstride & 7;
  1893. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  1894. if (log_srq_size + log_rq_stride + 4 < page_shift)
  1895. return 1;
  1896. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  1897. }
  1898. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1899. struct mlx4_vhcr *vhcr,
  1900. struct mlx4_cmd_mailbox *inbox,
  1901. struct mlx4_cmd_mailbox *outbox,
  1902. struct mlx4_cmd_info *cmd)
  1903. {
  1904. int err;
  1905. int srqn = vhcr->in_modifier;
  1906. struct res_mtt *mtt;
  1907. struct res_srq *srq;
  1908. struct mlx4_srq_context *srqc = inbox->buf;
  1909. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  1910. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  1911. return -EINVAL;
  1912. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  1913. if (err)
  1914. return err;
  1915. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1916. if (err)
  1917. goto ex_abort;
  1918. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  1919. mtt);
  1920. if (err)
  1921. goto ex_put_mtt;
  1922. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1923. if (err)
  1924. goto ex_put_mtt;
  1925. atomic_inc(&mtt->ref_count);
  1926. srq->mtt = mtt;
  1927. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1928. res_end_move(dev, slave, RES_SRQ, srqn);
  1929. return 0;
  1930. ex_put_mtt:
  1931. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1932. ex_abort:
  1933. res_abort_move(dev, slave, RES_SRQ, srqn);
  1934. return err;
  1935. }
  1936. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1937. struct mlx4_vhcr *vhcr,
  1938. struct mlx4_cmd_mailbox *inbox,
  1939. struct mlx4_cmd_mailbox *outbox,
  1940. struct mlx4_cmd_info *cmd)
  1941. {
  1942. int err;
  1943. int srqn = vhcr->in_modifier;
  1944. struct res_srq *srq;
  1945. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  1946. if (err)
  1947. return err;
  1948. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1949. if (err)
  1950. goto ex_abort;
  1951. atomic_dec(&srq->mtt->ref_count);
  1952. if (srq->cq)
  1953. atomic_dec(&srq->cq->ref_count);
  1954. res_end_move(dev, slave, RES_SRQ, srqn);
  1955. return 0;
  1956. ex_abort:
  1957. res_abort_move(dev, slave, RES_SRQ, srqn);
  1958. return err;
  1959. }
  1960. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1961. struct mlx4_vhcr *vhcr,
  1962. struct mlx4_cmd_mailbox *inbox,
  1963. struct mlx4_cmd_mailbox *outbox,
  1964. struct mlx4_cmd_info *cmd)
  1965. {
  1966. int err;
  1967. int srqn = vhcr->in_modifier;
  1968. struct res_srq *srq;
  1969. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1970. if (err)
  1971. return err;
  1972. if (srq->com.from_state != RES_SRQ_HW) {
  1973. err = -EBUSY;
  1974. goto out;
  1975. }
  1976. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1977. out:
  1978. put_res(dev, slave, srqn, RES_SRQ);
  1979. return err;
  1980. }
  1981. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1982. struct mlx4_vhcr *vhcr,
  1983. struct mlx4_cmd_mailbox *inbox,
  1984. struct mlx4_cmd_mailbox *outbox,
  1985. struct mlx4_cmd_info *cmd)
  1986. {
  1987. int err;
  1988. int srqn = vhcr->in_modifier;
  1989. struct res_srq *srq;
  1990. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1991. if (err)
  1992. return err;
  1993. if (srq->com.from_state != RES_SRQ_HW) {
  1994. err = -EBUSY;
  1995. goto out;
  1996. }
  1997. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1998. out:
  1999. put_res(dev, slave, srqn, RES_SRQ);
  2000. return err;
  2001. }
  2002. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2003. struct mlx4_vhcr *vhcr,
  2004. struct mlx4_cmd_mailbox *inbox,
  2005. struct mlx4_cmd_mailbox *outbox,
  2006. struct mlx4_cmd_info *cmd)
  2007. {
  2008. int err;
  2009. int qpn = vhcr->in_modifier & 0x7fffff;
  2010. struct res_qp *qp;
  2011. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2012. if (err)
  2013. return err;
  2014. if (qp->com.from_state != RES_QP_HW) {
  2015. err = -EBUSY;
  2016. goto out;
  2017. }
  2018. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2019. out:
  2020. put_res(dev, slave, qpn, RES_QP);
  2021. return err;
  2022. }
  2023. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2024. struct mlx4_vhcr *vhcr,
  2025. struct mlx4_cmd_mailbox *inbox,
  2026. struct mlx4_cmd_mailbox *outbox,
  2027. struct mlx4_cmd_info *cmd)
  2028. {
  2029. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2030. update_ud_gid(dev, qpc, (u8)slave);
  2031. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2032. }
  2033. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2034. struct mlx4_vhcr *vhcr,
  2035. struct mlx4_cmd_mailbox *inbox,
  2036. struct mlx4_cmd_mailbox *outbox,
  2037. struct mlx4_cmd_info *cmd)
  2038. {
  2039. int err;
  2040. int qpn = vhcr->in_modifier & 0x7fffff;
  2041. struct res_qp *qp;
  2042. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2043. if (err)
  2044. return err;
  2045. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2046. if (err)
  2047. goto ex_abort;
  2048. atomic_dec(&qp->mtt->ref_count);
  2049. atomic_dec(&qp->rcq->ref_count);
  2050. atomic_dec(&qp->scq->ref_count);
  2051. if (qp->srq)
  2052. atomic_dec(&qp->srq->ref_count);
  2053. res_end_move(dev, slave, RES_QP, qpn);
  2054. return 0;
  2055. ex_abort:
  2056. res_abort_move(dev, slave, RES_QP, qpn);
  2057. return err;
  2058. }
  2059. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2060. struct res_qp *rqp, u8 *gid)
  2061. {
  2062. struct res_gid *res;
  2063. list_for_each_entry(res, &rqp->mcg_list, list) {
  2064. if (!memcmp(res->gid, gid, 16))
  2065. return res;
  2066. }
  2067. return NULL;
  2068. }
  2069. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2070. u8 *gid, enum mlx4_protocol prot,
  2071. enum mlx4_steer_type steer)
  2072. {
  2073. struct res_gid *res;
  2074. int err;
  2075. res = kzalloc(sizeof *res, GFP_KERNEL);
  2076. if (!res)
  2077. return -ENOMEM;
  2078. spin_lock_irq(&rqp->mcg_spl);
  2079. if (find_gid(dev, slave, rqp, gid)) {
  2080. kfree(res);
  2081. err = -EEXIST;
  2082. } else {
  2083. memcpy(res->gid, gid, 16);
  2084. res->prot = prot;
  2085. res->steer = steer;
  2086. list_add_tail(&res->list, &rqp->mcg_list);
  2087. err = 0;
  2088. }
  2089. spin_unlock_irq(&rqp->mcg_spl);
  2090. return err;
  2091. }
  2092. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2093. u8 *gid, enum mlx4_protocol prot,
  2094. enum mlx4_steer_type steer)
  2095. {
  2096. struct res_gid *res;
  2097. int err;
  2098. spin_lock_irq(&rqp->mcg_spl);
  2099. res = find_gid(dev, slave, rqp, gid);
  2100. if (!res || res->prot != prot || res->steer != steer)
  2101. err = -EINVAL;
  2102. else {
  2103. list_del(&res->list);
  2104. kfree(res);
  2105. err = 0;
  2106. }
  2107. spin_unlock_irq(&rqp->mcg_spl);
  2108. return err;
  2109. }
  2110. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2111. struct mlx4_vhcr *vhcr,
  2112. struct mlx4_cmd_mailbox *inbox,
  2113. struct mlx4_cmd_mailbox *outbox,
  2114. struct mlx4_cmd_info *cmd)
  2115. {
  2116. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2117. u8 *gid = inbox->buf;
  2118. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  2119. int err, err1;
  2120. int qpn;
  2121. struct res_qp *rqp;
  2122. int attach = vhcr->op_modifier;
  2123. int block_loopback = vhcr->in_modifier >> 31;
  2124. u8 steer_type_mask = 2;
  2125. enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
  2126. qpn = vhcr->in_modifier & 0xffffff;
  2127. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2128. if (err)
  2129. return err;
  2130. qp.qpn = qpn;
  2131. if (attach) {
  2132. err = add_mcg_res(dev, slave, rqp, gid, prot, type);
  2133. if (err)
  2134. goto ex_put;
  2135. err = mlx4_qp_attach_common(dev, &qp, gid,
  2136. block_loopback, prot, type);
  2137. if (err)
  2138. goto ex_rem;
  2139. } else {
  2140. err = rem_mcg_res(dev, slave, rqp, gid, prot, type);
  2141. if (err)
  2142. goto ex_put;
  2143. err = mlx4_qp_detach_common(dev, &qp, gid, prot, type);
  2144. }
  2145. put_res(dev, slave, qpn, RES_QP);
  2146. return 0;
  2147. ex_rem:
  2148. /* ignore error return below, already in error */
  2149. err1 = rem_mcg_res(dev, slave, rqp, gid, prot, type);
  2150. ex_put:
  2151. put_res(dev, slave, qpn, RES_QP);
  2152. return err;
  2153. }
  2154. enum {
  2155. BUSY_MAX_RETRIES = 10
  2156. };
  2157. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  2158. struct mlx4_vhcr *vhcr,
  2159. struct mlx4_cmd_mailbox *inbox,
  2160. struct mlx4_cmd_mailbox *outbox,
  2161. struct mlx4_cmd_info *cmd)
  2162. {
  2163. int err;
  2164. int index = vhcr->in_modifier & 0xffff;
  2165. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  2166. if (err)
  2167. return err;
  2168. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2169. put_res(dev, slave, index, RES_COUNTER);
  2170. return err;
  2171. }
  2172. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  2173. {
  2174. struct res_gid *rgid;
  2175. struct res_gid *tmp;
  2176. int err;
  2177. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2178. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  2179. qp.qpn = rqp->local_qpn;
  2180. err = mlx4_qp_detach_common(dev, &qp, rgid->gid, rgid->prot,
  2181. rgid->steer);
  2182. list_del(&rgid->list);
  2183. kfree(rgid);
  2184. }
  2185. }
  2186. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  2187. enum mlx4_resource type, int print)
  2188. {
  2189. struct mlx4_priv *priv = mlx4_priv(dev);
  2190. struct mlx4_resource_tracker *tracker =
  2191. &priv->mfunc.master.res_tracker;
  2192. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  2193. struct res_common *r;
  2194. struct res_common *tmp;
  2195. int busy;
  2196. busy = 0;
  2197. spin_lock_irq(mlx4_tlock(dev));
  2198. list_for_each_entry_safe(r, tmp, rlist, list) {
  2199. if (r->owner == slave) {
  2200. if (!r->removing) {
  2201. if (r->state == RES_ANY_BUSY) {
  2202. if (print)
  2203. mlx4_dbg(dev,
  2204. "%s id 0x%x is busy\n",
  2205. ResourceType(type),
  2206. r->res_id);
  2207. ++busy;
  2208. } else {
  2209. r->from_state = r->state;
  2210. r->state = RES_ANY_BUSY;
  2211. r->removing = 1;
  2212. }
  2213. }
  2214. }
  2215. }
  2216. spin_unlock_irq(mlx4_tlock(dev));
  2217. return busy;
  2218. }
  2219. static int move_all_busy(struct mlx4_dev *dev, int slave,
  2220. enum mlx4_resource type)
  2221. {
  2222. unsigned long begin;
  2223. int busy;
  2224. begin = jiffies;
  2225. do {
  2226. busy = _move_all_busy(dev, slave, type, 0);
  2227. if (time_after(jiffies, begin + 5 * HZ))
  2228. break;
  2229. if (busy)
  2230. cond_resched();
  2231. } while (busy);
  2232. if (busy)
  2233. busy = _move_all_busy(dev, slave, type, 1);
  2234. return busy;
  2235. }
  2236. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  2237. {
  2238. struct mlx4_priv *priv = mlx4_priv(dev);
  2239. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2240. struct list_head *qp_list =
  2241. &tracker->slave_list[slave].res_list[RES_QP];
  2242. struct res_qp *qp;
  2243. struct res_qp *tmp;
  2244. int state;
  2245. u64 in_param;
  2246. int qpn;
  2247. int err;
  2248. err = move_all_busy(dev, slave, RES_QP);
  2249. if (err)
  2250. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  2251. "for slave %d\n", slave);
  2252. spin_lock_irq(mlx4_tlock(dev));
  2253. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  2254. spin_unlock_irq(mlx4_tlock(dev));
  2255. if (qp->com.owner == slave) {
  2256. qpn = qp->com.res_id;
  2257. detach_qp(dev, slave, qp);
  2258. state = qp->com.from_state;
  2259. while (state != 0) {
  2260. switch (state) {
  2261. case RES_QP_RESERVED:
  2262. spin_lock_irq(mlx4_tlock(dev));
  2263. radix_tree_delete(&tracker->res_tree[RES_QP],
  2264. qp->com.res_id);
  2265. list_del(&qp->com.list);
  2266. spin_unlock_irq(mlx4_tlock(dev));
  2267. kfree(qp);
  2268. state = 0;
  2269. break;
  2270. case RES_QP_MAPPED:
  2271. if (!valid_reserved(dev, slave, qpn))
  2272. __mlx4_qp_free_icm(dev, qpn);
  2273. state = RES_QP_RESERVED;
  2274. break;
  2275. case RES_QP_HW:
  2276. in_param = slave;
  2277. err = mlx4_cmd(dev, in_param,
  2278. qp->local_qpn, 2,
  2279. MLX4_CMD_2RST_QP,
  2280. MLX4_CMD_TIME_CLASS_A,
  2281. MLX4_CMD_NATIVE);
  2282. if (err)
  2283. mlx4_dbg(dev, "rem_slave_qps: failed"
  2284. " to move slave %d qpn %d to"
  2285. " reset\n", slave,
  2286. qp->local_qpn);
  2287. atomic_dec(&qp->rcq->ref_count);
  2288. atomic_dec(&qp->scq->ref_count);
  2289. atomic_dec(&qp->mtt->ref_count);
  2290. if (qp->srq)
  2291. atomic_dec(&qp->srq->ref_count);
  2292. state = RES_QP_MAPPED;
  2293. break;
  2294. default:
  2295. state = 0;
  2296. }
  2297. }
  2298. }
  2299. spin_lock_irq(mlx4_tlock(dev));
  2300. }
  2301. spin_unlock_irq(mlx4_tlock(dev));
  2302. }
  2303. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  2304. {
  2305. struct mlx4_priv *priv = mlx4_priv(dev);
  2306. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2307. struct list_head *srq_list =
  2308. &tracker->slave_list[slave].res_list[RES_SRQ];
  2309. struct res_srq *srq;
  2310. struct res_srq *tmp;
  2311. int state;
  2312. u64 in_param;
  2313. LIST_HEAD(tlist);
  2314. int srqn;
  2315. int err;
  2316. err = move_all_busy(dev, slave, RES_SRQ);
  2317. if (err)
  2318. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  2319. "busy for slave %d\n", slave);
  2320. spin_lock_irq(mlx4_tlock(dev));
  2321. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  2322. spin_unlock_irq(mlx4_tlock(dev));
  2323. if (srq->com.owner == slave) {
  2324. srqn = srq->com.res_id;
  2325. state = srq->com.from_state;
  2326. while (state != 0) {
  2327. switch (state) {
  2328. case RES_SRQ_ALLOCATED:
  2329. __mlx4_srq_free_icm(dev, srqn);
  2330. spin_lock_irq(mlx4_tlock(dev));
  2331. radix_tree_delete(&tracker->res_tree[RES_SRQ],
  2332. srqn);
  2333. list_del(&srq->com.list);
  2334. spin_unlock_irq(mlx4_tlock(dev));
  2335. kfree(srq);
  2336. state = 0;
  2337. break;
  2338. case RES_SRQ_HW:
  2339. in_param = slave;
  2340. err = mlx4_cmd(dev, in_param, srqn, 1,
  2341. MLX4_CMD_HW2SW_SRQ,
  2342. MLX4_CMD_TIME_CLASS_A,
  2343. MLX4_CMD_NATIVE);
  2344. if (err)
  2345. mlx4_dbg(dev, "rem_slave_srqs: failed"
  2346. " to move slave %d srq %d to"
  2347. " SW ownership\n",
  2348. slave, srqn);
  2349. atomic_dec(&srq->mtt->ref_count);
  2350. if (srq->cq)
  2351. atomic_dec(&srq->cq->ref_count);
  2352. state = RES_SRQ_ALLOCATED;
  2353. break;
  2354. default:
  2355. state = 0;
  2356. }
  2357. }
  2358. }
  2359. spin_lock_irq(mlx4_tlock(dev));
  2360. }
  2361. spin_unlock_irq(mlx4_tlock(dev));
  2362. }
  2363. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  2364. {
  2365. struct mlx4_priv *priv = mlx4_priv(dev);
  2366. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2367. struct list_head *cq_list =
  2368. &tracker->slave_list[slave].res_list[RES_CQ];
  2369. struct res_cq *cq;
  2370. struct res_cq *tmp;
  2371. int state;
  2372. u64 in_param;
  2373. LIST_HEAD(tlist);
  2374. int cqn;
  2375. int err;
  2376. err = move_all_busy(dev, slave, RES_CQ);
  2377. if (err)
  2378. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  2379. "busy for slave %d\n", slave);
  2380. spin_lock_irq(mlx4_tlock(dev));
  2381. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  2382. spin_unlock_irq(mlx4_tlock(dev));
  2383. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  2384. cqn = cq->com.res_id;
  2385. state = cq->com.from_state;
  2386. while (state != 0) {
  2387. switch (state) {
  2388. case RES_CQ_ALLOCATED:
  2389. __mlx4_cq_free_icm(dev, cqn);
  2390. spin_lock_irq(mlx4_tlock(dev));
  2391. radix_tree_delete(&tracker->res_tree[RES_CQ],
  2392. cqn);
  2393. list_del(&cq->com.list);
  2394. spin_unlock_irq(mlx4_tlock(dev));
  2395. kfree(cq);
  2396. state = 0;
  2397. break;
  2398. case RES_CQ_HW:
  2399. in_param = slave;
  2400. err = mlx4_cmd(dev, in_param, cqn, 1,
  2401. MLX4_CMD_HW2SW_CQ,
  2402. MLX4_CMD_TIME_CLASS_A,
  2403. MLX4_CMD_NATIVE);
  2404. if (err)
  2405. mlx4_dbg(dev, "rem_slave_cqs: failed"
  2406. " to move slave %d cq %d to"
  2407. " SW ownership\n",
  2408. slave, cqn);
  2409. atomic_dec(&cq->mtt->ref_count);
  2410. state = RES_CQ_ALLOCATED;
  2411. break;
  2412. default:
  2413. state = 0;
  2414. }
  2415. }
  2416. }
  2417. spin_lock_irq(mlx4_tlock(dev));
  2418. }
  2419. spin_unlock_irq(mlx4_tlock(dev));
  2420. }
  2421. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  2422. {
  2423. struct mlx4_priv *priv = mlx4_priv(dev);
  2424. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2425. struct list_head *mpt_list =
  2426. &tracker->slave_list[slave].res_list[RES_MPT];
  2427. struct res_mpt *mpt;
  2428. struct res_mpt *tmp;
  2429. int state;
  2430. u64 in_param;
  2431. LIST_HEAD(tlist);
  2432. int mptn;
  2433. int err;
  2434. err = move_all_busy(dev, slave, RES_MPT);
  2435. if (err)
  2436. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  2437. "busy for slave %d\n", slave);
  2438. spin_lock_irq(mlx4_tlock(dev));
  2439. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  2440. spin_unlock_irq(mlx4_tlock(dev));
  2441. if (mpt->com.owner == slave) {
  2442. mptn = mpt->com.res_id;
  2443. state = mpt->com.from_state;
  2444. while (state != 0) {
  2445. switch (state) {
  2446. case RES_MPT_RESERVED:
  2447. __mlx4_mr_release(dev, mpt->key);
  2448. spin_lock_irq(mlx4_tlock(dev));
  2449. radix_tree_delete(&tracker->res_tree[RES_MPT],
  2450. mptn);
  2451. list_del(&mpt->com.list);
  2452. spin_unlock_irq(mlx4_tlock(dev));
  2453. kfree(mpt);
  2454. state = 0;
  2455. break;
  2456. case RES_MPT_MAPPED:
  2457. __mlx4_mr_free_icm(dev, mpt->key);
  2458. state = RES_MPT_RESERVED;
  2459. break;
  2460. case RES_MPT_HW:
  2461. in_param = slave;
  2462. err = mlx4_cmd(dev, in_param, mptn, 0,
  2463. MLX4_CMD_HW2SW_MPT,
  2464. MLX4_CMD_TIME_CLASS_A,
  2465. MLX4_CMD_NATIVE);
  2466. if (err)
  2467. mlx4_dbg(dev, "rem_slave_mrs: failed"
  2468. " to move slave %d mpt %d to"
  2469. " SW ownership\n",
  2470. slave, mptn);
  2471. if (mpt->mtt)
  2472. atomic_dec(&mpt->mtt->ref_count);
  2473. state = RES_MPT_MAPPED;
  2474. break;
  2475. default:
  2476. state = 0;
  2477. }
  2478. }
  2479. }
  2480. spin_lock_irq(mlx4_tlock(dev));
  2481. }
  2482. spin_unlock_irq(mlx4_tlock(dev));
  2483. }
  2484. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  2485. {
  2486. struct mlx4_priv *priv = mlx4_priv(dev);
  2487. struct mlx4_resource_tracker *tracker =
  2488. &priv->mfunc.master.res_tracker;
  2489. struct list_head *mtt_list =
  2490. &tracker->slave_list[slave].res_list[RES_MTT];
  2491. struct res_mtt *mtt;
  2492. struct res_mtt *tmp;
  2493. int state;
  2494. LIST_HEAD(tlist);
  2495. int base;
  2496. int err;
  2497. err = move_all_busy(dev, slave, RES_MTT);
  2498. if (err)
  2499. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  2500. "busy for slave %d\n", slave);
  2501. spin_lock_irq(mlx4_tlock(dev));
  2502. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  2503. spin_unlock_irq(mlx4_tlock(dev));
  2504. if (mtt->com.owner == slave) {
  2505. base = mtt->com.res_id;
  2506. state = mtt->com.from_state;
  2507. while (state != 0) {
  2508. switch (state) {
  2509. case RES_MTT_ALLOCATED:
  2510. __mlx4_free_mtt_range(dev, base,
  2511. mtt->order);
  2512. spin_lock_irq(mlx4_tlock(dev));
  2513. radix_tree_delete(&tracker->res_tree[RES_MTT],
  2514. base);
  2515. list_del(&mtt->com.list);
  2516. spin_unlock_irq(mlx4_tlock(dev));
  2517. kfree(mtt);
  2518. state = 0;
  2519. break;
  2520. default:
  2521. state = 0;
  2522. }
  2523. }
  2524. }
  2525. spin_lock_irq(mlx4_tlock(dev));
  2526. }
  2527. spin_unlock_irq(mlx4_tlock(dev));
  2528. }
  2529. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  2530. {
  2531. struct mlx4_priv *priv = mlx4_priv(dev);
  2532. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2533. struct list_head *eq_list =
  2534. &tracker->slave_list[slave].res_list[RES_EQ];
  2535. struct res_eq *eq;
  2536. struct res_eq *tmp;
  2537. int err;
  2538. int state;
  2539. LIST_HEAD(tlist);
  2540. int eqn;
  2541. struct mlx4_cmd_mailbox *mailbox;
  2542. err = move_all_busy(dev, slave, RES_EQ);
  2543. if (err)
  2544. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  2545. "busy for slave %d\n", slave);
  2546. spin_lock_irq(mlx4_tlock(dev));
  2547. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  2548. spin_unlock_irq(mlx4_tlock(dev));
  2549. if (eq->com.owner == slave) {
  2550. eqn = eq->com.res_id;
  2551. state = eq->com.from_state;
  2552. while (state != 0) {
  2553. switch (state) {
  2554. case RES_EQ_RESERVED:
  2555. spin_lock_irq(mlx4_tlock(dev));
  2556. radix_tree_delete(&tracker->res_tree[RES_EQ],
  2557. eqn);
  2558. list_del(&eq->com.list);
  2559. spin_unlock_irq(mlx4_tlock(dev));
  2560. kfree(eq);
  2561. state = 0;
  2562. break;
  2563. case RES_EQ_HW:
  2564. mailbox = mlx4_alloc_cmd_mailbox(dev);
  2565. if (IS_ERR(mailbox)) {
  2566. cond_resched();
  2567. continue;
  2568. }
  2569. err = mlx4_cmd_box(dev, slave, 0,
  2570. eqn & 0xff, 0,
  2571. MLX4_CMD_HW2SW_EQ,
  2572. MLX4_CMD_TIME_CLASS_A,
  2573. MLX4_CMD_NATIVE);
  2574. mlx4_dbg(dev, "rem_slave_eqs: failed"
  2575. " to move slave %d eqs %d to"
  2576. " SW ownership\n", slave, eqn);
  2577. mlx4_free_cmd_mailbox(dev, mailbox);
  2578. if (!err) {
  2579. atomic_dec(&eq->mtt->ref_count);
  2580. state = RES_EQ_RESERVED;
  2581. }
  2582. break;
  2583. default:
  2584. state = 0;
  2585. }
  2586. }
  2587. }
  2588. spin_lock_irq(mlx4_tlock(dev));
  2589. }
  2590. spin_unlock_irq(mlx4_tlock(dev));
  2591. }
  2592. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  2593. {
  2594. struct mlx4_priv *priv = mlx4_priv(dev);
  2595. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2596. /*VLAN*/
  2597. rem_slave_macs(dev, slave);
  2598. rem_slave_qps(dev, slave);
  2599. rem_slave_srqs(dev, slave);
  2600. rem_slave_cqs(dev, slave);
  2601. rem_slave_mrs(dev, slave);
  2602. rem_slave_eqs(dev, slave);
  2603. rem_slave_mtts(dev, slave);
  2604. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2605. }