macb.c 36 KB

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  1. /*
  2. * Cadence MACB/GEM Ethernet Controller driver
  3. *
  4. * Copyright (C) 2004-2006 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  11. #include <linux/clk.h>
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/kernel.h>
  15. #include <linux/types.h>
  16. #include <linux/slab.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/netdevice.h>
  20. #include <linux/etherdevice.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/platform_data/macb.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/phy.h>
  25. #include <linux/of.h>
  26. #include <linux/of_device.h>
  27. #include <linux/of_net.h>
  28. #include "macb.h"
  29. #define RX_BUFFER_SIZE 128
  30. #define RX_RING_SIZE 512
  31. #define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE)
  32. /* Make the IP header word-aligned (the ethernet header is 14 bytes) */
  33. #define RX_OFFSET 2
  34. #define TX_RING_SIZE 128
  35. #define DEF_TX_RING_PENDING (TX_RING_SIZE - 1)
  36. #define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE)
  37. #define TX_RING_GAP(bp) \
  38. (TX_RING_SIZE - (bp)->tx_pending)
  39. #define TX_BUFFS_AVAIL(bp) \
  40. (((bp)->tx_tail <= (bp)->tx_head) ? \
  41. (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \
  42. (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
  43. #define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1))
  44. #define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1))
  45. /* minimum number of free TX descriptors before waking up TX process */
  46. #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
  47. #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
  48. | MACB_BIT(ISR_ROVR))
  49. static void __macb_set_hwaddr(struct macb *bp)
  50. {
  51. u32 bottom;
  52. u16 top;
  53. bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
  54. macb_or_gem_writel(bp, SA1B, bottom);
  55. top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
  56. macb_or_gem_writel(bp, SA1T, top);
  57. }
  58. static void __init macb_get_hwaddr(struct macb *bp)
  59. {
  60. u32 bottom;
  61. u16 top;
  62. u8 addr[6];
  63. bottom = macb_or_gem_readl(bp, SA1B);
  64. top = macb_or_gem_readl(bp, SA1T);
  65. addr[0] = bottom & 0xff;
  66. addr[1] = (bottom >> 8) & 0xff;
  67. addr[2] = (bottom >> 16) & 0xff;
  68. addr[3] = (bottom >> 24) & 0xff;
  69. addr[4] = top & 0xff;
  70. addr[5] = (top >> 8) & 0xff;
  71. if (is_valid_ether_addr(addr)) {
  72. memcpy(bp->dev->dev_addr, addr, sizeof(addr));
  73. } else {
  74. netdev_info(bp->dev, "invalid hw address, using random\n");
  75. eth_hw_addr_random(bp->dev);
  76. }
  77. }
  78. static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
  79. {
  80. struct macb *bp = bus->priv;
  81. int value;
  82. macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
  83. | MACB_BF(RW, MACB_MAN_READ)
  84. | MACB_BF(PHYA, mii_id)
  85. | MACB_BF(REGA, regnum)
  86. | MACB_BF(CODE, MACB_MAN_CODE)));
  87. /* wait for end of transfer */
  88. while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
  89. cpu_relax();
  90. value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
  91. return value;
  92. }
  93. static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
  94. u16 value)
  95. {
  96. struct macb *bp = bus->priv;
  97. macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
  98. | MACB_BF(RW, MACB_MAN_WRITE)
  99. | MACB_BF(PHYA, mii_id)
  100. | MACB_BF(REGA, regnum)
  101. | MACB_BF(CODE, MACB_MAN_CODE)
  102. | MACB_BF(DATA, value)));
  103. /* wait for end of transfer */
  104. while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
  105. cpu_relax();
  106. return 0;
  107. }
  108. static int macb_mdio_reset(struct mii_bus *bus)
  109. {
  110. return 0;
  111. }
  112. static void macb_handle_link_change(struct net_device *dev)
  113. {
  114. struct macb *bp = netdev_priv(dev);
  115. struct phy_device *phydev = bp->phy_dev;
  116. unsigned long flags;
  117. int status_change = 0;
  118. spin_lock_irqsave(&bp->lock, flags);
  119. if (phydev->link) {
  120. if ((bp->speed != phydev->speed) ||
  121. (bp->duplex != phydev->duplex)) {
  122. u32 reg;
  123. reg = macb_readl(bp, NCFGR);
  124. reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
  125. if (phydev->duplex)
  126. reg |= MACB_BIT(FD);
  127. if (phydev->speed == SPEED_100)
  128. reg |= MACB_BIT(SPD);
  129. macb_writel(bp, NCFGR, reg);
  130. bp->speed = phydev->speed;
  131. bp->duplex = phydev->duplex;
  132. status_change = 1;
  133. }
  134. }
  135. if (phydev->link != bp->link) {
  136. if (!phydev->link) {
  137. bp->speed = 0;
  138. bp->duplex = -1;
  139. }
  140. bp->link = phydev->link;
  141. status_change = 1;
  142. }
  143. spin_unlock_irqrestore(&bp->lock, flags);
  144. if (status_change) {
  145. if (phydev->link)
  146. netdev_info(dev, "link up (%d/%s)\n",
  147. phydev->speed,
  148. phydev->duplex == DUPLEX_FULL ?
  149. "Full" : "Half");
  150. else
  151. netdev_info(dev, "link down\n");
  152. }
  153. }
  154. /* based on au1000_eth. c*/
  155. static int macb_mii_probe(struct net_device *dev)
  156. {
  157. struct macb *bp = netdev_priv(dev);
  158. struct phy_device *phydev;
  159. int ret;
  160. phydev = phy_find_first(bp->mii_bus);
  161. if (!phydev) {
  162. netdev_err(dev, "no PHY found\n");
  163. return -1;
  164. }
  165. /* TODO : add pin_irq */
  166. /* attach the mac to the phy */
  167. ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0,
  168. bp->phy_interface);
  169. if (ret) {
  170. netdev_err(dev, "Could not attach to PHY\n");
  171. return ret;
  172. }
  173. /* mask with MAC supported features */
  174. phydev->supported &= PHY_BASIC_FEATURES;
  175. phydev->advertising = phydev->supported;
  176. bp->link = 0;
  177. bp->speed = 0;
  178. bp->duplex = -1;
  179. bp->phy_dev = phydev;
  180. return 0;
  181. }
  182. static int macb_mii_init(struct macb *bp)
  183. {
  184. struct macb_platform_data *pdata;
  185. int err = -ENXIO, i;
  186. /* Enable management port */
  187. macb_writel(bp, NCR, MACB_BIT(MPE));
  188. bp->mii_bus = mdiobus_alloc();
  189. if (bp->mii_bus == NULL) {
  190. err = -ENOMEM;
  191. goto err_out;
  192. }
  193. bp->mii_bus->name = "MACB_mii_bus";
  194. bp->mii_bus->read = &macb_mdio_read;
  195. bp->mii_bus->write = &macb_mdio_write;
  196. bp->mii_bus->reset = &macb_mdio_reset;
  197. snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  198. bp->pdev->name, bp->pdev->id);
  199. bp->mii_bus->priv = bp;
  200. bp->mii_bus->parent = &bp->dev->dev;
  201. pdata = bp->pdev->dev.platform_data;
  202. if (pdata)
  203. bp->mii_bus->phy_mask = pdata->phy_mask;
  204. bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
  205. if (!bp->mii_bus->irq) {
  206. err = -ENOMEM;
  207. goto err_out_free_mdiobus;
  208. }
  209. for (i = 0; i < PHY_MAX_ADDR; i++)
  210. bp->mii_bus->irq[i] = PHY_POLL;
  211. dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
  212. if (mdiobus_register(bp->mii_bus))
  213. goto err_out_free_mdio_irq;
  214. if (macb_mii_probe(bp->dev) != 0) {
  215. goto err_out_unregister_bus;
  216. }
  217. return 0;
  218. err_out_unregister_bus:
  219. mdiobus_unregister(bp->mii_bus);
  220. err_out_free_mdio_irq:
  221. kfree(bp->mii_bus->irq);
  222. err_out_free_mdiobus:
  223. mdiobus_free(bp->mii_bus);
  224. err_out:
  225. return err;
  226. }
  227. static void macb_update_stats(struct macb *bp)
  228. {
  229. u32 __iomem *reg = bp->regs + MACB_PFR;
  230. u32 *p = &bp->hw_stats.macb.rx_pause_frames;
  231. u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
  232. WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
  233. for(; p < end; p++, reg++)
  234. *p += __raw_readl(reg);
  235. }
  236. static void macb_tx(struct macb *bp)
  237. {
  238. unsigned int tail;
  239. unsigned int head;
  240. u32 status;
  241. status = macb_readl(bp, TSR);
  242. macb_writel(bp, TSR, status);
  243. netdev_dbg(bp->dev, "macb_tx status = %02lx\n", (unsigned long)status);
  244. if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) {
  245. int i;
  246. netdev_err(bp->dev, "TX %s, resetting buffers\n",
  247. status & MACB_BIT(UND) ?
  248. "underrun" : "retry limit exceeded");
  249. /* Transfer ongoing, disable transmitter, to avoid confusion */
  250. if (status & MACB_BIT(TGO))
  251. macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE));
  252. head = bp->tx_head;
  253. /*Mark all the buffer as used to avoid sending a lost buffer*/
  254. for (i = 0; i < TX_RING_SIZE; i++)
  255. bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
  256. /* Add wrap bit */
  257. bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
  258. /* free transmit buffer in upper layer*/
  259. for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
  260. struct ring_info *rp = &bp->tx_skb[tail];
  261. struct sk_buff *skb = rp->skb;
  262. BUG_ON(skb == NULL);
  263. rmb();
  264. dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
  265. DMA_TO_DEVICE);
  266. rp->skb = NULL;
  267. dev_kfree_skb_irq(skb);
  268. }
  269. bp->tx_head = bp->tx_tail = 0;
  270. /* Enable the transmitter again */
  271. if (status & MACB_BIT(TGO))
  272. macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
  273. }
  274. if (!(status & MACB_BIT(COMP)))
  275. /*
  276. * This may happen when a buffer becomes complete
  277. * between reading the ISR and scanning the
  278. * descriptors. Nothing to worry about.
  279. */
  280. return;
  281. head = bp->tx_head;
  282. for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
  283. struct ring_info *rp = &bp->tx_skb[tail];
  284. struct sk_buff *skb = rp->skb;
  285. u32 bufstat;
  286. BUG_ON(skb == NULL);
  287. rmb();
  288. bufstat = bp->tx_ring[tail].ctrl;
  289. if (!(bufstat & MACB_BIT(TX_USED)))
  290. break;
  291. netdev_dbg(bp->dev, "skb %u (data %p) TX complete\n",
  292. tail, skb->data);
  293. dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
  294. DMA_TO_DEVICE);
  295. bp->stats.tx_packets++;
  296. bp->stats.tx_bytes += skb->len;
  297. rp->skb = NULL;
  298. dev_kfree_skb_irq(skb);
  299. }
  300. bp->tx_tail = tail;
  301. if (netif_queue_stopped(bp->dev) &&
  302. TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
  303. netif_wake_queue(bp->dev);
  304. }
  305. static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
  306. unsigned int last_frag)
  307. {
  308. unsigned int len;
  309. unsigned int frag;
  310. unsigned int offset = 0;
  311. struct sk_buff *skb;
  312. len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
  313. netdev_dbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
  314. first_frag, last_frag, len);
  315. skb = netdev_alloc_skb(bp->dev, len + RX_OFFSET);
  316. if (!skb) {
  317. bp->stats.rx_dropped++;
  318. for (frag = first_frag; ; frag = NEXT_RX(frag)) {
  319. bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
  320. if (frag == last_frag)
  321. break;
  322. }
  323. wmb();
  324. return 1;
  325. }
  326. skb_reserve(skb, RX_OFFSET);
  327. skb_checksum_none_assert(skb);
  328. skb_put(skb, len);
  329. for (frag = first_frag; ; frag = NEXT_RX(frag)) {
  330. unsigned int frag_len = RX_BUFFER_SIZE;
  331. if (offset + frag_len > len) {
  332. BUG_ON(frag != last_frag);
  333. frag_len = len - offset;
  334. }
  335. skb_copy_to_linear_data_offset(skb, offset,
  336. (bp->rx_buffers +
  337. (RX_BUFFER_SIZE * frag)),
  338. frag_len);
  339. offset += RX_BUFFER_SIZE;
  340. bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
  341. wmb();
  342. if (frag == last_frag)
  343. break;
  344. }
  345. skb->protocol = eth_type_trans(skb, bp->dev);
  346. bp->stats.rx_packets++;
  347. bp->stats.rx_bytes += len;
  348. netdev_dbg(bp->dev, "received skb of length %u, csum: %08x\n",
  349. skb->len, skb->csum);
  350. netif_receive_skb(skb);
  351. return 0;
  352. }
  353. /* Mark DMA descriptors from begin up to and not including end as unused */
  354. static void discard_partial_frame(struct macb *bp, unsigned int begin,
  355. unsigned int end)
  356. {
  357. unsigned int frag;
  358. for (frag = begin; frag != end; frag = NEXT_RX(frag))
  359. bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
  360. wmb();
  361. /*
  362. * When this happens, the hardware stats registers for
  363. * whatever caused this is updated, so we don't have to record
  364. * anything.
  365. */
  366. }
  367. static int macb_rx(struct macb *bp, int budget)
  368. {
  369. int received = 0;
  370. unsigned int tail = bp->rx_tail;
  371. int first_frag = -1;
  372. for (; budget > 0; tail = NEXT_RX(tail)) {
  373. u32 addr, ctrl;
  374. rmb();
  375. addr = bp->rx_ring[tail].addr;
  376. ctrl = bp->rx_ring[tail].ctrl;
  377. if (!(addr & MACB_BIT(RX_USED)))
  378. break;
  379. if (ctrl & MACB_BIT(RX_SOF)) {
  380. if (first_frag != -1)
  381. discard_partial_frame(bp, first_frag, tail);
  382. first_frag = tail;
  383. }
  384. if (ctrl & MACB_BIT(RX_EOF)) {
  385. int dropped;
  386. BUG_ON(first_frag == -1);
  387. dropped = macb_rx_frame(bp, first_frag, tail);
  388. first_frag = -1;
  389. if (!dropped) {
  390. received++;
  391. budget--;
  392. }
  393. }
  394. }
  395. if (first_frag != -1)
  396. bp->rx_tail = first_frag;
  397. else
  398. bp->rx_tail = tail;
  399. return received;
  400. }
  401. static int macb_poll(struct napi_struct *napi, int budget)
  402. {
  403. struct macb *bp = container_of(napi, struct macb, napi);
  404. int work_done;
  405. u32 status;
  406. status = macb_readl(bp, RSR);
  407. macb_writel(bp, RSR, status);
  408. work_done = 0;
  409. netdev_dbg(bp->dev, "poll: status = %08lx, budget = %d\n",
  410. (unsigned long)status, budget);
  411. work_done = macb_rx(bp, budget);
  412. if (work_done < budget) {
  413. napi_complete(napi);
  414. /*
  415. * We've done what we can to clean the buffers. Make sure we
  416. * get notified when new packets arrive.
  417. */
  418. macb_writel(bp, IER, MACB_RX_INT_FLAGS);
  419. }
  420. /* TODO: Handle errors */
  421. return work_done;
  422. }
  423. static irqreturn_t macb_interrupt(int irq, void *dev_id)
  424. {
  425. struct net_device *dev = dev_id;
  426. struct macb *bp = netdev_priv(dev);
  427. u32 status;
  428. status = macb_readl(bp, ISR);
  429. if (unlikely(!status))
  430. return IRQ_NONE;
  431. spin_lock(&bp->lock);
  432. while (status) {
  433. /* close possible race with dev_close */
  434. if (unlikely(!netif_running(dev))) {
  435. macb_writel(bp, IDR, ~0UL);
  436. break;
  437. }
  438. if (status & MACB_RX_INT_FLAGS) {
  439. /*
  440. * There's no point taking any more interrupts
  441. * until we have processed the buffers. The
  442. * scheduling call may fail if the poll routine
  443. * is already scheduled, so disable interrupts
  444. * now.
  445. */
  446. macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
  447. if (napi_schedule_prep(&bp->napi)) {
  448. netdev_dbg(bp->dev, "scheduling RX softirq\n");
  449. __napi_schedule(&bp->napi);
  450. }
  451. }
  452. if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
  453. MACB_BIT(ISR_RLE)))
  454. macb_tx(bp);
  455. /*
  456. * Link change detection isn't possible with RMII, so we'll
  457. * add that if/when we get our hands on a full-blown MII PHY.
  458. */
  459. if (status & MACB_BIT(ISR_ROVR)) {
  460. /* We missed at least one packet */
  461. if (macb_is_gem(bp))
  462. bp->hw_stats.gem.rx_overruns++;
  463. else
  464. bp->hw_stats.macb.rx_overruns++;
  465. }
  466. if (status & MACB_BIT(HRESP)) {
  467. /*
  468. * TODO: Reset the hardware, and maybe move the
  469. * netdev_err to a lower-priority context as well
  470. * (work queue?)
  471. */
  472. netdev_err(dev, "DMA bus error: HRESP not OK\n");
  473. }
  474. status = macb_readl(bp, ISR);
  475. }
  476. spin_unlock(&bp->lock);
  477. return IRQ_HANDLED;
  478. }
  479. #ifdef CONFIG_NET_POLL_CONTROLLER
  480. /*
  481. * Polling receive - used by netconsole and other diagnostic tools
  482. * to allow network i/o with interrupts disabled.
  483. */
  484. static void macb_poll_controller(struct net_device *dev)
  485. {
  486. unsigned long flags;
  487. local_irq_save(flags);
  488. macb_interrupt(dev->irq, dev);
  489. local_irq_restore(flags);
  490. }
  491. #endif
  492. static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
  493. {
  494. struct macb *bp = netdev_priv(dev);
  495. dma_addr_t mapping;
  496. unsigned int len, entry;
  497. u32 ctrl;
  498. unsigned long flags;
  499. #ifdef DEBUG
  500. netdev_dbg(bp->dev,
  501. "start_xmit: len %u head %p data %p tail %p end %p\n",
  502. skb->len, skb->head, skb->data,
  503. skb_tail_pointer(skb), skb_end_pointer(skb));
  504. print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
  505. skb->data, 16, true);
  506. #endif
  507. len = skb->len;
  508. spin_lock_irqsave(&bp->lock, flags);
  509. /* This is a hard error, log it. */
  510. if (TX_BUFFS_AVAIL(bp) < 1) {
  511. netif_stop_queue(dev);
  512. spin_unlock_irqrestore(&bp->lock, flags);
  513. netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
  514. netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
  515. bp->tx_head, bp->tx_tail);
  516. return NETDEV_TX_BUSY;
  517. }
  518. entry = bp->tx_head;
  519. netdev_dbg(bp->dev, "Allocated ring entry %u\n", entry);
  520. mapping = dma_map_single(&bp->pdev->dev, skb->data,
  521. len, DMA_TO_DEVICE);
  522. bp->tx_skb[entry].skb = skb;
  523. bp->tx_skb[entry].mapping = mapping;
  524. netdev_dbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
  525. skb->data, (unsigned long)mapping);
  526. ctrl = MACB_BF(TX_FRMLEN, len);
  527. ctrl |= MACB_BIT(TX_LAST);
  528. if (entry == (TX_RING_SIZE - 1))
  529. ctrl |= MACB_BIT(TX_WRAP);
  530. bp->tx_ring[entry].addr = mapping;
  531. bp->tx_ring[entry].ctrl = ctrl;
  532. wmb();
  533. entry = NEXT_TX(entry);
  534. bp->tx_head = entry;
  535. skb_tx_timestamp(skb);
  536. macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
  537. if (TX_BUFFS_AVAIL(bp) < 1)
  538. netif_stop_queue(dev);
  539. spin_unlock_irqrestore(&bp->lock, flags);
  540. return NETDEV_TX_OK;
  541. }
  542. static void macb_free_consistent(struct macb *bp)
  543. {
  544. if (bp->tx_skb) {
  545. kfree(bp->tx_skb);
  546. bp->tx_skb = NULL;
  547. }
  548. if (bp->rx_ring) {
  549. dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
  550. bp->rx_ring, bp->rx_ring_dma);
  551. bp->rx_ring = NULL;
  552. }
  553. if (bp->tx_ring) {
  554. dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
  555. bp->tx_ring, bp->tx_ring_dma);
  556. bp->tx_ring = NULL;
  557. }
  558. if (bp->rx_buffers) {
  559. dma_free_coherent(&bp->pdev->dev,
  560. RX_RING_SIZE * RX_BUFFER_SIZE,
  561. bp->rx_buffers, bp->rx_buffers_dma);
  562. bp->rx_buffers = NULL;
  563. }
  564. }
  565. static int macb_alloc_consistent(struct macb *bp)
  566. {
  567. int size;
  568. size = TX_RING_SIZE * sizeof(struct ring_info);
  569. bp->tx_skb = kmalloc(size, GFP_KERNEL);
  570. if (!bp->tx_skb)
  571. goto out_err;
  572. size = RX_RING_BYTES;
  573. bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
  574. &bp->rx_ring_dma, GFP_KERNEL);
  575. if (!bp->rx_ring)
  576. goto out_err;
  577. netdev_dbg(bp->dev,
  578. "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
  579. size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
  580. size = TX_RING_BYTES;
  581. bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
  582. &bp->tx_ring_dma, GFP_KERNEL);
  583. if (!bp->tx_ring)
  584. goto out_err;
  585. netdev_dbg(bp->dev,
  586. "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
  587. size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
  588. size = RX_RING_SIZE * RX_BUFFER_SIZE;
  589. bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
  590. &bp->rx_buffers_dma, GFP_KERNEL);
  591. if (!bp->rx_buffers)
  592. goto out_err;
  593. netdev_dbg(bp->dev,
  594. "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
  595. size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
  596. return 0;
  597. out_err:
  598. macb_free_consistent(bp);
  599. return -ENOMEM;
  600. }
  601. static void macb_init_rings(struct macb *bp)
  602. {
  603. int i;
  604. dma_addr_t addr;
  605. addr = bp->rx_buffers_dma;
  606. for (i = 0; i < RX_RING_SIZE; i++) {
  607. bp->rx_ring[i].addr = addr;
  608. bp->rx_ring[i].ctrl = 0;
  609. addr += RX_BUFFER_SIZE;
  610. }
  611. bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
  612. for (i = 0; i < TX_RING_SIZE; i++) {
  613. bp->tx_ring[i].addr = 0;
  614. bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
  615. }
  616. bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
  617. bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
  618. }
  619. static void macb_reset_hw(struct macb *bp)
  620. {
  621. /* Make sure we have the write buffer for ourselves */
  622. wmb();
  623. /*
  624. * Disable RX and TX (XXX: Should we halt the transmission
  625. * more gracefully?)
  626. */
  627. macb_writel(bp, NCR, 0);
  628. /* Clear the stats registers (XXX: Update stats first?) */
  629. macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
  630. /* Clear all status flags */
  631. macb_writel(bp, TSR, ~0UL);
  632. macb_writel(bp, RSR, ~0UL);
  633. /* Disable all interrupts */
  634. macb_writel(bp, IDR, ~0UL);
  635. macb_readl(bp, ISR);
  636. }
  637. static u32 gem_mdc_clk_div(struct macb *bp)
  638. {
  639. u32 config;
  640. unsigned long pclk_hz = clk_get_rate(bp->pclk);
  641. if (pclk_hz <= 20000000)
  642. config = GEM_BF(CLK, GEM_CLK_DIV8);
  643. else if (pclk_hz <= 40000000)
  644. config = GEM_BF(CLK, GEM_CLK_DIV16);
  645. else if (pclk_hz <= 80000000)
  646. config = GEM_BF(CLK, GEM_CLK_DIV32);
  647. else if (pclk_hz <= 120000000)
  648. config = GEM_BF(CLK, GEM_CLK_DIV48);
  649. else if (pclk_hz <= 160000000)
  650. config = GEM_BF(CLK, GEM_CLK_DIV64);
  651. else
  652. config = GEM_BF(CLK, GEM_CLK_DIV96);
  653. return config;
  654. }
  655. static u32 macb_mdc_clk_div(struct macb *bp)
  656. {
  657. u32 config;
  658. unsigned long pclk_hz;
  659. if (macb_is_gem(bp))
  660. return gem_mdc_clk_div(bp);
  661. pclk_hz = clk_get_rate(bp->pclk);
  662. if (pclk_hz <= 20000000)
  663. config = MACB_BF(CLK, MACB_CLK_DIV8);
  664. else if (pclk_hz <= 40000000)
  665. config = MACB_BF(CLK, MACB_CLK_DIV16);
  666. else if (pclk_hz <= 80000000)
  667. config = MACB_BF(CLK, MACB_CLK_DIV32);
  668. else
  669. config = MACB_BF(CLK, MACB_CLK_DIV64);
  670. return config;
  671. }
  672. /*
  673. * Get the DMA bus width field of the network configuration register that we
  674. * should program. We find the width from decoding the design configuration
  675. * register to find the maximum supported data bus width.
  676. */
  677. static u32 macb_dbw(struct macb *bp)
  678. {
  679. if (!macb_is_gem(bp))
  680. return 0;
  681. switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
  682. case 4:
  683. return GEM_BF(DBW, GEM_DBW128);
  684. case 2:
  685. return GEM_BF(DBW, GEM_DBW64);
  686. case 1:
  687. default:
  688. return GEM_BF(DBW, GEM_DBW32);
  689. }
  690. }
  691. /*
  692. * Configure the receive DMA engine to use the correct receive buffer size.
  693. * This is a configurable parameter for GEM.
  694. */
  695. static void macb_configure_dma(struct macb *bp)
  696. {
  697. u32 dmacfg;
  698. if (macb_is_gem(bp)) {
  699. dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
  700. dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64);
  701. gem_writel(bp, DMACFG, dmacfg);
  702. }
  703. }
  704. static void macb_init_hw(struct macb *bp)
  705. {
  706. u32 config;
  707. macb_reset_hw(bp);
  708. __macb_set_hwaddr(bp);
  709. config = macb_mdc_clk_div(bp);
  710. config |= MACB_BIT(PAE); /* PAuse Enable */
  711. config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
  712. config |= MACB_BIT(BIG); /* Receive oversized frames */
  713. if (bp->dev->flags & IFF_PROMISC)
  714. config |= MACB_BIT(CAF); /* Copy All Frames */
  715. if (!(bp->dev->flags & IFF_BROADCAST))
  716. config |= MACB_BIT(NBC); /* No BroadCast */
  717. config |= macb_dbw(bp);
  718. macb_writel(bp, NCFGR, config);
  719. macb_configure_dma(bp);
  720. /* Initialize TX and RX buffers */
  721. macb_writel(bp, RBQP, bp->rx_ring_dma);
  722. macb_writel(bp, TBQP, bp->tx_ring_dma);
  723. /* Enable TX and RX */
  724. macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
  725. /* Enable interrupts */
  726. macb_writel(bp, IER, (MACB_BIT(RCOMP)
  727. | MACB_BIT(RXUBR)
  728. | MACB_BIT(ISR_TUND)
  729. | MACB_BIT(ISR_RLE)
  730. | MACB_BIT(TXERR)
  731. | MACB_BIT(TCOMP)
  732. | MACB_BIT(ISR_ROVR)
  733. | MACB_BIT(HRESP)));
  734. }
  735. /*
  736. * The hash address register is 64 bits long and takes up two
  737. * locations in the memory map. The least significant bits are stored
  738. * in EMAC_HSL and the most significant bits in EMAC_HSH.
  739. *
  740. * The unicast hash enable and the multicast hash enable bits in the
  741. * network configuration register enable the reception of hash matched
  742. * frames. The destination address is reduced to a 6 bit index into
  743. * the 64 bit hash register using the following hash function. The
  744. * hash function is an exclusive or of every sixth bit of the
  745. * destination address.
  746. *
  747. * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
  748. * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
  749. * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
  750. * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
  751. * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
  752. * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
  753. *
  754. * da[0] represents the least significant bit of the first byte
  755. * received, that is, the multicast/unicast indicator, and da[47]
  756. * represents the most significant bit of the last byte received. If
  757. * the hash index, hi[n], points to a bit that is set in the hash
  758. * register then the frame will be matched according to whether the
  759. * frame is multicast or unicast. A multicast match will be signalled
  760. * if the multicast hash enable bit is set, da[0] is 1 and the hash
  761. * index points to a bit set in the hash register. A unicast match
  762. * will be signalled if the unicast hash enable bit is set, da[0] is 0
  763. * and the hash index points to a bit set in the hash register. To
  764. * receive all multicast frames, the hash register should be set with
  765. * all ones and the multicast hash enable bit should be set in the
  766. * network configuration register.
  767. */
  768. static inline int hash_bit_value(int bitnr, __u8 *addr)
  769. {
  770. if (addr[bitnr / 8] & (1 << (bitnr % 8)))
  771. return 1;
  772. return 0;
  773. }
  774. /*
  775. * Return the hash index value for the specified address.
  776. */
  777. static int hash_get_index(__u8 *addr)
  778. {
  779. int i, j, bitval;
  780. int hash_index = 0;
  781. for (j = 0; j < 6; j++) {
  782. for (i = 0, bitval = 0; i < 8; i++)
  783. bitval ^= hash_bit_value(i*6 + j, addr);
  784. hash_index |= (bitval << j);
  785. }
  786. return hash_index;
  787. }
  788. /*
  789. * Add multicast addresses to the internal multicast-hash table.
  790. */
  791. static void macb_sethashtable(struct net_device *dev)
  792. {
  793. struct netdev_hw_addr *ha;
  794. unsigned long mc_filter[2];
  795. unsigned int bitnr;
  796. struct macb *bp = netdev_priv(dev);
  797. mc_filter[0] = mc_filter[1] = 0;
  798. netdev_for_each_mc_addr(ha, dev) {
  799. bitnr = hash_get_index(ha->addr);
  800. mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
  801. }
  802. macb_or_gem_writel(bp, HRB, mc_filter[0]);
  803. macb_or_gem_writel(bp, HRT, mc_filter[1]);
  804. }
  805. /*
  806. * Enable/Disable promiscuous and multicast modes.
  807. */
  808. static void macb_set_rx_mode(struct net_device *dev)
  809. {
  810. unsigned long cfg;
  811. struct macb *bp = netdev_priv(dev);
  812. cfg = macb_readl(bp, NCFGR);
  813. if (dev->flags & IFF_PROMISC)
  814. /* Enable promiscuous mode */
  815. cfg |= MACB_BIT(CAF);
  816. else if (dev->flags & (~IFF_PROMISC))
  817. /* Disable promiscuous mode */
  818. cfg &= ~MACB_BIT(CAF);
  819. if (dev->flags & IFF_ALLMULTI) {
  820. /* Enable all multicast mode */
  821. macb_or_gem_writel(bp, HRB, -1);
  822. macb_or_gem_writel(bp, HRT, -1);
  823. cfg |= MACB_BIT(NCFGR_MTI);
  824. } else if (!netdev_mc_empty(dev)) {
  825. /* Enable specific multicasts */
  826. macb_sethashtable(dev);
  827. cfg |= MACB_BIT(NCFGR_MTI);
  828. } else if (dev->flags & (~IFF_ALLMULTI)) {
  829. /* Disable all multicast mode */
  830. macb_or_gem_writel(bp, HRB, 0);
  831. macb_or_gem_writel(bp, HRT, 0);
  832. cfg &= ~MACB_BIT(NCFGR_MTI);
  833. }
  834. macb_writel(bp, NCFGR, cfg);
  835. }
  836. static int macb_open(struct net_device *dev)
  837. {
  838. struct macb *bp = netdev_priv(dev);
  839. int err;
  840. netdev_dbg(bp->dev, "open\n");
  841. /* if the phy is not yet register, retry later*/
  842. if (!bp->phy_dev)
  843. return -EAGAIN;
  844. if (!is_valid_ether_addr(dev->dev_addr))
  845. return -EADDRNOTAVAIL;
  846. err = macb_alloc_consistent(bp);
  847. if (err) {
  848. netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
  849. err);
  850. return err;
  851. }
  852. napi_enable(&bp->napi);
  853. macb_init_rings(bp);
  854. macb_init_hw(bp);
  855. /* schedule a link state check */
  856. phy_start(bp->phy_dev);
  857. netif_start_queue(dev);
  858. return 0;
  859. }
  860. static int macb_close(struct net_device *dev)
  861. {
  862. struct macb *bp = netdev_priv(dev);
  863. unsigned long flags;
  864. netif_stop_queue(dev);
  865. napi_disable(&bp->napi);
  866. if (bp->phy_dev)
  867. phy_stop(bp->phy_dev);
  868. spin_lock_irqsave(&bp->lock, flags);
  869. macb_reset_hw(bp);
  870. netif_carrier_off(dev);
  871. spin_unlock_irqrestore(&bp->lock, flags);
  872. macb_free_consistent(bp);
  873. return 0;
  874. }
  875. static void gem_update_stats(struct macb *bp)
  876. {
  877. u32 __iomem *reg = bp->regs + GEM_OTX;
  878. u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
  879. u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
  880. for (; p < end; p++, reg++)
  881. *p += __raw_readl(reg);
  882. }
  883. static struct net_device_stats *gem_get_stats(struct macb *bp)
  884. {
  885. struct gem_stats *hwstat = &bp->hw_stats.gem;
  886. struct net_device_stats *nstat = &bp->stats;
  887. gem_update_stats(bp);
  888. nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
  889. hwstat->rx_alignment_errors +
  890. hwstat->rx_resource_errors +
  891. hwstat->rx_overruns +
  892. hwstat->rx_oversize_frames +
  893. hwstat->rx_jabbers +
  894. hwstat->rx_undersized_frames +
  895. hwstat->rx_length_field_frame_errors);
  896. nstat->tx_errors = (hwstat->tx_late_collisions +
  897. hwstat->tx_excessive_collisions +
  898. hwstat->tx_underrun +
  899. hwstat->tx_carrier_sense_errors);
  900. nstat->multicast = hwstat->rx_multicast_frames;
  901. nstat->collisions = (hwstat->tx_single_collision_frames +
  902. hwstat->tx_multiple_collision_frames +
  903. hwstat->tx_excessive_collisions);
  904. nstat->rx_length_errors = (hwstat->rx_oversize_frames +
  905. hwstat->rx_jabbers +
  906. hwstat->rx_undersized_frames +
  907. hwstat->rx_length_field_frame_errors);
  908. nstat->rx_over_errors = hwstat->rx_resource_errors;
  909. nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
  910. nstat->rx_frame_errors = hwstat->rx_alignment_errors;
  911. nstat->rx_fifo_errors = hwstat->rx_overruns;
  912. nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
  913. nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
  914. nstat->tx_fifo_errors = hwstat->tx_underrun;
  915. return nstat;
  916. }
  917. static struct net_device_stats *macb_get_stats(struct net_device *dev)
  918. {
  919. struct macb *bp = netdev_priv(dev);
  920. struct net_device_stats *nstat = &bp->stats;
  921. struct macb_stats *hwstat = &bp->hw_stats.macb;
  922. if (macb_is_gem(bp))
  923. return gem_get_stats(bp);
  924. /* read stats from hardware */
  925. macb_update_stats(bp);
  926. /* Convert HW stats into netdevice stats */
  927. nstat->rx_errors = (hwstat->rx_fcs_errors +
  928. hwstat->rx_align_errors +
  929. hwstat->rx_resource_errors +
  930. hwstat->rx_overruns +
  931. hwstat->rx_oversize_pkts +
  932. hwstat->rx_jabbers +
  933. hwstat->rx_undersize_pkts +
  934. hwstat->sqe_test_errors +
  935. hwstat->rx_length_mismatch);
  936. nstat->tx_errors = (hwstat->tx_late_cols +
  937. hwstat->tx_excessive_cols +
  938. hwstat->tx_underruns +
  939. hwstat->tx_carrier_errors);
  940. nstat->collisions = (hwstat->tx_single_cols +
  941. hwstat->tx_multiple_cols +
  942. hwstat->tx_excessive_cols);
  943. nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
  944. hwstat->rx_jabbers +
  945. hwstat->rx_undersize_pkts +
  946. hwstat->rx_length_mismatch);
  947. nstat->rx_over_errors = hwstat->rx_resource_errors +
  948. hwstat->rx_overruns;
  949. nstat->rx_crc_errors = hwstat->rx_fcs_errors;
  950. nstat->rx_frame_errors = hwstat->rx_align_errors;
  951. nstat->rx_fifo_errors = hwstat->rx_overruns;
  952. /* XXX: What does "missed" mean? */
  953. nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
  954. nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
  955. nstat->tx_fifo_errors = hwstat->tx_underruns;
  956. /* Don't know about heartbeat or window errors... */
  957. return nstat;
  958. }
  959. static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  960. {
  961. struct macb *bp = netdev_priv(dev);
  962. struct phy_device *phydev = bp->phy_dev;
  963. if (!phydev)
  964. return -ENODEV;
  965. return phy_ethtool_gset(phydev, cmd);
  966. }
  967. static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  968. {
  969. struct macb *bp = netdev_priv(dev);
  970. struct phy_device *phydev = bp->phy_dev;
  971. if (!phydev)
  972. return -ENODEV;
  973. return phy_ethtool_sset(phydev, cmd);
  974. }
  975. static void macb_get_drvinfo(struct net_device *dev,
  976. struct ethtool_drvinfo *info)
  977. {
  978. struct macb *bp = netdev_priv(dev);
  979. strcpy(info->driver, bp->pdev->dev.driver->name);
  980. strcpy(info->version, "$Revision: 1.14 $");
  981. strcpy(info->bus_info, dev_name(&bp->pdev->dev));
  982. }
  983. static const struct ethtool_ops macb_ethtool_ops = {
  984. .get_settings = macb_get_settings,
  985. .set_settings = macb_set_settings,
  986. .get_drvinfo = macb_get_drvinfo,
  987. .get_link = ethtool_op_get_link,
  988. };
  989. static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  990. {
  991. struct macb *bp = netdev_priv(dev);
  992. struct phy_device *phydev = bp->phy_dev;
  993. if (!netif_running(dev))
  994. return -EINVAL;
  995. if (!phydev)
  996. return -ENODEV;
  997. return phy_mii_ioctl(phydev, rq, cmd);
  998. }
  999. static const struct net_device_ops macb_netdev_ops = {
  1000. .ndo_open = macb_open,
  1001. .ndo_stop = macb_close,
  1002. .ndo_start_xmit = macb_start_xmit,
  1003. .ndo_set_rx_mode = macb_set_rx_mode,
  1004. .ndo_get_stats = macb_get_stats,
  1005. .ndo_do_ioctl = macb_ioctl,
  1006. .ndo_validate_addr = eth_validate_addr,
  1007. .ndo_change_mtu = eth_change_mtu,
  1008. .ndo_set_mac_address = eth_mac_addr,
  1009. #ifdef CONFIG_NET_POLL_CONTROLLER
  1010. .ndo_poll_controller = macb_poll_controller,
  1011. #endif
  1012. };
  1013. #if defined(CONFIG_OF)
  1014. static const struct of_device_id macb_dt_ids[] = {
  1015. { .compatible = "cdns,at32ap7000-macb" },
  1016. { .compatible = "cdns,at91sam9260-macb" },
  1017. { .compatible = "cdns,macb" },
  1018. { .compatible = "cdns,pc302-gem" },
  1019. { .compatible = "cdns,gem" },
  1020. { /* sentinel */ }
  1021. };
  1022. MODULE_DEVICE_TABLE(of, macb_dt_ids);
  1023. static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev)
  1024. {
  1025. struct device_node *np = pdev->dev.of_node;
  1026. if (np)
  1027. return of_get_phy_mode(np);
  1028. return -ENODEV;
  1029. }
  1030. static int __devinit macb_get_hwaddr_dt(struct macb *bp)
  1031. {
  1032. struct device_node *np = bp->pdev->dev.of_node;
  1033. if (np) {
  1034. const char *mac = of_get_mac_address(np);
  1035. if (mac) {
  1036. memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
  1037. return 0;
  1038. }
  1039. }
  1040. return -ENODEV;
  1041. }
  1042. #else
  1043. static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev)
  1044. {
  1045. return -ENODEV;
  1046. }
  1047. static int __devinit macb_get_hwaddr_dt(struct macb *bp)
  1048. {
  1049. return -ENODEV;
  1050. }
  1051. #endif
  1052. static int __init macb_probe(struct platform_device *pdev)
  1053. {
  1054. struct macb_platform_data *pdata;
  1055. struct resource *regs;
  1056. struct net_device *dev;
  1057. struct macb *bp;
  1058. struct phy_device *phydev;
  1059. u32 config;
  1060. int err = -ENXIO;
  1061. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1062. if (!regs) {
  1063. dev_err(&pdev->dev, "no mmio resource defined\n");
  1064. goto err_out;
  1065. }
  1066. err = -ENOMEM;
  1067. dev = alloc_etherdev(sizeof(*bp));
  1068. if (!dev)
  1069. goto err_out;
  1070. SET_NETDEV_DEV(dev, &pdev->dev);
  1071. /* TODO: Actually, we have some interesting features... */
  1072. dev->features |= 0;
  1073. bp = netdev_priv(dev);
  1074. bp->pdev = pdev;
  1075. bp->dev = dev;
  1076. spin_lock_init(&bp->lock);
  1077. bp->pclk = clk_get(&pdev->dev, "pclk");
  1078. if (IS_ERR(bp->pclk)) {
  1079. dev_err(&pdev->dev, "failed to get macb_clk\n");
  1080. goto err_out_free_dev;
  1081. }
  1082. clk_enable(bp->pclk);
  1083. bp->hclk = clk_get(&pdev->dev, "hclk");
  1084. if (IS_ERR(bp->hclk)) {
  1085. dev_err(&pdev->dev, "failed to get hclk\n");
  1086. goto err_out_put_pclk;
  1087. }
  1088. clk_enable(bp->hclk);
  1089. bp->regs = ioremap(regs->start, resource_size(regs));
  1090. if (!bp->regs) {
  1091. dev_err(&pdev->dev, "failed to map registers, aborting.\n");
  1092. err = -ENOMEM;
  1093. goto err_out_disable_clocks;
  1094. }
  1095. dev->irq = platform_get_irq(pdev, 0);
  1096. err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev);
  1097. if (err) {
  1098. dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
  1099. dev->irq, err);
  1100. goto err_out_iounmap;
  1101. }
  1102. dev->netdev_ops = &macb_netdev_ops;
  1103. netif_napi_add(dev, &bp->napi, macb_poll, 64);
  1104. dev->ethtool_ops = &macb_ethtool_ops;
  1105. dev->base_addr = regs->start;
  1106. /* Set MII management clock divider */
  1107. config = macb_mdc_clk_div(bp);
  1108. config |= macb_dbw(bp);
  1109. macb_writel(bp, NCFGR, config);
  1110. err = macb_get_hwaddr_dt(bp);
  1111. if (err < 0)
  1112. macb_get_hwaddr(bp);
  1113. err = macb_get_phy_mode_dt(pdev);
  1114. if (err < 0) {
  1115. pdata = pdev->dev.platform_data;
  1116. if (pdata && pdata->is_rmii)
  1117. bp->phy_interface = PHY_INTERFACE_MODE_RMII;
  1118. else
  1119. bp->phy_interface = PHY_INTERFACE_MODE_MII;
  1120. } else {
  1121. bp->phy_interface = err;
  1122. }
  1123. if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
  1124. #if defined(CONFIG_ARCH_AT91)
  1125. macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
  1126. MACB_BIT(CLKEN)));
  1127. #else
  1128. macb_or_gem_writel(bp, USRIO, 0);
  1129. #endif
  1130. else
  1131. #if defined(CONFIG_ARCH_AT91)
  1132. macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
  1133. #else
  1134. macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
  1135. #endif
  1136. bp->tx_pending = DEF_TX_RING_PENDING;
  1137. err = register_netdev(dev);
  1138. if (err) {
  1139. dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
  1140. goto err_out_free_irq;
  1141. }
  1142. if (macb_mii_init(bp) != 0) {
  1143. goto err_out_unregister_netdev;
  1144. }
  1145. platform_set_drvdata(pdev, dev);
  1146. netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
  1147. macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
  1148. dev->irq, dev->dev_addr);
  1149. phydev = bp->phy_dev;
  1150. netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
  1151. phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
  1152. return 0;
  1153. err_out_unregister_netdev:
  1154. unregister_netdev(dev);
  1155. err_out_free_irq:
  1156. free_irq(dev->irq, dev);
  1157. err_out_iounmap:
  1158. iounmap(bp->regs);
  1159. err_out_disable_clocks:
  1160. clk_disable(bp->hclk);
  1161. clk_put(bp->hclk);
  1162. clk_disable(bp->pclk);
  1163. err_out_put_pclk:
  1164. clk_put(bp->pclk);
  1165. err_out_free_dev:
  1166. free_netdev(dev);
  1167. err_out:
  1168. platform_set_drvdata(pdev, NULL);
  1169. return err;
  1170. }
  1171. static int __exit macb_remove(struct platform_device *pdev)
  1172. {
  1173. struct net_device *dev;
  1174. struct macb *bp;
  1175. dev = platform_get_drvdata(pdev);
  1176. if (dev) {
  1177. bp = netdev_priv(dev);
  1178. if (bp->phy_dev)
  1179. phy_disconnect(bp->phy_dev);
  1180. mdiobus_unregister(bp->mii_bus);
  1181. kfree(bp->mii_bus->irq);
  1182. mdiobus_free(bp->mii_bus);
  1183. unregister_netdev(dev);
  1184. free_irq(dev->irq, dev);
  1185. iounmap(bp->regs);
  1186. clk_disable(bp->hclk);
  1187. clk_put(bp->hclk);
  1188. clk_disable(bp->pclk);
  1189. clk_put(bp->pclk);
  1190. free_netdev(dev);
  1191. platform_set_drvdata(pdev, NULL);
  1192. }
  1193. return 0;
  1194. }
  1195. #ifdef CONFIG_PM
  1196. static int macb_suspend(struct platform_device *pdev, pm_message_t state)
  1197. {
  1198. struct net_device *netdev = platform_get_drvdata(pdev);
  1199. struct macb *bp = netdev_priv(netdev);
  1200. netif_device_detach(netdev);
  1201. clk_disable(bp->hclk);
  1202. clk_disable(bp->pclk);
  1203. return 0;
  1204. }
  1205. static int macb_resume(struct platform_device *pdev)
  1206. {
  1207. struct net_device *netdev = platform_get_drvdata(pdev);
  1208. struct macb *bp = netdev_priv(netdev);
  1209. clk_enable(bp->pclk);
  1210. clk_enable(bp->hclk);
  1211. netif_device_attach(netdev);
  1212. return 0;
  1213. }
  1214. #else
  1215. #define macb_suspend NULL
  1216. #define macb_resume NULL
  1217. #endif
  1218. static struct platform_driver macb_driver = {
  1219. .remove = __exit_p(macb_remove),
  1220. .suspend = macb_suspend,
  1221. .resume = macb_resume,
  1222. .driver = {
  1223. .name = "macb",
  1224. .owner = THIS_MODULE,
  1225. .of_match_table = of_match_ptr(macb_dt_ids),
  1226. },
  1227. };
  1228. static int __init macb_init(void)
  1229. {
  1230. return platform_driver_probe(&macb_driver, macb_probe);
  1231. }
  1232. static void __exit macb_exit(void)
  1233. {
  1234. platform_driver_unregister(&macb_driver);
  1235. }
  1236. module_init(macb_init);
  1237. module_exit(macb_exit);
  1238. MODULE_LICENSE("GPL");
  1239. MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
  1240. MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
  1241. MODULE_ALIAS("platform:macb");