tps65912-irq.c 6.2 KB

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  1. /*
  2. * tps65912-irq.c -- TI TPS6591x
  3. *
  4. * Copyright 2011 Texas Instruments Inc.
  5. *
  6. * Author: Margarita Olaya <magi@slimlogic.co.uk>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. * This driver is based on wm8350 implementation.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/bug.h>
  19. #include <linux/device.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/irq.h>
  22. #include <linux/gpio.h>
  23. #include <linux/mfd/tps65912.h>
  24. static inline int irq_to_tps65912_irq(struct tps65912 *tps65912,
  25. int irq)
  26. {
  27. return irq - tps65912->irq_base;
  28. }
  29. /*
  30. * This is a threaded IRQ handler so can access I2C/SPI. Since the
  31. * IRQ handler explicitly clears the IRQ it handles the IRQ line
  32. * will be reasserted and the physical IRQ will be handled again if
  33. * another interrupt is asserted while we run - in the normal course
  34. * of events this is a rare occurrence so we save I2C/SPI reads. We're
  35. * also assuming that it's rare to get lots of interrupts firing
  36. * simultaneously so try to minimise I/O.
  37. */
  38. static irqreturn_t tps65912_irq(int irq, void *irq_data)
  39. {
  40. struct tps65912 *tps65912 = irq_data;
  41. u32 irq_sts;
  42. u32 irq_mask;
  43. u8 reg;
  44. int i;
  45. tps65912->read(tps65912, TPS65912_INT_STS, 1, &reg);
  46. irq_sts = reg;
  47. tps65912->read(tps65912, TPS65912_INT_STS2, 1, &reg);
  48. irq_sts |= reg << 8;
  49. tps65912->read(tps65912, TPS65912_INT_STS3, 1, &reg);
  50. irq_sts |= reg << 16;
  51. tps65912->read(tps65912, TPS65912_INT_STS4, 1, &reg);
  52. irq_sts |= reg << 24;
  53. tps65912->read(tps65912, TPS65912_INT_MSK, 1, &reg);
  54. irq_mask = reg;
  55. tps65912->read(tps65912, TPS65912_INT_MSK2, 1, &reg);
  56. irq_mask |= reg << 8;
  57. tps65912->read(tps65912, TPS65912_INT_MSK3, 1, &reg);
  58. irq_mask |= reg << 16;
  59. tps65912->read(tps65912, TPS65912_INT_MSK4, 1, &reg);
  60. irq_mask |= reg << 24;
  61. irq_sts &= ~irq_mask;
  62. if (!irq_sts)
  63. return IRQ_NONE;
  64. for (i = 0; i < tps65912->irq_num; i++) {
  65. if (!(irq_sts & (1 << i)))
  66. continue;
  67. handle_nested_irq(tps65912->irq_base + i);
  68. }
  69. /* Write the STS register back to clear IRQs we handled */
  70. reg = irq_sts & 0xFF;
  71. irq_sts >>= 8;
  72. if (reg)
  73. tps65912->write(tps65912, TPS65912_INT_STS, 1, &reg);
  74. reg = irq_sts & 0xFF;
  75. irq_sts >>= 8;
  76. if (reg)
  77. tps65912->write(tps65912, TPS65912_INT_STS2, 1, &reg);
  78. reg = irq_sts & 0xFF;
  79. irq_sts >>= 8;
  80. if (reg)
  81. tps65912->write(tps65912, TPS65912_INT_STS3, 1, &reg);
  82. reg = irq_sts & 0xFF;
  83. if (reg)
  84. tps65912->write(tps65912, TPS65912_INT_STS4, 1, &reg);
  85. return IRQ_HANDLED;
  86. }
  87. static void tps65912_irq_lock(struct irq_data *data)
  88. {
  89. struct tps65912 *tps65912 = irq_data_get_irq_chip_data(data);
  90. mutex_lock(&tps65912->irq_lock);
  91. }
  92. static void tps65912_irq_sync_unlock(struct irq_data *data)
  93. {
  94. struct tps65912 *tps65912 = irq_data_get_irq_chip_data(data);
  95. u32 reg_mask;
  96. u8 reg;
  97. tps65912->read(tps65912, TPS65912_INT_MSK, 1, &reg);
  98. reg_mask = reg;
  99. tps65912->read(tps65912, TPS65912_INT_MSK2, 1, &reg);
  100. reg_mask |= reg << 8;
  101. tps65912->read(tps65912, TPS65912_INT_MSK3, 1, &reg);
  102. reg_mask |= reg << 16;
  103. tps65912->read(tps65912, TPS65912_INT_MSK4, 1, &reg);
  104. reg_mask |= reg << 24;
  105. if (tps65912->irq_mask != reg_mask) {
  106. reg = tps65912->irq_mask & 0xFF;
  107. tps65912->write(tps65912, TPS65912_INT_MSK, 1, &reg);
  108. reg = tps65912->irq_mask >> 8 & 0xFF;
  109. tps65912->write(tps65912, TPS65912_INT_MSK2, 1, &reg);
  110. reg = tps65912->irq_mask >> 16 & 0xFF;
  111. tps65912->write(tps65912, TPS65912_INT_MSK3, 1, &reg);
  112. reg = tps65912->irq_mask >> 24 & 0xFF;
  113. tps65912->write(tps65912, TPS65912_INT_MSK4, 1, &reg);
  114. }
  115. mutex_unlock(&tps65912->irq_lock);
  116. }
  117. static void tps65912_irq_enable(struct irq_data *data)
  118. {
  119. struct tps65912 *tps65912 = irq_data_get_irq_chip_data(data);
  120. tps65912->irq_mask &= ~(1 << irq_to_tps65912_irq(tps65912, data->irq));
  121. }
  122. static void tps65912_irq_disable(struct irq_data *data)
  123. {
  124. struct tps65912 *tps65912 = irq_data_get_irq_chip_data(data);
  125. tps65912->irq_mask |= (1 << irq_to_tps65912_irq(tps65912, data->irq));
  126. }
  127. static struct irq_chip tps65912_irq_chip = {
  128. .name = "tps65912",
  129. .irq_bus_lock = tps65912_irq_lock,
  130. .irq_bus_sync_unlock = tps65912_irq_sync_unlock,
  131. .irq_disable = tps65912_irq_disable,
  132. .irq_enable = tps65912_irq_enable,
  133. };
  134. int tps65912_irq_init(struct tps65912 *tps65912, int irq,
  135. struct tps65912_platform_data *pdata)
  136. {
  137. int ret, cur_irq;
  138. int flags = IRQF_ONESHOT;
  139. u8 reg;
  140. if (!irq) {
  141. dev_warn(tps65912->dev, "No interrupt support, no core IRQ\n");
  142. return 0;
  143. }
  144. if (!pdata || !pdata->irq_base) {
  145. dev_warn(tps65912->dev, "No interrupt support, no IRQ base\n");
  146. return 0;
  147. }
  148. /* Clear unattended interrupts */
  149. tps65912->read(tps65912, TPS65912_INT_STS, 1, &reg);
  150. tps65912->write(tps65912, TPS65912_INT_STS, 1, &reg);
  151. tps65912->read(tps65912, TPS65912_INT_STS2, 1, &reg);
  152. tps65912->write(tps65912, TPS65912_INT_STS2, 1, &reg);
  153. tps65912->read(tps65912, TPS65912_INT_STS3, 1, &reg);
  154. tps65912->write(tps65912, TPS65912_INT_STS3, 1, &reg);
  155. tps65912->read(tps65912, TPS65912_INT_STS4, 1, &reg);
  156. tps65912->write(tps65912, TPS65912_INT_STS4, 1, &reg);
  157. /* Mask top level interrupts */
  158. tps65912->irq_mask = 0xFFFFFFFF;
  159. mutex_init(&tps65912->irq_lock);
  160. tps65912->chip_irq = irq;
  161. tps65912->irq_base = pdata->irq_base;
  162. tps65912->irq_num = TPS65912_NUM_IRQ;
  163. /* Register with genirq */
  164. for (cur_irq = tps65912->irq_base;
  165. cur_irq < tps65912->irq_num + tps65912->irq_base;
  166. cur_irq++) {
  167. irq_set_chip_data(cur_irq, tps65912);
  168. irq_set_chip_and_handler(cur_irq, &tps65912_irq_chip,
  169. handle_edge_irq);
  170. irq_set_nested_thread(cur_irq, 1);
  171. /* ARM needs us to explicitly flag the IRQ as valid
  172. * and will set them noprobe when we do so. */
  173. #ifdef CONFIG_ARM
  174. set_irq_flags(cur_irq, IRQF_VALID);
  175. #else
  176. irq_set_noprobe(cur_irq);
  177. #endif
  178. }
  179. ret = request_threaded_irq(irq, NULL, tps65912_irq, flags,
  180. "tps65912", tps65912);
  181. irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
  182. if (ret != 0)
  183. dev_err(tps65912->dev, "Failed to request IRQ: %d\n", ret);
  184. return ret;
  185. }
  186. int tps65912_irq_exit(struct tps65912 *tps65912)
  187. {
  188. free_irq(tps65912->chip_irq, tps65912);
  189. return 0;
  190. }