max77828-irq.c 8.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285
  1. /*
  2. * max77828-irq.c - Interrupt controller support for MAX77828
  3. *
  4. * Copyright (C) 2011 Samsung Electronics Co.Ltd
  5. * SangYoung Son <hello.son@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. *
  21. * This driver is based on max77828-irq.c
  22. */
  23. #include <linux/err.h>
  24. #include <linux/irq.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/gpio.h>
  27. #include <linux/mfd/max77828.h>
  28. #include <linux/mfd/max77828-private.h>
  29. static const u8 max77828_mask_reg[] = {
  30. [MUIC_INT1] = MAX77828_MUIC_REG_INTMASK1,
  31. [MUIC_INT2] = MAX77828_MUIC_REG_INTMASK2,
  32. [MUIC_INT3] = MAX77828_MUIC_REG_INTMASK3,
  33. };
  34. static struct i2c_client *get_i2c(struct max77828_dev *max77828,
  35. enum max77828_irq_source src)
  36. {
  37. switch (src) {
  38. case MUIC_INT1 ... MUIC_INT3:
  39. return max77828->muic;
  40. default:
  41. return ERR_PTR(-EINVAL);
  42. }
  43. }
  44. struct max77828_irq_data {
  45. int mask;
  46. enum max77828_irq_source group;
  47. };
  48. #define DECLARE_IRQ(idx, _group, _mask) \
  49. [(idx)] = { .group = (_group), .mask = (_mask) }
  50. static const struct max77828_irq_data max77828_irqs[] = {
  51. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT1_ADC, MUIC_INT1, 1 << 0),
  52. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT1_ADCERR, MUIC_INT1, 1 << 2),
  53. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT1_ADC1K, MUIC_INT1, 1 << 3),
  54. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT2_CHGTYP, MUIC_INT2, 1 << 0),
  55. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT2_CHGDETREUN, MUIC_INT2, 1 << 1),
  56. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT2_DCDTMR, MUIC_INT2, 1 << 2),
  57. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT2_DXOVP, MUIC_INT2, 1 << 3),
  58. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT2_VBVOLT, MUIC_INT2, 1 << 4),
  59. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT3_VBADC, MUIC_INT3, 1 << 0),
  60. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT3_VDNMON, MUIC_INT3, 1 << 1),
  61. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT3_DNRES, MUIC_INT3, 1 << 2),
  62. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT3_MPNACK, MUIC_INT3, 1 << 3),
  63. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT3_MRXBUFOW, MUIC_INT3, 1 << 4),
  64. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT3_MRXTRF, MUIC_INT3, 1 << 5),
  65. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT3_MRXPERR, MUIC_INT3, 1 << 6),
  66. DECLARE_IRQ(MAX77828_MUIC_IRQ_INT3_MRXRDY, MUIC_INT3, 1 << 7),
  67. };
  68. static void max77828_irq_lock(struct irq_data *data)
  69. {
  70. struct max77828_dev *max77828 = irq_get_chip_data(data->irq);
  71. mutex_lock(&max77828->irqlock);
  72. }
  73. static void max77828_irq_sync_unlock(struct irq_data *data)
  74. {
  75. struct max77828_dev *max77828 = irq_get_chip_data(data->irq);
  76. int i;
  77. for (i = 0; i < MAX77828_IRQ_GROUP_NR; i++) {
  78. u8 mask_reg = max77828_mask_reg[i];
  79. struct i2c_client *i2c = get_i2c(max77828, i);
  80. if (mask_reg == MAX77828_REG_INVALID ||
  81. IS_ERR_OR_NULL(i2c))
  82. continue;
  83. max77828->irq_masks_cache[i] = max77828->irq_masks_cur[i];
  84. max77828_write_reg(i2c, max77828_mask_reg[i],
  85. max77828->irq_masks_cur[i]);
  86. }
  87. mutex_unlock(&max77828->irqlock);
  88. }
  89. static const inline struct max77828_irq_data *
  90. irq_to_max77828_irq(struct max77828_dev *max77828, int irq)
  91. {
  92. return &max77828_irqs[irq - max77828->irq_base];
  93. }
  94. static void max77828_irq_mask(struct irq_data *data)
  95. {
  96. struct max77828_dev *max77828 = irq_get_chip_data(data->irq);
  97. const struct max77828_irq_data *irq_data =
  98. irq_to_max77828_irq(max77828, data->irq);
  99. if (irq_data->group >= MAX77828_IRQ_GROUP_NR)
  100. return;
  101. max77828->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
  102. }
  103. static void max77828_irq_unmask(struct irq_data *data)
  104. {
  105. struct max77828_dev *max77828 = irq_get_chip_data(data->irq);
  106. const struct max77828_irq_data *irq_data =
  107. irq_to_max77828_irq(max77828, data->irq);
  108. if (irq_data->group >= MAX77828_IRQ_GROUP_NR)
  109. return;
  110. max77828->irq_masks_cur[irq_data->group] |= irq_data->mask;
  111. }
  112. static struct irq_chip max77828_irq_chip = {
  113. .name = "max77828",
  114. .irq_bus_lock = max77828_irq_lock,
  115. .irq_bus_sync_unlock = max77828_irq_sync_unlock,
  116. .irq_mask = max77828_irq_mask,
  117. .irq_unmask = max77828_irq_unmask,
  118. };
  119. static irqreturn_t max77828_irq_thread(int irq, void *data)
  120. {
  121. struct max77828_dev *max77828 = data;
  122. u8 irq_reg[MAX77828_IRQ_GROUP_NR] = {0};
  123. u8 tmp_irq_reg[MAX77828_IRQ_GROUP_NR] = {};
  124. int i;
  125. pr_debug("%s: irq gpio pre-state(0x%02x)\n", __func__,
  126. gpio_get_value(max77828->irq_gpio));
  127. clear_retry:
  128. max77828_bulk_read(max77828->muic, MAX77828_MUIC_REG_INT1,
  129. MAX77828_NUM_IRQ_MUIC_REGS,
  130. &tmp_irq_reg[MUIC_INT1]);
  131. /* Or temp irq register to irq register for if it retries */
  132. for (i = MUIC_INT1; i < MAX77828_IRQ_GROUP_NR; i++)
  133. irq_reg[i] |= tmp_irq_reg[i];
  134. pr_info("%s: muic interrupt(0x%02x, 0x%02x, 0x%02x)\n",
  135. __func__, irq_reg[MUIC_INT1],
  136. irq_reg[MUIC_INT2], irq_reg[MUIC_INT3]);
  137. pr_debug("%s: irq gpio post-state(0x%02x)\n", __func__,
  138. gpio_get_value(max77828->irq_gpio));
  139. if (gpio_get_value(max77828->irq_gpio) == 0) {
  140. pr_warn("%s: irq_gpio is not High!\n", __func__);
  141. goto clear_retry;
  142. }
  143. /* Apply masking */
  144. /*
  145. for (i = 0; i < MAX77828_IRQ_GROUP_NR; i++) {
  146. irq_reg[i] &= max77828->irq_masks_cur[i];
  147. }
  148. */
  149. /* Report */
  150. for (i = 0; i < MAX77828_IRQ_NR; i++) {
  151. if (irq_reg[max77828_irqs[i].group] & max77828_irqs[i].mask)
  152. handle_nested_irq(max77828->irq_base + i);
  153. }
  154. return IRQ_HANDLED;
  155. }
  156. int max77828_irq_resume(struct max77828_dev *max77828)
  157. {
  158. int ret = 0;
  159. if (max77828->irq && max77828->irq_base)
  160. ret = max77828_irq_thread(max77828->irq_base, max77828);
  161. dev_info(max77828->dev, "%s: irq_resume ret=%d", __func__, ret);
  162. return ret >= 0 ? 0 : ret;
  163. }
  164. int max77828_irq_init(struct max77828_dev *max77828)
  165. {
  166. int i;
  167. int cur_irq;
  168. int ret;
  169. pr_info("func: %s, irq_gpio: %d, irq_base: %d\n", __func__,
  170. max77828->irq_gpio, max77828->irq_base);
  171. if (!max77828->irq_gpio) {
  172. dev_warn(max77828->dev, "No interrupt specified.\n");
  173. max77828->irq_base = 0;
  174. return 0;
  175. }
  176. if (!max77828->irq_base) {
  177. dev_err(max77828->dev, "No interrupt base specified.\n");
  178. return 0;
  179. }
  180. mutex_init(&max77828->irqlock);
  181. max77828->irq = gpio_to_irq(max77828->irq_gpio);
  182. ret = gpio_request(max77828->irq_gpio, "if_pmic_irq");
  183. if (ret) {
  184. dev_err(max77828->dev, "%s: failed requesting gpio %d\n",
  185. __func__, max77828->irq_gpio);
  186. return ret;
  187. }
  188. gpio_direction_input(max77828->irq_gpio);
  189. gpio_free(max77828->irq_gpio);
  190. /* Mask individual interrupt sources */
  191. for (i = 0; i < MAX77828_IRQ_GROUP_NR; i++) {
  192. struct i2c_client *i2c;
  193. /* MUIC IRQ 0:MASK 1:NOT MASK */
  194. /* Other IRQ 1:MASK 0:NOT MASK */
  195. if (i >= MUIC_INT1 && i <= MUIC_INT3) {
  196. max77828->irq_masks_cur[i] = 0x00;
  197. max77828->irq_masks_cache[i] = 0x00;
  198. } else {
  199. max77828->irq_masks_cur[i] = 0xff;
  200. max77828->irq_masks_cache[i] = 0xff;
  201. }
  202. i2c = get_i2c(max77828, i);
  203. if (IS_ERR_OR_NULL(i2c))
  204. continue;
  205. if (max77828_mask_reg[i] == MAX77828_REG_INVALID)
  206. continue;
  207. if (i >= MUIC_INT1 && i <= MUIC_INT3)
  208. max77828_write_reg(i2c, max77828_mask_reg[i], 0x00);
  209. else
  210. max77828_write_reg(i2c, max77828_mask_reg[i], 0xff);
  211. }
  212. /* Register with genirq */
  213. for (i = 0; i < MAX77828_IRQ_NR; i++) {
  214. cur_irq = i + max77828->irq_base;
  215. irq_set_chip_data(cur_irq, max77828);
  216. irq_set_chip_and_handler(cur_irq, &max77828_irq_chip,
  217. handle_edge_irq);
  218. irq_set_nested_thread(cur_irq, 1);
  219. #ifdef CONFIG_ARM
  220. set_irq_flags(cur_irq, IRQF_VALID);
  221. #else
  222. irq_set_noprobe(cur_irq);
  223. #endif
  224. }
  225. ret = request_threaded_irq(max77828->irq, NULL, max77828_irq_thread,
  226. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  227. "max77828-irq", max77828);
  228. if (ret) {
  229. dev_err(max77828->dev, "Failed to request IRQ %d: %d\n",
  230. max77828->irq, ret);
  231. return ret;
  232. }
  233. return 0;
  234. }
  235. void max77828_irq_exit(struct max77828_dev *max77828)
  236. {
  237. if (max77828->irq)
  238. free_irq(max77828->irq, max77828);
  239. }