Kconfig 9.0 KB

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  1. #
  2. # EDAC Kconfig
  3. # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
  4. # Licensed and distributed under the GPL
  5. #
  6. menuconfig EDAC
  7. bool "EDAC (Error Detection And Correction) reporting"
  8. depends on HAS_IOMEM
  9. depends on X86 || PPC || TILE
  10. help
  11. EDAC is designed to report errors in the core system.
  12. These are low-level errors that are reported in the CPU or
  13. supporting chipset or other subsystems:
  14. memory errors, cache errors, PCI errors, thermal throttling, etc..
  15. If unsure, select 'Y'.
  16. If this code is reporting problems on your system, please
  17. see the EDAC project web pages for more information at:
  18. <http://bluesmoke.sourceforge.net/>
  19. and:
  20. <http://buttersideup.com/edacwiki>
  21. There is also a mailing list for the EDAC project, which can
  22. be found via the sourceforge page.
  23. if EDAC
  24. comment "Reporting subsystems"
  25. config EDAC_DEBUG
  26. bool "Debugging"
  27. help
  28. This turns on debugging information for the entire EDAC
  29. sub-system. You can insert module with "debug_level=x", current
  30. there're four debug levels (x=0,1,2,3 from low to high).
  31. Usually you should select 'N'.
  32. config EDAC_DECODE_MCE
  33. tristate "Decode MCEs in human-readable form (only on AMD for now)"
  34. depends on CPU_SUP_AMD && X86_MCE_AMD
  35. default y
  36. ---help---
  37. Enable this option if you want to decode Machine Check Exceptions
  38. occurring on your machine in human-readable form.
  39. You should definitely say Y here in case you want to decode MCEs
  40. which occur really early upon boot, before the module infrastructure
  41. has been initialized.
  42. config EDAC_MCE_INJ
  43. tristate "Simple MCE injection interface over /sysfs"
  44. depends on EDAC_DECODE_MCE
  45. default n
  46. help
  47. This is a simple interface to inject MCEs over /sysfs and test
  48. the MCE decoding code in EDAC.
  49. This is currently AMD-only.
  50. config EDAC_MM_EDAC
  51. tristate "Main Memory EDAC (Error Detection And Correction) reporting"
  52. help
  53. Some systems are able to detect and correct errors in main
  54. memory. EDAC can report statistics on memory error
  55. detection and correction (EDAC - or commonly referred to ECC
  56. errors). EDAC will also try to decode where these errors
  57. occurred so that a particular failing memory module can be
  58. replaced. If unsure, select 'Y'.
  59. config EDAC_AMD64
  60. tristate "AMD64 (Opteron, Athlon64) K8, F10h"
  61. depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
  62. help
  63. Support for error detection and correction of DRAM ECC errors on
  64. the AMD64 families of memory controllers (K8 and F10h)
  65. config EDAC_AMD64_ERROR_INJECTION
  66. bool "Sysfs HW Error injection facilities"
  67. depends on EDAC_AMD64
  68. help
  69. Recent Opterons (Family 10h and later) provide for Memory Error
  70. Injection into the ECC detection circuits. The amd64_edac module
  71. allows the operator/user to inject Uncorrectable and Correctable
  72. errors into DRAM.
  73. When enabled, in each of the respective memory controller directories
  74. (/sys/devices/system/edac/mc/mcX), there are 3 input files:
  75. - inject_section (0..3, 16-byte section of 64-byte cacheline),
  76. - inject_word (0..8, 16-bit word of 16-byte section),
  77. - inject_ecc_vector (hex ecc vector: select bits of inject word)
  78. In addition, there are two control files, inject_read and inject_write,
  79. which trigger the DRAM ECC Read and Write respectively.
  80. config EDAC_AMD76X
  81. tristate "AMD 76x (760, 762, 768)"
  82. depends on EDAC_MM_EDAC && PCI && X86_32
  83. help
  84. Support for error detection and correction on the AMD 76x
  85. series of chipsets used with the Athlon processor.
  86. config EDAC_E7XXX
  87. tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
  88. depends on EDAC_MM_EDAC && PCI && X86_32
  89. help
  90. Support for error detection and correction on the Intel
  91. E7205, E7500, E7501 and E7505 server chipsets.
  92. config EDAC_E752X
  93. tristate "Intel e752x (e7520, e7525, e7320) and 3100"
  94. depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
  95. help
  96. Support for error detection and correction on the Intel
  97. E7520, E7525, E7320 server chipsets.
  98. config EDAC_I82443BXGX
  99. tristate "Intel 82443BX/GX (440BX/GX)"
  100. depends on EDAC_MM_EDAC && PCI && X86_32
  101. depends on BROKEN
  102. help
  103. Support for error detection and correction on the Intel
  104. 82443BX/GX memory controllers (440BX/GX chipsets).
  105. config EDAC_I82875P
  106. tristate "Intel 82875p (D82875P, E7210)"
  107. depends on EDAC_MM_EDAC && PCI && X86_32
  108. help
  109. Support for error detection and correction on the Intel
  110. DP82785P and E7210 server chipsets.
  111. config EDAC_I82975X
  112. tristate "Intel 82975x (D82975x)"
  113. depends on EDAC_MM_EDAC && PCI && X86
  114. help
  115. Support for error detection and correction on the Intel
  116. DP82975x server chipsets.
  117. config EDAC_I3000
  118. tristate "Intel 3000/3010"
  119. depends on EDAC_MM_EDAC && PCI && X86
  120. help
  121. Support for error detection and correction on the Intel
  122. 3000 and 3010 server chipsets.
  123. config EDAC_I3200
  124. tristate "Intel 3200"
  125. depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
  126. help
  127. Support for error detection and correction on the Intel
  128. 3200 and 3210 server chipsets.
  129. config EDAC_X38
  130. tristate "Intel X38"
  131. depends on EDAC_MM_EDAC && PCI && X86
  132. help
  133. Support for error detection and correction on the Intel
  134. X38 server chipsets.
  135. config EDAC_I5400
  136. tristate "Intel 5400 (Seaburg) chipsets"
  137. depends on EDAC_MM_EDAC && PCI && X86
  138. help
  139. Support for error detection and correction the Intel
  140. i5400 MCH chipset (Seaburg).
  141. config EDAC_I7CORE
  142. tristate "Intel i7 Core (Nehalem) processors"
  143. depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
  144. help
  145. Support for error detection and correction the Intel
  146. i7 Core (Nehalem) Integrated Memory Controller that exists on
  147. newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
  148. and Xeon 55xx processors.
  149. config EDAC_I82860
  150. tristate "Intel 82860"
  151. depends on EDAC_MM_EDAC && PCI && X86_32
  152. help
  153. Support for error detection and correction on the Intel
  154. 82860 chipset.
  155. config EDAC_R82600
  156. tristate "Radisys 82600 embedded chipset"
  157. depends on EDAC_MM_EDAC && PCI && X86_32
  158. help
  159. Support for error detection and correction on the Radisys
  160. 82600 embedded chipset.
  161. config EDAC_I5000
  162. tristate "Intel Greencreek/Blackford chipset"
  163. depends on EDAC_MM_EDAC && X86 && PCI
  164. help
  165. Support for error detection and correction the Intel
  166. Greekcreek/Blackford chipsets.
  167. config EDAC_I5100
  168. tristate "Intel San Clemente MCH"
  169. depends on EDAC_MM_EDAC && X86 && PCI
  170. help
  171. Support for error detection and correction the Intel
  172. San Clemente MCH.
  173. config EDAC_I7300
  174. tristate "Intel Clarksboro MCH"
  175. depends on EDAC_MM_EDAC && X86 && PCI
  176. help
  177. Support for error detection and correction the Intel
  178. Clarksboro MCH (Intel 7300 chipset).
  179. config EDAC_SBRIDGE
  180. tristate "Intel Sandy-Bridge Integrated MC"
  181. depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
  182. depends on PCI_MMCONFIG && EXPERIMENTAL
  183. help
  184. Support for error detection and correction the Intel
  185. Sandy Bridge Integrated Memory Controller.
  186. config EDAC_MPC85XX
  187. tristate "Freescale MPC83xx / MPC85xx"
  188. depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
  189. help
  190. Support for error detection and correction on the Freescale
  191. MPC8349, MPC8560, MPC8540, MPC8548
  192. config EDAC_MV64X60
  193. tristate "Marvell MV64x60"
  194. depends on EDAC_MM_EDAC && MV64X60
  195. help
  196. Support for error detection and correction on the Marvell
  197. MV64360 and MV64460 chipsets.
  198. config EDAC_PASEMI
  199. tristate "PA Semi PWRficient"
  200. depends on EDAC_MM_EDAC && PCI
  201. depends on PPC_PASEMI
  202. help
  203. Support for error detection and correction on PA Semi
  204. PWRficient.
  205. config EDAC_CELL
  206. tristate "Cell Broadband Engine memory controller"
  207. depends on EDAC_MM_EDAC && PPC_CELL_COMMON
  208. help
  209. Support for error detection and correction on the
  210. Cell Broadband Engine internal memory controller
  211. on platform without a hypervisor
  212. config EDAC_PPC4XX
  213. tristate "PPC4xx IBM DDR2 Memory Controller"
  214. depends on EDAC_MM_EDAC && 4xx
  215. help
  216. This enables support for EDAC on the ECC memory used
  217. with the IBM DDR2 memory controller found in various
  218. PowerPC 4xx embedded processors such as the 405EX[r],
  219. 440SP, 440SPe, 460EX, 460GT and 460SX.
  220. config EDAC_AMD8131
  221. tristate "AMD8131 HyperTransport PCI-X Tunnel"
  222. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  223. help
  224. Support for error detection and correction on the
  225. AMD8131 HyperTransport PCI-X Tunnel chip.
  226. Note, add more Kconfig dependency if it's adopted
  227. on some machine other than Maple.
  228. config EDAC_AMD8111
  229. tristate "AMD8111 HyperTransport I/O Hub"
  230. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  231. help
  232. Support for error detection and correction on the
  233. AMD8111 HyperTransport I/O Hub chip.
  234. Note, add more Kconfig dependency if it's adopted
  235. on some machine other than Maple.
  236. config EDAC_CPC925
  237. tristate "IBM CPC925 Memory Controller (PPC970FX)"
  238. depends on EDAC_MM_EDAC && PPC64
  239. help
  240. Support for error detection and correction on the
  241. IBM CPC925 Bridge and Memory Controller, which is
  242. a companion chip to the PowerPC 970 family of
  243. processors.
  244. config EDAC_TILE
  245. tristate "Tilera Memory Controller"
  246. depends on EDAC_MM_EDAC && TILE
  247. default y
  248. help
  249. Support for error detection and correction on the
  250. Tilera memory controller.
  251. endif # EDAC