swim3.c 32 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283
  1. /*
  2. * Driver for the SWIM3 (Super Woz Integrated Machine 3)
  3. * floppy controller found on Power Macintoshes.
  4. *
  5. * Copyright (C) 1996 Paul Mackerras.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. /*
  13. * TODO:
  14. * handle 2 drives
  15. * handle GCR disks
  16. */
  17. #undef DEBUG
  18. #include <linux/stddef.h>
  19. #include <linux/kernel.h>
  20. #include <linux/sched.h>
  21. #include <linux/timer.h>
  22. #include <linux/delay.h>
  23. #include <linux/fd.h>
  24. #include <linux/ioctl.h>
  25. #include <linux/blkdev.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/mutex.h>
  28. #include <linux/module.h>
  29. #include <linux/spinlock.h>
  30. #include <asm/io.h>
  31. #include <asm/dbdma.h>
  32. #include <asm/prom.h>
  33. #include <asm/uaccess.h>
  34. #include <asm/mediabay.h>
  35. #include <asm/machdep.h>
  36. #include <asm/pmac_feature.h>
  37. #define MAX_FLOPPIES 2
  38. static DEFINE_MUTEX(swim3_mutex);
  39. static struct gendisk *disks[MAX_FLOPPIES];
  40. enum swim_state {
  41. idle,
  42. locating,
  43. seeking,
  44. settling,
  45. do_transfer,
  46. jogging,
  47. available,
  48. revalidating,
  49. ejecting
  50. };
  51. #define REG(x) unsigned char x; char x ## _pad[15];
  52. /*
  53. * The names for these registers mostly represent speculation on my part.
  54. * It will be interesting to see how close they are to the names Apple uses.
  55. */
  56. struct swim3 {
  57. REG(data);
  58. REG(timer); /* counts down at 1MHz */
  59. REG(error);
  60. REG(mode);
  61. REG(select); /* controls CA0, CA1, CA2 and LSTRB signals */
  62. REG(setup);
  63. REG(control); /* writing bits clears them */
  64. REG(status); /* writing bits sets them in control */
  65. REG(intr);
  66. REG(nseek); /* # tracks to seek */
  67. REG(ctrack); /* current track number */
  68. REG(csect); /* current sector number */
  69. REG(gap3); /* size of gap 3 in track format */
  70. REG(sector); /* sector # to read or write */
  71. REG(nsect); /* # sectors to read or write */
  72. REG(intr_enable);
  73. };
  74. #define control_bic control
  75. #define control_bis status
  76. /* Bits in select register */
  77. #define CA_MASK 7
  78. #define LSTRB 8
  79. /* Bits in control register */
  80. #define DO_SEEK 0x80
  81. #define FORMAT 0x40
  82. #define SELECT 0x20
  83. #define WRITE_SECTORS 0x10
  84. #define DO_ACTION 0x08
  85. #define DRIVE2_ENABLE 0x04
  86. #define DRIVE_ENABLE 0x02
  87. #define INTR_ENABLE 0x01
  88. /* Bits in status register */
  89. #define FIFO_1BYTE 0x80
  90. #define FIFO_2BYTE 0x40
  91. #define ERROR 0x20
  92. #define DATA 0x08
  93. #define RDDATA 0x04
  94. #define INTR_PENDING 0x02
  95. #define MARK_BYTE 0x01
  96. /* Bits in intr and intr_enable registers */
  97. #define ERROR_INTR 0x20
  98. #define DATA_CHANGED 0x10
  99. #define TRANSFER_DONE 0x08
  100. #define SEEN_SECTOR 0x04
  101. #define SEEK_DONE 0x02
  102. #define TIMER_DONE 0x01
  103. /* Bits in error register */
  104. #define ERR_DATA_CRC 0x80
  105. #define ERR_ADDR_CRC 0x40
  106. #define ERR_OVERRUN 0x04
  107. #define ERR_UNDERRUN 0x01
  108. /* Bits in setup register */
  109. #define S_SW_RESET 0x80
  110. #define S_GCR_WRITE 0x40
  111. #define S_IBM_DRIVE 0x20
  112. #define S_TEST_MODE 0x10
  113. #define S_FCLK_DIV2 0x08
  114. #define S_GCR 0x04
  115. #define S_COPY_PROT 0x02
  116. #define S_INV_WDATA 0x01
  117. /* Select values for swim3_action */
  118. #define SEEK_POSITIVE 0
  119. #define SEEK_NEGATIVE 4
  120. #define STEP 1
  121. #define MOTOR_ON 2
  122. #define MOTOR_OFF 6
  123. #define INDEX 3
  124. #define EJECT 7
  125. #define SETMFM 9
  126. #define SETGCR 13
  127. /* Select values for swim3_select and swim3_readbit */
  128. #define STEP_DIR 0
  129. #define STEPPING 1
  130. #define MOTOR_ON 2
  131. #define RELAX 3 /* also eject in progress */
  132. #define READ_DATA_0 4
  133. #define TWOMEG_DRIVE 5
  134. #define SINGLE_SIDED 6 /* drive or diskette is 4MB type? */
  135. #define DRIVE_PRESENT 7
  136. #define DISK_IN 8
  137. #define WRITE_PROT 9
  138. #define TRACK_ZERO 10
  139. #define TACHO 11
  140. #define READ_DATA_1 12
  141. #define MFM_MODE 13
  142. #define SEEK_COMPLETE 14
  143. #define ONEMEG_MEDIA 15
  144. /* Definitions of values used in writing and formatting */
  145. #define DATA_ESCAPE 0x99
  146. #define GCR_SYNC_EXC 0x3f
  147. #define GCR_SYNC_CONV 0x80
  148. #define GCR_FIRST_MARK 0xd5
  149. #define GCR_SECOND_MARK 0xaa
  150. #define GCR_ADDR_MARK "\xd5\xaa\x00"
  151. #define GCR_DATA_MARK "\xd5\xaa\x0b"
  152. #define GCR_SLIP_BYTE "\x27\xaa"
  153. #define GCR_SELF_SYNC "\x3f\xbf\x1e\x34\x3c\x3f"
  154. #define DATA_99 "\x99\x99"
  155. #define MFM_ADDR_MARK "\x99\xa1\x99\xa1\x99\xa1\x99\xfe"
  156. #define MFM_INDEX_MARK "\x99\xc2\x99\xc2\x99\xc2\x99\xfc"
  157. #define MFM_GAP_LEN 12
  158. struct floppy_state {
  159. enum swim_state state;
  160. struct swim3 __iomem *swim3; /* hardware registers */
  161. struct dbdma_regs __iomem *dma; /* DMA controller registers */
  162. int swim3_intr; /* interrupt number for SWIM3 */
  163. int dma_intr; /* interrupt number for DMA channel */
  164. int cur_cyl; /* cylinder head is on, or -1 */
  165. int cur_sector; /* last sector we saw go past */
  166. int req_cyl; /* the cylinder for the current r/w request */
  167. int head; /* head number ditto */
  168. int req_sector; /* sector number ditto */
  169. int scount; /* # sectors we're transferring at present */
  170. int retries;
  171. int settle_time;
  172. int secpercyl; /* disk geometry information */
  173. int secpertrack;
  174. int total_secs;
  175. int write_prot; /* 1 if write-protected, 0 if not, -1 dunno */
  176. struct dbdma_cmd *dma_cmd;
  177. int ref_count;
  178. int expect_cyl;
  179. struct timer_list timeout;
  180. int timeout_pending;
  181. int ejected;
  182. wait_queue_head_t wait;
  183. int wanted;
  184. struct macio_dev *mdev;
  185. char dbdma_cmd_space[5 * sizeof(struct dbdma_cmd)];
  186. int index;
  187. struct request *cur_req;
  188. };
  189. #define swim3_err(fmt, arg...) dev_err(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
  190. #define swim3_warn(fmt, arg...) dev_warn(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
  191. #define swim3_info(fmt, arg...) dev_info(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
  192. #ifdef DEBUG
  193. #define swim3_dbg(fmt, arg...) dev_dbg(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg)
  194. #else
  195. #define swim3_dbg(fmt, arg...) do { } while(0)
  196. #endif
  197. static struct floppy_state floppy_states[MAX_FLOPPIES];
  198. static int floppy_count = 0;
  199. static DEFINE_SPINLOCK(swim3_lock);
  200. static unsigned short write_preamble[] = {
  201. 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, /* gap field */
  202. 0, 0, 0, 0, 0, 0, /* sync field */
  203. 0x99a1, 0x99a1, 0x99a1, 0x99fb, /* data address mark */
  204. 0x990f /* no escape for 512 bytes */
  205. };
  206. static unsigned short write_postamble[] = {
  207. 0x9904, /* insert CRC */
  208. 0x4e4e, 0x4e4e,
  209. 0x9908, /* stop writing */
  210. 0, 0, 0, 0, 0, 0
  211. };
  212. static void seek_track(struct floppy_state *fs, int n);
  213. static void init_dma(struct dbdma_cmd *cp, int cmd, void *buf, int count);
  214. static void act(struct floppy_state *fs);
  215. static void scan_timeout(unsigned long data);
  216. static void seek_timeout(unsigned long data);
  217. static void settle_timeout(unsigned long data);
  218. static void xfer_timeout(unsigned long data);
  219. static irqreturn_t swim3_interrupt(int irq, void *dev_id);
  220. /*static void fd_dma_interrupt(int irq, void *dev_id);*/
  221. static int grab_drive(struct floppy_state *fs, enum swim_state state,
  222. int interruptible);
  223. static void release_drive(struct floppy_state *fs);
  224. static int fd_eject(struct floppy_state *fs);
  225. static int floppy_ioctl(struct block_device *bdev, fmode_t mode,
  226. unsigned int cmd, unsigned long param);
  227. static int floppy_open(struct block_device *bdev, fmode_t mode);
  228. static int floppy_release(struct gendisk *disk, fmode_t mode);
  229. static unsigned int floppy_check_events(struct gendisk *disk,
  230. unsigned int clearing);
  231. static int floppy_revalidate(struct gendisk *disk);
  232. static bool swim3_end_request(struct floppy_state *fs, int err, unsigned int nr_bytes)
  233. {
  234. struct request *req = fs->cur_req;
  235. int rc;
  236. swim3_dbg(" end request, err=%d nr_bytes=%d, cur_req=%p\n",
  237. err, nr_bytes, req);
  238. if (err)
  239. nr_bytes = blk_rq_cur_bytes(req);
  240. rc = __blk_end_request(req, err, nr_bytes);
  241. if (rc)
  242. return true;
  243. fs->cur_req = NULL;
  244. return false;
  245. }
  246. static void swim3_select(struct floppy_state *fs, int sel)
  247. {
  248. struct swim3 __iomem *sw = fs->swim3;
  249. out_8(&sw->select, RELAX);
  250. if (sel & 8)
  251. out_8(&sw->control_bis, SELECT);
  252. else
  253. out_8(&sw->control_bic, SELECT);
  254. out_8(&sw->select, sel & CA_MASK);
  255. }
  256. static void swim3_action(struct floppy_state *fs, int action)
  257. {
  258. struct swim3 __iomem *sw = fs->swim3;
  259. swim3_select(fs, action);
  260. udelay(1);
  261. out_8(&sw->select, sw->select | LSTRB);
  262. udelay(2);
  263. out_8(&sw->select, sw->select & ~LSTRB);
  264. udelay(1);
  265. }
  266. static int swim3_readbit(struct floppy_state *fs, int bit)
  267. {
  268. struct swim3 __iomem *sw = fs->swim3;
  269. int stat;
  270. swim3_select(fs, bit);
  271. udelay(1);
  272. stat = in_8(&sw->status);
  273. return (stat & DATA) == 0;
  274. }
  275. static void start_request(struct floppy_state *fs)
  276. {
  277. struct request *req;
  278. unsigned long x;
  279. swim3_dbg("start request, initial state=%d\n", fs->state);
  280. if (fs->state == idle && fs->wanted) {
  281. fs->state = available;
  282. wake_up(&fs->wait);
  283. return;
  284. }
  285. while (fs->state == idle) {
  286. swim3_dbg("start request, idle loop, cur_req=%p\n", fs->cur_req);
  287. if (!fs->cur_req) {
  288. fs->cur_req = blk_fetch_request(disks[fs->index]->queue);
  289. swim3_dbg(" fetched request %p\n", fs->cur_req);
  290. if (!fs->cur_req)
  291. break;
  292. }
  293. req = fs->cur_req;
  294. if (fs->mdev->media_bay &&
  295. check_media_bay(fs->mdev->media_bay) != MB_FD) {
  296. swim3_dbg("%s", " media bay absent, dropping req\n");
  297. swim3_end_request(fs, -ENODEV, 0);
  298. continue;
  299. }
  300. #if 0 /* This is really too verbose */
  301. swim3_dbg("do_fd_req: dev=%s cmd=%d sec=%ld nr_sec=%u buf=%p\n",
  302. req->rq_disk->disk_name, req->cmd,
  303. (long)blk_rq_pos(req), blk_rq_sectors(req),
  304. req->buffer);
  305. swim3_dbg(" errors=%d current_nr_sectors=%u\n",
  306. req->errors, blk_rq_cur_sectors(req));
  307. #endif
  308. if (blk_rq_pos(req) >= fs->total_secs) {
  309. swim3_dbg(" pos out of bounds (%ld, max is %ld)\n",
  310. (long)blk_rq_pos(req), (long)fs->total_secs);
  311. swim3_end_request(fs, -EIO, 0);
  312. continue;
  313. }
  314. if (fs->ejected) {
  315. swim3_dbg("%s", " disk ejected\n");
  316. swim3_end_request(fs, -EIO, 0);
  317. continue;
  318. }
  319. if (rq_data_dir(req) == WRITE) {
  320. if (fs->write_prot < 0)
  321. fs->write_prot = swim3_readbit(fs, WRITE_PROT);
  322. if (fs->write_prot) {
  323. swim3_dbg("%s", " try to write, disk write protected\n");
  324. swim3_end_request(fs, -EIO, 0);
  325. continue;
  326. }
  327. }
  328. /* Do not remove the cast. blk_rq_pos(req) is now a
  329. * sector_t and can be 64 bits, but it will never go
  330. * past 32 bits for this driver anyway, so we can
  331. * safely cast it down and not have to do a 64/32
  332. * division
  333. */
  334. fs->req_cyl = ((long)blk_rq_pos(req)) / fs->secpercyl;
  335. x = ((long)blk_rq_pos(req)) % fs->secpercyl;
  336. fs->head = x / fs->secpertrack;
  337. fs->req_sector = x % fs->secpertrack + 1;
  338. fs->state = do_transfer;
  339. fs->retries = 0;
  340. act(fs);
  341. }
  342. }
  343. static void do_fd_request(struct request_queue * q)
  344. {
  345. start_request(q->queuedata);
  346. }
  347. static void set_timeout(struct floppy_state *fs, int nticks,
  348. void (*proc)(unsigned long))
  349. {
  350. if (fs->timeout_pending)
  351. del_timer(&fs->timeout);
  352. fs->timeout.expires = jiffies + nticks;
  353. fs->timeout.function = proc;
  354. fs->timeout.data = (unsigned long) fs;
  355. add_timer(&fs->timeout);
  356. fs->timeout_pending = 1;
  357. }
  358. static inline void scan_track(struct floppy_state *fs)
  359. {
  360. struct swim3 __iomem *sw = fs->swim3;
  361. swim3_select(fs, READ_DATA_0);
  362. in_8(&sw->intr); /* clear SEEN_SECTOR bit */
  363. in_8(&sw->error);
  364. out_8(&sw->intr_enable, SEEN_SECTOR);
  365. out_8(&sw->control_bis, DO_ACTION);
  366. /* enable intr when track found */
  367. set_timeout(fs, HZ, scan_timeout); /* enable timeout */
  368. }
  369. static inline void seek_track(struct floppy_state *fs, int n)
  370. {
  371. struct swim3 __iomem *sw = fs->swim3;
  372. if (n >= 0) {
  373. swim3_action(fs, SEEK_POSITIVE);
  374. sw->nseek = n;
  375. } else {
  376. swim3_action(fs, SEEK_NEGATIVE);
  377. sw->nseek = -n;
  378. }
  379. fs->expect_cyl = (fs->cur_cyl >= 0)? fs->cur_cyl + n: -1;
  380. swim3_select(fs, STEP);
  381. in_8(&sw->error);
  382. /* enable intr when seek finished */
  383. out_8(&sw->intr_enable, SEEK_DONE);
  384. out_8(&sw->control_bis, DO_SEEK);
  385. set_timeout(fs, 3*HZ, seek_timeout); /* enable timeout */
  386. fs->settle_time = 0;
  387. }
  388. static inline void init_dma(struct dbdma_cmd *cp, int cmd,
  389. void *buf, int count)
  390. {
  391. st_le16(&cp->req_count, count);
  392. st_le16(&cp->command, cmd);
  393. st_le32(&cp->phy_addr, virt_to_bus(buf));
  394. cp->xfer_status = 0;
  395. }
  396. static inline void setup_transfer(struct floppy_state *fs)
  397. {
  398. int n;
  399. struct swim3 __iomem *sw = fs->swim3;
  400. struct dbdma_cmd *cp = fs->dma_cmd;
  401. struct dbdma_regs __iomem *dr = fs->dma;
  402. struct request *req = fs->cur_req;
  403. if (blk_rq_cur_sectors(req) <= 0) {
  404. swim3_warn("%s", "Transfer 0 sectors ?\n");
  405. return;
  406. }
  407. if (rq_data_dir(req) == WRITE)
  408. n = 1;
  409. else {
  410. n = fs->secpertrack - fs->req_sector + 1;
  411. if (n > blk_rq_cur_sectors(req))
  412. n = blk_rq_cur_sectors(req);
  413. }
  414. swim3_dbg(" setup xfer at sect %d (of %d) head %d for %d\n",
  415. fs->req_sector, fs->secpertrack, fs->head, n);
  416. fs->scount = n;
  417. swim3_select(fs, fs->head? READ_DATA_1: READ_DATA_0);
  418. out_8(&sw->sector, fs->req_sector);
  419. out_8(&sw->nsect, n);
  420. out_8(&sw->gap3, 0);
  421. out_le32(&dr->cmdptr, virt_to_bus(cp));
  422. if (rq_data_dir(req) == WRITE) {
  423. /* Set up 3 dma commands: write preamble, data, postamble */
  424. init_dma(cp, OUTPUT_MORE, write_preamble, sizeof(write_preamble));
  425. ++cp;
  426. init_dma(cp, OUTPUT_MORE, req->buffer, 512);
  427. ++cp;
  428. init_dma(cp, OUTPUT_LAST, write_postamble, sizeof(write_postamble));
  429. } else {
  430. init_dma(cp, INPUT_LAST, req->buffer, n * 512);
  431. }
  432. ++cp;
  433. out_le16(&cp->command, DBDMA_STOP);
  434. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  435. in_8(&sw->error);
  436. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  437. if (rq_data_dir(req) == WRITE)
  438. out_8(&sw->control_bis, WRITE_SECTORS);
  439. in_8(&sw->intr);
  440. out_le32(&dr->control, (RUN << 16) | RUN);
  441. /* enable intr when transfer complete */
  442. out_8(&sw->intr_enable, TRANSFER_DONE);
  443. out_8(&sw->control_bis, DO_ACTION);
  444. set_timeout(fs, 2*HZ, xfer_timeout); /* enable timeout */
  445. }
  446. static void act(struct floppy_state *fs)
  447. {
  448. for (;;) {
  449. swim3_dbg(" act loop, state=%d, req_cyl=%d, cur_cyl=%d\n",
  450. fs->state, fs->req_cyl, fs->cur_cyl);
  451. switch (fs->state) {
  452. case idle:
  453. return; /* XXX shouldn't get here */
  454. case locating:
  455. if (swim3_readbit(fs, TRACK_ZERO)) {
  456. swim3_dbg("%s", " locate track 0\n");
  457. fs->cur_cyl = 0;
  458. if (fs->req_cyl == 0)
  459. fs->state = do_transfer;
  460. else
  461. fs->state = seeking;
  462. break;
  463. }
  464. scan_track(fs);
  465. return;
  466. case seeking:
  467. if (fs->cur_cyl < 0) {
  468. fs->expect_cyl = -1;
  469. fs->state = locating;
  470. break;
  471. }
  472. if (fs->req_cyl == fs->cur_cyl) {
  473. swim3_warn("%s", "Whoops, seeking 0\n");
  474. fs->state = do_transfer;
  475. break;
  476. }
  477. seek_track(fs, fs->req_cyl - fs->cur_cyl);
  478. return;
  479. case settling:
  480. /* check for SEEK_COMPLETE after 30ms */
  481. fs->settle_time = (HZ + 32) / 33;
  482. set_timeout(fs, fs->settle_time, settle_timeout);
  483. return;
  484. case do_transfer:
  485. if (fs->cur_cyl != fs->req_cyl) {
  486. if (fs->retries > 5) {
  487. swim3_err("Wrong cylinder in transfer, want: %d got %d\n",
  488. fs->req_cyl, fs->cur_cyl);
  489. swim3_end_request(fs, -EIO, 0);
  490. fs->state = idle;
  491. return;
  492. }
  493. fs->state = seeking;
  494. break;
  495. }
  496. setup_transfer(fs);
  497. return;
  498. case jogging:
  499. seek_track(fs, -5);
  500. return;
  501. default:
  502. swim3_err("Unknown state %d\n", fs->state);
  503. return;
  504. }
  505. }
  506. }
  507. static void scan_timeout(unsigned long data)
  508. {
  509. struct floppy_state *fs = (struct floppy_state *) data;
  510. struct swim3 __iomem *sw = fs->swim3;
  511. unsigned long flags;
  512. swim3_dbg("* scan timeout, state=%d\n", fs->state);
  513. spin_lock_irqsave(&swim3_lock, flags);
  514. fs->timeout_pending = 0;
  515. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  516. out_8(&sw->select, RELAX);
  517. out_8(&sw->intr_enable, 0);
  518. fs->cur_cyl = -1;
  519. if (fs->retries > 5) {
  520. swim3_end_request(fs, -EIO, 0);
  521. fs->state = idle;
  522. start_request(fs);
  523. } else {
  524. fs->state = jogging;
  525. act(fs);
  526. }
  527. spin_unlock_irqrestore(&swim3_lock, flags);
  528. }
  529. static void seek_timeout(unsigned long data)
  530. {
  531. struct floppy_state *fs = (struct floppy_state *) data;
  532. struct swim3 __iomem *sw = fs->swim3;
  533. unsigned long flags;
  534. swim3_dbg("* seek timeout, state=%d\n", fs->state);
  535. spin_lock_irqsave(&swim3_lock, flags);
  536. fs->timeout_pending = 0;
  537. out_8(&sw->control_bic, DO_SEEK);
  538. out_8(&sw->select, RELAX);
  539. out_8(&sw->intr_enable, 0);
  540. swim3_err("%s", "Seek timeout\n");
  541. swim3_end_request(fs, -EIO, 0);
  542. fs->state = idle;
  543. start_request(fs);
  544. spin_unlock_irqrestore(&swim3_lock, flags);
  545. }
  546. static void settle_timeout(unsigned long data)
  547. {
  548. struct floppy_state *fs = (struct floppy_state *) data;
  549. struct swim3 __iomem *sw = fs->swim3;
  550. unsigned long flags;
  551. swim3_dbg("* settle timeout, state=%d\n", fs->state);
  552. spin_lock_irqsave(&swim3_lock, flags);
  553. fs->timeout_pending = 0;
  554. if (swim3_readbit(fs, SEEK_COMPLETE)) {
  555. out_8(&sw->select, RELAX);
  556. fs->state = locating;
  557. act(fs);
  558. goto unlock;
  559. }
  560. out_8(&sw->select, RELAX);
  561. if (fs->settle_time < 2*HZ) {
  562. ++fs->settle_time;
  563. set_timeout(fs, 1, settle_timeout);
  564. goto unlock;
  565. }
  566. swim3_err("%s", "Seek settle timeout\n");
  567. swim3_end_request(fs, -EIO, 0);
  568. fs->state = idle;
  569. start_request(fs);
  570. unlock:
  571. spin_unlock_irqrestore(&swim3_lock, flags);
  572. }
  573. static void xfer_timeout(unsigned long data)
  574. {
  575. struct floppy_state *fs = (struct floppy_state *) data;
  576. struct swim3 __iomem *sw = fs->swim3;
  577. struct dbdma_regs __iomem *dr = fs->dma;
  578. unsigned long flags;
  579. int n;
  580. swim3_dbg("* xfer timeout, state=%d\n", fs->state);
  581. spin_lock_irqsave(&swim3_lock, flags);
  582. fs->timeout_pending = 0;
  583. out_le32(&dr->control, RUN << 16);
  584. /* We must wait a bit for dbdma to stop */
  585. for (n = 0; (in_le32(&dr->status) & ACTIVE) && n < 1000; n++)
  586. udelay(1);
  587. out_8(&sw->intr_enable, 0);
  588. out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION);
  589. out_8(&sw->select, RELAX);
  590. swim3_err("Timeout %sing sector %ld\n",
  591. (rq_data_dir(fs->cur_req)==WRITE? "writ": "read"),
  592. (long)blk_rq_pos(fs->cur_req));
  593. swim3_end_request(fs, -EIO, 0);
  594. fs->state = idle;
  595. start_request(fs);
  596. spin_unlock_irqrestore(&swim3_lock, flags);
  597. }
  598. static irqreturn_t swim3_interrupt(int irq, void *dev_id)
  599. {
  600. struct floppy_state *fs = (struct floppy_state *) dev_id;
  601. struct swim3 __iomem *sw = fs->swim3;
  602. int intr, err, n;
  603. int stat, resid;
  604. struct dbdma_regs __iomem *dr;
  605. struct dbdma_cmd *cp;
  606. unsigned long flags;
  607. struct request *req = fs->cur_req;
  608. swim3_dbg("* interrupt, state=%d\n", fs->state);
  609. spin_lock_irqsave(&swim3_lock, flags);
  610. intr = in_8(&sw->intr);
  611. err = (intr & ERROR_INTR)? in_8(&sw->error): 0;
  612. if ((intr & ERROR_INTR) && fs->state != do_transfer)
  613. swim3_err("Non-transfer error interrupt: state=%d, dir=%x, intr=%x, err=%x\n",
  614. fs->state, rq_data_dir(req), intr, err);
  615. switch (fs->state) {
  616. case locating:
  617. if (intr & SEEN_SECTOR) {
  618. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  619. out_8(&sw->select, RELAX);
  620. out_8(&sw->intr_enable, 0);
  621. del_timer(&fs->timeout);
  622. fs->timeout_pending = 0;
  623. if (sw->ctrack == 0xff) {
  624. swim3_err("%s", "Seen sector but cyl=ff?\n");
  625. fs->cur_cyl = -1;
  626. if (fs->retries > 5) {
  627. swim3_end_request(fs, -EIO, 0);
  628. fs->state = idle;
  629. start_request(fs);
  630. } else {
  631. fs->state = jogging;
  632. act(fs);
  633. }
  634. break;
  635. }
  636. fs->cur_cyl = sw->ctrack;
  637. fs->cur_sector = sw->csect;
  638. if (fs->expect_cyl != -1 && fs->expect_cyl != fs->cur_cyl)
  639. swim3_err("Expected cyl %d, got %d\n",
  640. fs->expect_cyl, fs->cur_cyl);
  641. fs->state = do_transfer;
  642. act(fs);
  643. }
  644. break;
  645. case seeking:
  646. case jogging:
  647. if (sw->nseek == 0) {
  648. out_8(&sw->control_bic, DO_SEEK);
  649. out_8(&sw->select, RELAX);
  650. out_8(&sw->intr_enable, 0);
  651. del_timer(&fs->timeout);
  652. fs->timeout_pending = 0;
  653. if (fs->state == seeking)
  654. ++fs->retries;
  655. fs->state = settling;
  656. act(fs);
  657. }
  658. break;
  659. case settling:
  660. out_8(&sw->intr_enable, 0);
  661. del_timer(&fs->timeout);
  662. fs->timeout_pending = 0;
  663. act(fs);
  664. break;
  665. case do_transfer:
  666. if ((intr & (ERROR_INTR | TRANSFER_DONE)) == 0)
  667. break;
  668. out_8(&sw->intr_enable, 0);
  669. out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION);
  670. out_8(&sw->select, RELAX);
  671. del_timer(&fs->timeout);
  672. fs->timeout_pending = 0;
  673. dr = fs->dma;
  674. cp = fs->dma_cmd;
  675. if (rq_data_dir(req) == WRITE)
  676. ++cp;
  677. /*
  678. * Check that the main data transfer has finished.
  679. * On writing, the swim3 sometimes doesn't use
  680. * up all the bytes of the postamble, so we can still
  681. * see DMA active here. That doesn't matter as long
  682. * as all the sector data has been transferred.
  683. */
  684. if ((intr & ERROR_INTR) == 0 && cp->xfer_status == 0) {
  685. /* wait a little while for DMA to complete */
  686. for (n = 0; n < 100; ++n) {
  687. if (cp->xfer_status != 0)
  688. break;
  689. udelay(1);
  690. barrier();
  691. }
  692. }
  693. /* turn off DMA */
  694. out_le32(&dr->control, (RUN | PAUSE) << 16);
  695. stat = ld_le16(&cp->xfer_status);
  696. resid = ld_le16(&cp->res_count);
  697. if (intr & ERROR_INTR) {
  698. n = fs->scount - 1 - resid / 512;
  699. if (n > 0) {
  700. blk_update_request(req, 0, n << 9);
  701. fs->req_sector += n;
  702. }
  703. if (fs->retries < 5) {
  704. ++fs->retries;
  705. act(fs);
  706. } else {
  707. swim3_err("Error %sing block %ld (err=%x)\n",
  708. rq_data_dir(req) == WRITE? "writ": "read",
  709. (long)blk_rq_pos(req), err);
  710. swim3_end_request(fs, -EIO, 0);
  711. fs->state = idle;
  712. }
  713. } else {
  714. if ((stat & ACTIVE) == 0 || resid != 0) {
  715. /* musta been an error */
  716. swim3_err("fd dma error: stat=%x resid=%d\n", stat, resid);
  717. swim3_err(" state=%d, dir=%x, intr=%x, err=%x\n",
  718. fs->state, rq_data_dir(req), intr, err);
  719. swim3_end_request(fs, -EIO, 0);
  720. fs->state = idle;
  721. start_request(fs);
  722. break;
  723. }
  724. fs->retries = 0;
  725. if (swim3_end_request(fs, 0, fs->scount << 9)) {
  726. fs->req_sector += fs->scount;
  727. if (fs->req_sector > fs->secpertrack) {
  728. fs->req_sector -= fs->secpertrack;
  729. if (++fs->head > 1) {
  730. fs->head = 0;
  731. ++fs->req_cyl;
  732. }
  733. }
  734. act(fs);
  735. } else
  736. fs->state = idle;
  737. }
  738. if (fs->state == idle)
  739. start_request(fs);
  740. break;
  741. default:
  742. swim3_err("Don't know what to do in state %d\n", fs->state);
  743. }
  744. spin_unlock_irqrestore(&swim3_lock, flags);
  745. return IRQ_HANDLED;
  746. }
  747. /*
  748. static void fd_dma_interrupt(int irq, void *dev_id)
  749. {
  750. }
  751. */
  752. /* Called under the mutex to grab exclusive access to a drive */
  753. static int grab_drive(struct floppy_state *fs, enum swim_state state,
  754. int interruptible)
  755. {
  756. unsigned long flags;
  757. swim3_dbg("%s", "-> grab drive\n");
  758. spin_lock_irqsave(&swim3_lock, flags);
  759. if (fs->state != idle && fs->state != available) {
  760. ++fs->wanted;
  761. while (fs->state != available) {
  762. spin_unlock_irqrestore(&swim3_lock, flags);
  763. if (interruptible && signal_pending(current)) {
  764. --fs->wanted;
  765. return -EINTR;
  766. }
  767. interruptible_sleep_on(&fs->wait);
  768. spin_lock_irqsave(&swim3_lock, flags);
  769. }
  770. --fs->wanted;
  771. }
  772. fs->state = state;
  773. spin_unlock_irqrestore(&swim3_lock, flags);
  774. return 0;
  775. }
  776. static void release_drive(struct floppy_state *fs)
  777. {
  778. unsigned long flags;
  779. swim3_dbg("%s", "-> release drive\n");
  780. spin_lock_irqsave(&swim3_lock, flags);
  781. fs->state = idle;
  782. start_request(fs);
  783. spin_unlock_irqrestore(&swim3_lock, flags);
  784. }
  785. static int fd_eject(struct floppy_state *fs)
  786. {
  787. int err, n;
  788. err = grab_drive(fs, ejecting, 1);
  789. if (err)
  790. return err;
  791. swim3_action(fs, EJECT);
  792. for (n = 20; n > 0; --n) {
  793. if (signal_pending(current)) {
  794. err = -EINTR;
  795. break;
  796. }
  797. swim3_select(fs, RELAX);
  798. schedule_timeout_interruptible(1);
  799. if (swim3_readbit(fs, DISK_IN) == 0)
  800. break;
  801. }
  802. swim3_select(fs, RELAX);
  803. udelay(150);
  804. fs->ejected = 1;
  805. release_drive(fs);
  806. return err;
  807. }
  808. static struct floppy_struct floppy_type =
  809. { 2880,18,2,80,0,0x1B,0x00,0xCF,0x6C,NULL }; /* 7 1.44MB 3.5" */
  810. static int floppy_locked_ioctl(struct block_device *bdev, fmode_t mode,
  811. unsigned int cmd, unsigned long param)
  812. {
  813. struct floppy_state *fs = bdev->bd_disk->private_data;
  814. int err;
  815. if ((cmd & 0x80) && !capable(CAP_SYS_ADMIN))
  816. return -EPERM;
  817. if (fs->mdev->media_bay &&
  818. check_media_bay(fs->mdev->media_bay) != MB_FD)
  819. return -ENXIO;
  820. switch (cmd) {
  821. case FDEJECT:
  822. if (fs->ref_count != 1)
  823. return -EBUSY;
  824. err = fd_eject(fs);
  825. return err;
  826. case FDGETPRM:
  827. if (copy_to_user((void __user *) param, &floppy_type,
  828. sizeof(struct floppy_struct)))
  829. return -EFAULT;
  830. return 0;
  831. }
  832. return -ENOTTY;
  833. }
  834. static int floppy_ioctl(struct block_device *bdev, fmode_t mode,
  835. unsigned int cmd, unsigned long param)
  836. {
  837. int ret;
  838. mutex_lock(&swim3_mutex);
  839. ret = floppy_locked_ioctl(bdev, mode, cmd, param);
  840. mutex_unlock(&swim3_mutex);
  841. return ret;
  842. }
  843. static int floppy_open(struct block_device *bdev, fmode_t mode)
  844. {
  845. struct floppy_state *fs = bdev->bd_disk->private_data;
  846. struct swim3 __iomem *sw = fs->swim3;
  847. int n, err = 0;
  848. if (fs->ref_count == 0) {
  849. if (fs->mdev->media_bay &&
  850. check_media_bay(fs->mdev->media_bay) != MB_FD)
  851. return -ENXIO;
  852. out_8(&sw->setup, S_IBM_DRIVE | S_FCLK_DIV2);
  853. out_8(&sw->control_bic, 0xff);
  854. out_8(&sw->mode, 0x95);
  855. udelay(10);
  856. out_8(&sw->intr_enable, 0);
  857. out_8(&sw->control_bis, DRIVE_ENABLE | INTR_ENABLE);
  858. swim3_action(fs, MOTOR_ON);
  859. fs->write_prot = -1;
  860. fs->cur_cyl = -1;
  861. for (n = 0; n < 2 * HZ; ++n) {
  862. if (n >= HZ/30 && swim3_readbit(fs, SEEK_COMPLETE))
  863. break;
  864. if (signal_pending(current)) {
  865. err = -EINTR;
  866. break;
  867. }
  868. swim3_select(fs, RELAX);
  869. schedule_timeout_interruptible(1);
  870. }
  871. if (err == 0 && (swim3_readbit(fs, SEEK_COMPLETE) == 0
  872. || swim3_readbit(fs, DISK_IN) == 0))
  873. err = -ENXIO;
  874. swim3_action(fs, SETMFM);
  875. swim3_select(fs, RELAX);
  876. } else if (fs->ref_count == -1 || mode & FMODE_EXCL)
  877. return -EBUSY;
  878. if (err == 0 && (mode & FMODE_NDELAY) == 0
  879. && (mode & (FMODE_READ|FMODE_WRITE))) {
  880. check_disk_change(bdev);
  881. if (fs->ejected)
  882. err = -ENXIO;
  883. }
  884. if (err == 0 && (mode & FMODE_WRITE)) {
  885. if (fs->write_prot < 0)
  886. fs->write_prot = swim3_readbit(fs, WRITE_PROT);
  887. if (fs->write_prot)
  888. err = -EROFS;
  889. }
  890. if (err) {
  891. if (fs->ref_count == 0) {
  892. swim3_action(fs, MOTOR_OFF);
  893. out_8(&sw->control_bic, DRIVE_ENABLE | INTR_ENABLE);
  894. swim3_select(fs, RELAX);
  895. }
  896. return err;
  897. }
  898. if (mode & FMODE_EXCL)
  899. fs->ref_count = -1;
  900. else
  901. ++fs->ref_count;
  902. return 0;
  903. }
  904. static int floppy_unlocked_open(struct block_device *bdev, fmode_t mode)
  905. {
  906. int ret;
  907. mutex_lock(&swim3_mutex);
  908. ret = floppy_open(bdev, mode);
  909. mutex_unlock(&swim3_mutex);
  910. return ret;
  911. }
  912. static int floppy_release(struct gendisk *disk, fmode_t mode)
  913. {
  914. struct floppy_state *fs = disk->private_data;
  915. struct swim3 __iomem *sw = fs->swim3;
  916. mutex_lock(&swim3_mutex);
  917. if (fs->ref_count > 0 && --fs->ref_count == 0) {
  918. swim3_action(fs, MOTOR_OFF);
  919. out_8(&sw->control_bic, 0xff);
  920. swim3_select(fs, RELAX);
  921. }
  922. mutex_unlock(&swim3_mutex);
  923. return 0;
  924. }
  925. static unsigned int floppy_check_events(struct gendisk *disk,
  926. unsigned int clearing)
  927. {
  928. struct floppy_state *fs = disk->private_data;
  929. return fs->ejected ? DISK_EVENT_MEDIA_CHANGE : 0;
  930. }
  931. static int floppy_revalidate(struct gendisk *disk)
  932. {
  933. struct floppy_state *fs = disk->private_data;
  934. struct swim3 __iomem *sw;
  935. int ret, n;
  936. if (fs->mdev->media_bay &&
  937. check_media_bay(fs->mdev->media_bay) != MB_FD)
  938. return -ENXIO;
  939. sw = fs->swim3;
  940. grab_drive(fs, revalidating, 0);
  941. out_8(&sw->intr_enable, 0);
  942. out_8(&sw->control_bis, DRIVE_ENABLE);
  943. swim3_action(fs, MOTOR_ON); /* necessary? */
  944. fs->write_prot = -1;
  945. fs->cur_cyl = -1;
  946. mdelay(1);
  947. for (n = HZ; n > 0; --n) {
  948. if (swim3_readbit(fs, SEEK_COMPLETE))
  949. break;
  950. if (signal_pending(current))
  951. break;
  952. swim3_select(fs, RELAX);
  953. schedule_timeout_interruptible(1);
  954. }
  955. ret = swim3_readbit(fs, SEEK_COMPLETE) == 0
  956. || swim3_readbit(fs, DISK_IN) == 0;
  957. if (ret)
  958. swim3_action(fs, MOTOR_OFF);
  959. else {
  960. fs->ejected = 0;
  961. swim3_action(fs, SETMFM);
  962. }
  963. swim3_select(fs, RELAX);
  964. release_drive(fs);
  965. return ret;
  966. }
  967. static const struct block_device_operations floppy_fops = {
  968. .open = floppy_unlocked_open,
  969. .release = floppy_release,
  970. .ioctl = floppy_ioctl,
  971. .check_events = floppy_check_events,
  972. .revalidate_disk= floppy_revalidate,
  973. };
  974. static void swim3_mb_event(struct macio_dev* mdev, int mb_state)
  975. {
  976. struct floppy_state *fs = macio_get_drvdata(mdev);
  977. struct swim3 __iomem *sw = fs->swim3;
  978. if (!fs)
  979. return;
  980. if (mb_state != MB_FD)
  981. return;
  982. /* Clear state */
  983. out_8(&sw->intr_enable, 0);
  984. in_8(&sw->intr);
  985. in_8(&sw->error);
  986. }
  987. static int swim3_add_device(struct macio_dev *mdev, int index)
  988. {
  989. struct device_node *swim = mdev->ofdev.dev.of_node;
  990. struct floppy_state *fs = &floppy_states[index];
  991. int rc = -EBUSY;
  992. /* Do this first for message macros */
  993. memset(fs, 0, sizeof(*fs));
  994. fs->mdev = mdev;
  995. fs->index = index;
  996. /* Check & Request resources */
  997. if (macio_resource_count(mdev) < 2) {
  998. swim3_err("%s", "No address in device-tree\n");
  999. return -ENXIO;
  1000. }
  1001. if (macio_irq_count(mdev) < 1) {
  1002. swim3_err("%s", "No interrupt in device-tree\n");
  1003. return -ENXIO;
  1004. }
  1005. if (macio_request_resource(mdev, 0, "swim3 (mmio)")) {
  1006. swim3_err("%s", "Can't request mmio resource\n");
  1007. return -EBUSY;
  1008. }
  1009. if (macio_request_resource(mdev, 1, "swim3 (dma)")) {
  1010. swim3_err("%s", "Can't request dma resource\n");
  1011. macio_release_resource(mdev, 0);
  1012. return -EBUSY;
  1013. }
  1014. dev_set_drvdata(&mdev->ofdev.dev, fs);
  1015. if (mdev->media_bay == NULL)
  1016. pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 1);
  1017. fs->state = idle;
  1018. fs->swim3 = (struct swim3 __iomem *)
  1019. ioremap(macio_resource_start(mdev, 0), 0x200);
  1020. if (fs->swim3 == NULL) {
  1021. swim3_err("%s", "Couldn't map mmio registers\n");
  1022. rc = -ENOMEM;
  1023. goto out_release;
  1024. }
  1025. fs->dma = (struct dbdma_regs __iomem *)
  1026. ioremap(macio_resource_start(mdev, 1), 0x200);
  1027. if (fs->dma == NULL) {
  1028. swim3_err("%s", "Couldn't map dma registers\n");
  1029. iounmap(fs->swim3);
  1030. rc = -ENOMEM;
  1031. goto out_release;
  1032. }
  1033. fs->swim3_intr = macio_irq(mdev, 0);
  1034. fs->dma_intr = macio_irq(mdev, 1);
  1035. fs->cur_cyl = -1;
  1036. fs->cur_sector = -1;
  1037. fs->secpercyl = 36;
  1038. fs->secpertrack = 18;
  1039. fs->total_secs = 2880;
  1040. init_waitqueue_head(&fs->wait);
  1041. fs->dma_cmd = (struct dbdma_cmd *) DBDMA_ALIGN(fs->dbdma_cmd_space);
  1042. memset(fs->dma_cmd, 0, 2 * sizeof(struct dbdma_cmd));
  1043. st_le16(&fs->dma_cmd[1].command, DBDMA_STOP);
  1044. if (mdev->media_bay == NULL || check_media_bay(mdev->media_bay) == MB_FD)
  1045. swim3_mb_event(mdev, MB_FD);
  1046. if (request_irq(fs->swim3_intr, swim3_interrupt, 0, "SWIM3", fs)) {
  1047. swim3_err("%s", "Couldn't request interrupt\n");
  1048. pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 0);
  1049. goto out_unmap;
  1050. return -EBUSY;
  1051. }
  1052. init_timer(&fs->timeout);
  1053. swim3_info("SWIM3 floppy controller %s\n",
  1054. mdev->media_bay ? "in media bay" : "");
  1055. return 0;
  1056. out_unmap:
  1057. iounmap(fs->dma);
  1058. iounmap(fs->swim3);
  1059. out_release:
  1060. macio_release_resource(mdev, 0);
  1061. macio_release_resource(mdev, 1);
  1062. return rc;
  1063. }
  1064. static int __devinit swim3_attach(struct macio_dev *mdev, const struct of_device_id *match)
  1065. {
  1066. struct gendisk *disk;
  1067. int index, rc;
  1068. index = floppy_count++;
  1069. if (index >= MAX_FLOPPIES)
  1070. return -ENXIO;
  1071. /* Add the drive */
  1072. rc = swim3_add_device(mdev, index);
  1073. if (rc)
  1074. return rc;
  1075. /* Now register that disk. Same comment about failure handling */
  1076. disk = disks[index] = alloc_disk(1);
  1077. if (disk == NULL)
  1078. return -ENOMEM;
  1079. disk->queue = blk_init_queue(do_fd_request, &swim3_lock);
  1080. if (disk->queue == NULL) {
  1081. put_disk(disk);
  1082. return -ENOMEM;
  1083. }
  1084. disk->queue->queuedata = &floppy_states[index];
  1085. if (index == 0) {
  1086. /* If we failed, there isn't much we can do as the driver is still
  1087. * too dumb to remove the device, just bail out
  1088. */
  1089. if (register_blkdev(FLOPPY_MAJOR, "fd"))
  1090. return 0;
  1091. }
  1092. disk->major = FLOPPY_MAJOR;
  1093. disk->first_minor = index;
  1094. disk->fops = &floppy_fops;
  1095. disk->private_data = &floppy_states[index];
  1096. disk->flags |= GENHD_FL_REMOVABLE;
  1097. sprintf(disk->disk_name, "fd%d", index);
  1098. set_capacity(disk, 2880);
  1099. add_disk(disk);
  1100. return 0;
  1101. }
  1102. static struct of_device_id swim3_match[] =
  1103. {
  1104. {
  1105. .name = "swim3",
  1106. },
  1107. {
  1108. .compatible = "ohare-swim3"
  1109. },
  1110. {
  1111. .compatible = "swim3"
  1112. },
  1113. { /* end of list */ }
  1114. };
  1115. static struct macio_driver swim3_driver =
  1116. {
  1117. .driver = {
  1118. .name = "swim3",
  1119. .of_match_table = swim3_match,
  1120. },
  1121. .probe = swim3_attach,
  1122. #ifdef CONFIG_PMAC_MEDIABAY
  1123. .mediabay_event = swim3_mb_event,
  1124. #endif
  1125. #if 0
  1126. .suspend = swim3_suspend,
  1127. .resume = swim3_resume,
  1128. #endif
  1129. };
  1130. int swim3_init(void)
  1131. {
  1132. macio_register_driver(&swim3_driver);
  1133. return 0;
  1134. }
  1135. module_init(swim3_init)
  1136. MODULE_LICENSE("GPL");
  1137. MODULE_AUTHOR("Paul Mackerras");
  1138. MODULE_ALIAS_BLOCKDEV_MAJOR(FLOPPY_MAJOR);