p5020si-pre.dtsi 2.8 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697
  1. /*
  2. * P5020/P5010 Silicon/SoC Device Tree Source (pre include)
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. /dts-v1/;
  35. / {
  36. compatible = "fsl,P5020";
  37. #address-cells = <2>;
  38. #size-cells = <2>;
  39. interrupt-parent = <&mpic>;
  40. aliases {
  41. ccsr = &soc;
  42. dcsr = &dcsr;
  43. serial0 = &serial0;
  44. serial1 = &serial1;
  45. serial2 = &serial2;
  46. serial3 = &serial3;
  47. pci0 = &pci0;
  48. pci1 = &pci1;
  49. pci2 = &pci2;
  50. pci3 = &pci3;
  51. usb0 = &usb0;
  52. usb1 = &usb1;
  53. dma0 = &dma0;
  54. dma1 = &dma1;
  55. sdhc = &sdhc;
  56. msi0 = &msi0;
  57. msi1 = &msi1;
  58. msi2 = &msi2;
  59. crypto = &crypto;
  60. sec_jr0 = &sec_jr0;
  61. sec_jr1 = &sec_jr1;
  62. sec_jr2 = &sec_jr2;
  63. sec_jr3 = &sec_jr3;
  64. rtic_a = &rtic_a;
  65. rtic_b = &rtic_b;
  66. rtic_c = &rtic_c;
  67. rtic_d = &rtic_d;
  68. sec_mon = &sec_mon;
  69. };
  70. cpus {
  71. #address-cells = <1>;
  72. #size-cells = <0>;
  73. cpu0: PowerPC,e5500@0 {
  74. device_type = "cpu";
  75. reg = <0>;
  76. next-level-cache = <&L2_0>;
  77. L2_0: l2-cache {
  78. next-level-cache = <&cpc>;
  79. };
  80. };
  81. cpu1: PowerPC,e5500@1 {
  82. device_type = "cpu";
  83. reg = <1>;
  84. next-level-cache = <&L2_1>;
  85. L2_1: l2-cache {
  86. next-level-cache = <&cpc>;
  87. };
  88. };
  89. };
  90. };