omap-dmic.c 12 KB

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  1. /*
  2. * omap-dmic.c -- OMAP ASoC DMIC DAI driver
  3. *
  4. * Copyright (C) 2010 - 2011 Texas Instruments
  5. *
  6. * Author: David Lambert <dlambert@ti.com>
  7. * Misael Lopez Cruz <misael.lopez@ti.com>
  8. * Liam Girdwood <lrg@ti.com>
  9. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * version 2 as published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23. * 02110-1301 USA
  24. *
  25. */
  26. #include <linux/init.h>
  27. #include <linux/module.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/err.h>
  30. #include <linux/clk.h>
  31. #include <linux/io.h>
  32. #include <linux/slab.h>
  33. #include <linux/pm_runtime.h>
  34. #include <plat/dma.h>
  35. #include <sound/core.h>
  36. #include <sound/pcm.h>
  37. #include <sound/pcm_params.h>
  38. #include <sound/initval.h>
  39. #include <sound/soc.h>
  40. #include "omap-pcm.h"
  41. #include "omap-dmic.h"
  42. struct omap_dmic {
  43. struct device *dev;
  44. void __iomem *io_base;
  45. struct clk *fclk;
  46. int fclk_freq;
  47. int out_freq;
  48. int clk_div;
  49. int sysclk;
  50. int threshold;
  51. u32 ch_enabled;
  52. bool active;
  53. struct mutex mutex;
  54. };
  55. /*
  56. * Stream DMA parameters
  57. */
  58. static struct omap_pcm_dma_data omap_dmic_dai_dma_params = {
  59. .name = "DMIC capture",
  60. .data_type = OMAP_DMA_DATA_TYPE_S32,
  61. .sync_mode = OMAP_DMA_SYNC_PACKET,
  62. };
  63. static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
  64. {
  65. __raw_writel(val, dmic->io_base + reg);
  66. }
  67. static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
  68. {
  69. return __raw_readl(dmic->io_base + reg);
  70. }
  71. static inline void omap_dmic_start(struct omap_dmic *dmic)
  72. {
  73. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  74. /* Configure DMA controller */
  75. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
  76. OMAP_DMIC_DMA_ENABLE);
  77. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled);
  78. }
  79. static inline void omap_dmic_stop(struct omap_dmic *dmic)
  80. {
  81. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  82. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  83. ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);
  84. /* Disable DMA request generation */
  85. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
  86. OMAP_DMIC_DMA_ENABLE);
  87. }
  88. static inline int dmic_is_enabled(struct omap_dmic *dmic)
  89. {
  90. return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
  91. OMAP_DMIC_UP_ENABLE_MASK;
  92. }
  93. static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
  94. struct snd_soc_dai *dai)
  95. {
  96. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  97. int ret = 0;
  98. mutex_lock(&dmic->mutex);
  99. if (!dai->active)
  100. dmic->active = 1;
  101. else
  102. ret = -EBUSY;
  103. mutex_unlock(&dmic->mutex);
  104. return ret;
  105. }
  106. static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
  107. struct snd_soc_dai *dai)
  108. {
  109. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  110. mutex_lock(&dmic->mutex);
  111. if (!dai->active)
  112. dmic->active = 0;
  113. mutex_unlock(&dmic->mutex);
  114. }
  115. static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
  116. {
  117. int divider = -EINVAL;
  118. /*
  119. * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
  120. * configuration.
  121. */
  122. if (sample_rate == 192000) {
  123. if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
  124. divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
  125. else
  126. dev_err(dmic->dev,
  127. "invalid clock configuration for 192KHz\n");
  128. return divider;
  129. }
  130. switch (dmic->out_freq) {
  131. case 1536000:
  132. if (dmic->fclk_freq != 24576000)
  133. goto div_err;
  134. divider = 0x4; /* Divider: 16 */
  135. break;
  136. case 2400000:
  137. switch (dmic->fclk_freq) {
  138. case 12000000:
  139. divider = 0x5; /* Divider: 5 */
  140. break;
  141. case 19200000:
  142. divider = 0x0; /* Divider: 8 */
  143. break;
  144. case 24000000:
  145. divider = 0x2; /* Divider: 10 */
  146. break;
  147. default:
  148. goto div_err;
  149. }
  150. break;
  151. case 3072000:
  152. if (dmic->fclk_freq != 24576000)
  153. goto div_err;
  154. divider = 0x3; /* Divider: 8 */
  155. break;
  156. case 3840000:
  157. if (dmic->fclk_freq != 19200000)
  158. goto div_err;
  159. divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
  160. break;
  161. default:
  162. dev_err(dmic->dev, "invalid out frequency: %dHz\n",
  163. dmic->out_freq);
  164. break;
  165. }
  166. return divider;
  167. div_err:
  168. dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
  169. dmic->out_freq, dmic->fclk_freq);
  170. return -EINVAL;
  171. }
  172. static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
  173. struct snd_pcm_hw_params *params,
  174. struct snd_soc_dai *dai)
  175. {
  176. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  177. int channels;
  178. dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
  179. if (dmic->clk_div < 0) {
  180. dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
  181. dmic->out_freq, dmic->fclk_freq);
  182. return -EINVAL;
  183. }
  184. dmic->ch_enabled = 0;
  185. channels = params_channels(params);
  186. switch (channels) {
  187. case 6:
  188. dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE;
  189. case 4:
  190. dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE;
  191. case 2:
  192. dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE;
  193. break;
  194. default:
  195. dev_err(dmic->dev, "invalid number of legacy channels\n");
  196. return -EINVAL;
  197. }
  198. /* packet size is threshold * channels */
  199. omap_dmic_dai_dma_params.packet_size = dmic->threshold * channels;
  200. snd_soc_dai_set_dma_data(dai, substream, &omap_dmic_dai_dma_params);
  201. return 0;
  202. }
  203. static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
  204. struct snd_soc_dai *dai)
  205. {
  206. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  207. u32 ctrl;
  208. /* Configure uplink threshold */
  209. omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);
  210. ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  211. /* Set dmic out format */
  212. ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK);
  213. ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  214. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  215. /* Configure dmic clock divider */
  216. ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
  217. ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div);
  218. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);
  219. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  220. ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  221. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  222. return 0;
  223. }
  224. static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
  225. int cmd, struct snd_soc_dai *dai)
  226. {
  227. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  228. switch (cmd) {
  229. case SNDRV_PCM_TRIGGER_START:
  230. omap_dmic_start(dmic);
  231. break;
  232. case SNDRV_PCM_TRIGGER_STOP:
  233. omap_dmic_stop(dmic);
  234. break;
  235. default:
  236. break;
  237. }
  238. return 0;
  239. }
  240. static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
  241. unsigned int freq)
  242. {
  243. struct clk *parent_clk;
  244. char *parent_clk_name;
  245. int ret = 0;
  246. switch (freq) {
  247. case 12000000:
  248. case 19200000:
  249. case 24000000:
  250. case 24576000:
  251. break;
  252. default:
  253. dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
  254. dmic->fclk_freq = 0;
  255. return -EINVAL;
  256. }
  257. if (dmic->sysclk == clk_id) {
  258. dmic->fclk_freq = freq;
  259. return 0;
  260. }
  261. /* re-parent not allowed if a stream is ongoing */
  262. if (dmic->active && dmic_is_enabled(dmic)) {
  263. dev_err(dmic->dev, "can't re-parent when DMIC active\n");
  264. return -EBUSY;
  265. }
  266. switch (clk_id) {
  267. case OMAP_DMIC_SYSCLK_PAD_CLKS:
  268. parent_clk_name = "pad_clks_ck";
  269. break;
  270. case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
  271. parent_clk_name = "slimbus_clk";
  272. break;
  273. case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
  274. parent_clk_name = "dmic_sync_mux_ck";
  275. break;
  276. default:
  277. dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
  278. return -EINVAL;
  279. }
  280. parent_clk = clk_get(dmic->dev, parent_clk_name);
  281. if (IS_ERR(parent_clk)) {
  282. dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
  283. return -ENODEV;
  284. }
  285. mutex_lock(&dmic->mutex);
  286. if (dmic->active) {
  287. /* disable clock while reparenting */
  288. pm_runtime_put_sync(dmic->dev);
  289. ret = clk_set_parent(dmic->fclk, parent_clk);
  290. pm_runtime_get_sync(dmic->dev);
  291. } else {
  292. ret = clk_set_parent(dmic->fclk, parent_clk);
  293. }
  294. mutex_unlock(&dmic->mutex);
  295. if (ret < 0) {
  296. dev_err(dmic->dev, "re-parent failed\n");
  297. goto err_busy;
  298. }
  299. dmic->sysclk = clk_id;
  300. dmic->fclk_freq = freq;
  301. err_busy:
  302. clk_put(parent_clk);
  303. return ret;
  304. }
  305. static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
  306. unsigned int freq)
  307. {
  308. int ret = 0;
  309. if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
  310. dev_err(dmic->dev, "output clk_id (%d) not supported\n",
  311. clk_id);
  312. return -EINVAL;
  313. }
  314. switch (freq) {
  315. case 1536000:
  316. case 2400000:
  317. case 3072000:
  318. case 3840000:
  319. dmic->out_freq = freq;
  320. break;
  321. default:
  322. dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
  323. dmic->out_freq = 0;
  324. ret = -EINVAL;
  325. }
  326. return ret;
  327. }
  328. static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  329. unsigned int freq, int dir)
  330. {
  331. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  332. if (dir == SND_SOC_CLOCK_IN)
  333. return omap_dmic_select_fclk(dmic, clk_id, freq);
  334. else if (dir == SND_SOC_CLOCK_OUT)
  335. return omap_dmic_select_outclk(dmic, clk_id, freq);
  336. dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
  337. return -EINVAL;
  338. }
  339. static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
  340. .startup = omap_dmic_dai_startup,
  341. .shutdown = omap_dmic_dai_shutdown,
  342. .hw_params = omap_dmic_dai_hw_params,
  343. .prepare = omap_dmic_dai_prepare,
  344. .trigger = omap_dmic_dai_trigger,
  345. .set_sysclk = omap_dmic_set_dai_sysclk,
  346. };
  347. static int omap_dmic_probe(struct snd_soc_dai *dai)
  348. {
  349. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  350. pm_runtime_enable(dmic->dev);
  351. /* Disable lines while request is ongoing */
  352. pm_runtime_get_sync(dmic->dev);
  353. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
  354. pm_runtime_put_sync(dmic->dev);
  355. /* Configure DMIC threshold value */
  356. dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
  357. return 0;
  358. }
  359. static int omap_dmic_remove(struct snd_soc_dai *dai)
  360. {
  361. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  362. pm_runtime_disable(dmic->dev);
  363. return 0;
  364. }
  365. static struct snd_soc_dai_driver omap_dmic_dai = {
  366. .name = "omap-dmic",
  367. .probe = omap_dmic_probe,
  368. .remove = omap_dmic_remove,
  369. .capture = {
  370. .channels_min = 2,
  371. .channels_max = 6,
  372. .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
  373. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  374. .sig_bits = 24,
  375. },
  376. .ops = &omap_dmic_dai_ops,
  377. };
  378. static __devinit int asoc_dmic_probe(struct platform_device *pdev)
  379. {
  380. struct omap_dmic *dmic;
  381. struct resource *res;
  382. int ret;
  383. dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
  384. if (!dmic)
  385. return -ENOMEM;
  386. platform_set_drvdata(pdev, dmic);
  387. dmic->dev = &pdev->dev;
  388. dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;
  389. mutex_init(&dmic->mutex);
  390. dmic->fclk = clk_get(dmic->dev, "dmic_fck");
  391. if (IS_ERR(dmic->fclk)) {
  392. dev_err(dmic->dev, "cant get dmic_fck\n");
  393. return -ENODEV;
  394. }
  395. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  396. if (!res) {
  397. dev_err(dmic->dev, "invalid dma memory resource\n");
  398. ret = -ENODEV;
  399. goto err_put_clk;
  400. }
  401. omap_dmic_dai_dma_params.port_addr = res->start + OMAP_DMIC_DATA_REG;
  402. res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  403. if (!res) {
  404. dev_err(dmic->dev, "invalid dma resource\n");
  405. ret = -ENODEV;
  406. goto err_put_clk;
  407. }
  408. omap_dmic_dai_dma_params.dma_req = res->start;
  409. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  410. if (!res) {
  411. dev_err(dmic->dev, "invalid memory resource\n");
  412. ret = -ENODEV;
  413. goto err_put_clk;
  414. }
  415. if (!devm_request_mem_region(&pdev->dev, res->start,
  416. resource_size(res), pdev->name)) {
  417. dev_err(dmic->dev, "memory region already claimed\n");
  418. ret = -ENODEV;
  419. goto err_put_clk;
  420. }
  421. dmic->io_base = devm_ioremap(&pdev->dev, res->start,
  422. resource_size(res));
  423. if (!dmic->io_base) {
  424. ret = -ENOMEM;
  425. goto err_put_clk;
  426. }
  427. ret = snd_soc_register_dai(&pdev->dev, &omap_dmic_dai);
  428. if (ret)
  429. goto err_put_clk;
  430. return 0;
  431. err_put_clk:
  432. clk_put(dmic->fclk);
  433. return ret;
  434. }
  435. static int __devexit asoc_dmic_remove(struct platform_device *pdev)
  436. {
  437. struct omap_dmic *dmic = platform_get_drvdata(pdev);
  438. snd_soc_unregister_dai(&pdev->dev);
  439. clk_put(dmic->fclk);
  440. return 0;
  441. }
  442. static struct platform_driver asoc_dmic_driver = {
  443. .driver = {
  444. .name = "omap-dmic",
  445. .owner = THIS_MODULE,
  446. },
  447. .probe = asoc_dmic_probe,
  448. .remove = __devexit_p(asoc_dmic_remove),
  449. };
  450. module_platform_driver(asoc_dmic_driver);
  451. MODULE_ALIAS("platform:omap-dmic");
  452. MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
  453. MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
  454. MODULE_LICENSE("GPL");