qla_isr.c 68 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/delay.h>
  9. #include <linux/slab.h>
  10. #include <scsi/scsi_tcq.h>
  11. #include <scsi/scsi_bsg_fc.h>
  12. #include <scsi/scsi_eh.h>
  13. static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
  14. static void qla2x00_process_completed_request(struct scsi_qla_host *,
  15. struct req_que *, uint32_t);
  16. static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
  17. static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
  18. static void qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
  19. sts_entry_t *);
  20. /**
  21. * qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
  22. * @irq:
  23. * @dev_id: SCSI driver HA context
  24. *
  25. * Called by system whenever the host adapter generates an interrupt.
  26. *
  27. * Returns handled flag.
  28. */
  29. irqreturn_t
  30. qla2100_intr_handler(int irq, void *dev_id)
  31. {
  32. scsi_qla_host_t *vha;
  33. struct qla_hw_data *ha;
  34. struct device_reg_2xxx __iomem *reg;
  35. int status;
  36. unsigned long iter;
  37. uint16_t hccr;
  38. uint16_t mb[4];
  39. struct rsp_que *rsp;
  40. unsigned long flags;
  41. rsp = (struct rsp_que *) dev_id;
  42. if (!rsp) {
  43. ql_log(ql_log_info, NULL, 0x505d,
  44. "%s: NULL response queue pointer.\n", __func__);
  45. return (IRQ_NONE);
  46. }
  47. ha = rsp->hw;
  48. reg = &ha->iobase->isp;
  49. status = 0;
  50. spin_lock_irqsave(&ha->hardware_lock, flags);
  51. vha = pci_get_drvdata(ha->pdev);
  52. for (iter = 50; iter--; ) {
  53. hccr = RD_REG_WORD(&reg->hccr);
  54. if (hccr & HCCR_RISC_PAUSE) {
  55. if (pci_channel_offline(ha->pdev))
  56. break;
  57. /*
  58. * Issue a "HARD" reset in order for the RISC interrupt
  59. * bit to be cleared. Schedule a big hammer to get
  60. * out of the RISC PAUSED state.
  61. */
  62. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  63. RD_REG_WORD(&reg->hccr);
  64. ha->isp_ops->fw_dump(vha, 1);
  65. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  66. break;
  67. } else if ((RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) == 0)
  68. break;
  69. if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
  70. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  71. RD_REG_WORD(&reg->hccr);
  72. /* Get mailbox data. */
  73. mb[0] = RD_MAILBOX_REG(ha, reg, 0);
  74. if (mb[0] > 0x3fff && mb[0] < 0x8000) {
  75. qla2x00_mbx_completion(vha, mb[0]);
  76. status |= MBX_INTERRUPT;
  77. } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
  78. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  79. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  80. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  81. qla2x00_async_event(vha, rsp, mb);
  82. } else {
  83. /*EMPTY*/
  84. ql_dbg(ql_dbg_async, vha, 0x5025,
  85. "Unrecognized interrupt type (%d).\n",
  86. mb[0]);
  87. }
  88. /* Release mailbox registers. */
  89. WRT_REG_WORD(&reg->semaphore, 0);
  90. RD_REG_WORD(&reg->semaphore);
  91. } else {
  92. qla2x00_process_response_queue(rsp);
  93. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  94. RD_REG_WORD(&reg->hccr);
  95. }
  96. }
  97. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  98. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  99. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  100. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  101. complete(&ha->mbx_intr_comp);
  102. }
  103. return (IRQ_HANDLED);
  104. }
  105. /**
  106. * qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
  107. * @irq:
  108. * @dev_id: SCSI driver HA context
  109. *
  110. * Called by system whenever the host adapter generates an interrupt.
  111. *
  112. * Returns handled flag.
  113. */
  114. irqreturn_t
  115. qla2300_intr_handler(int irq, void *dev_id)
  116. {
  117. scsi_qla_host_t *vha;
  118. struct device_reg_2xxx __iomem *reg;
  119. int status;
  120. unsigned long iter;
  121. uint32_t stat;
  122. uint16_t hccr;
  123. uint16_t mb[4];
  124. struct rsp_que *rsp;
  125. struct qla_hw_data *ha;
  126. unsigned long flags;
  127. rsp = (struct rsp_que *) dev_id;
  128. if (!rsp) {
  129. ql_log(ql_log_info, NULL, 0x5058,
  130. "%s: NULL response queue pointer.\n", __func__);
  131. return (IRQ_NONE);
  132. }
  133. ha = rsp->hw;
  134. reg = &ha->iobase->isp;
  135. status = 0;
  136. spin_lock_irqsave(&ha->hardware_lock, flags);
  137. vha = pci_get_drvdata(ha->pdev);
  138. for (iter = 50; iter--; ) {
  139. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  140. if (stat & HSR_RISC_PAUSED) {
  141. if (unlikely(pci_channel_offline(ha->pdev)))
  142. break;
  143. hccr = RD_REG_WORD(&reg->hccr);
  144. if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
  145. ql_log(ql_log_warn, vha, 0x5026,
  146. "Parity error -- HCCR=%x, Dumping "
  147. "firmware.\n", hccr);
  148. else
  149. ql_log(ql_log_warn, vha, 0x5027,
  150. "RISC paused -- HCCR=%x, Dumping "
  151. "firmware.\n", hccr);
  152. /*
  153. * Issue a "HARD" reset in order for the RISC
  154. * interrupt bit to be cleared. Schedule a big
  155. * hammer to get out of the RISC PAUSED state.
  156. */
  157. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  158. RD_REG_WORD(&reg->hccr);
  159. ha->isp_ops->fw_dump(vha, 1);
  160. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  161. break;
  162. } else if ((stat & HSR_RISC_INT) == 0)
  163. break;
  164. switch (stat & 0xff) {
  165. case 0x1:
  166. case 0x2:
  167. case 0x10:
  168. case 0x11:
  169. qla2x00_mbx_completion(vha, MSW(stat));
  170. status |= MBX_INTERRUPT;
  171. /* Release mailbox registers. */
  172. WRT_REG_WORD(&reg->semaphore, 0);
  173. break;
  174. case 0x12:
  175. mb[0] = MSW(stat);
  176. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  177. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  178. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  179. qla2x00_async_event(vha, rsp, mb);
  180. break;
  181. case 0x13:
  182. qla2x00_process_response_queue(rsp);
  183. break;
  184. case 0x15:
  185. mb[0] = MBA_CMPLT_1_16BIT;
  186. mb[1] = MSW(stat);
  187. qla2x00_async_event(vha, rsp, mb);
  188. break;
  189. case 0x16:
  190. mb[0] = MBA_SCSI_COMPLETION;
  191. mb[1] = MSW(stat);
  192. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  193. qla2x00_async_event(vha, rsp, mb);
  194. break;
  195. default:
  196. ql_dbg(ql_dbg_async, vha, 0x5028,
  197. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  198. break;
  199. }
  200. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  201. RD_REG_WORD_RELAXED(&reg->hccr);
  202. }
  203. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  204. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  205. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  206. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  207. complete(&ha->mbx_intr_comp);
  208. }
  209. return (IRQ_HANDLED);
  210. }
  211. /**
  212. * qla2x00_mbx_completion() - Process mailbox command completions.
  213. * @ha: SCSI driver HA context
  214. * @mb0: Mailbox0 register
  215. */
  216. static void
  217. qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  218. {
  219. uint16_t cnt;
  220. uint32_t mboxes;
  221. uint16_t __iomem *wptr;
  222. struct qla_hw_data *ha = vha->hw;
  223. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  224. /* Read all mbox registers? */
  225. mboxes = (1 << ha->mbx_count) - 1;
  226. if (!ha->mcp)
  227. ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERRROR.\n");
  228. else
  229. mboxes = ha->mcp->in_mb;
  230. /* Load return mailbox registers. */
  231. ha->flags.mbox_int = 1;
  232. ha->mailbox_out[0] = mb0;
  233. mboxes >>= 1;
  234. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
  235. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  236. if (IS_QLA2200(ha) && cnt == 8)
  237. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
  238. if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
  239. ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
  240. else if (mboxes & BIT_0)
  241. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  242. wptr++;
  243. mboxes >>= 1;
  244. }
  245. }
  246. static void
  247. qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
  248. {
  249. static char *event[] =
  250. { "Complete", "Request Notification", "Time Extension" };
  251. int rval;
  252. struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
  253. uint16_t __iomem *wptr;
  254. uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
  255. /* Seed data -- mailbox1 -> mailbox7. */
  256. wptr = (uint16_t __iomem *)&reg24->mailbox1;
  257. for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
  258. mb[cnt] = RD_REG_WORD(wptr);
  259. ql_dbg(ql_dbg_async, vha, 0x5021,
  260. "Inter-Driver Communication %s -- "
  261. "%04x %04x %04x %04x %04x %04x %04x.\n",
  262. event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
  263. mb[4], mb[5], mb[6]);
  264. /* Acknowledgement needed? [Notify && non-zero timeout]. */
  265. timeout = (descr >> 8) & 0xf;
  266. if (aen != MBA_IDC_NOTIFY || !timeout)
  267. return;
  268. ql_dbg(ql_dbg_async, vha, 0x5022,
  269. "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
  270. vha->host_no, event[aen & 0xff], timeout);
  271. rval = qla2x00_post_idc_ack_work(vha, mb);
  272. if (rval != QLA_SUCCESS)
  273. ql_log(ql_log_warn, vha, 0x5023,
  274. "IDC failed to post ACK.\n");
  275. }
  276. /**
  277. * qla2x00_async_event() - Process aynchronous events.
  278. * @ha: SCSI driver HA context
  279. * @mb: Mailbox registers (0 - 3)
  280. */
  281. void
  282. qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
  283. {
  284. #define LS_UNKNOWN 2
  285. static char *link_speeds[] = { "1", "2", "?", "4", "8", "16", "10" };
  286. char *link_speed;
  287. uint16_t handle_cnt;
  288. uint16_t cnt, mbx;
  289. uint32_t handles[5];
  290. struct qla_hw_data *ha = vha->hw;
  291. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  292. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  293. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  294. uint32_t rscn_entry, host_pid;
  295. unsigned long flags;
  296. /* Setup to process RIO completion. */
  297. handle_cnt = 0;
  298. if (IS_CNA_CAPABLE(ha))
  299. goto skip_rio;
  300. switch (mb[0]) {
  301. case MBA_SCSI_COMPLETION:
  302. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  303. handle_cnt = 1;
  304. break;
  305. case MBA_CMPLT_1_16BIT:
  306. handles[0] = mb[1];
  307. handle_cnt = 1;
  308. mb[0] = MBA_SCSI_COMPLETION;
  309. break;
  310. case MBA_CMPLT_2_16BIT:
  311. handles[0] = mb[1];
  312. handles[1] = mb[2];
  313. handle_cnt = 2;
  314. mb[0] = MBA_SCSI_COMPLETION;
  315. break;
  316. case MBA_CMPLT_3_16BIT:
  317. handles[0] = mb[1];
  318. handles[1] = mb[2];
  319. handles[2] = mb[3];
  320. handle_cnt = 3;
  321. mb[0] = MBA_SCSI_COMPLETION;
  322. break;
  323. case MBA_CMPLT_4_16BIT:
  324. handles[0] = mb[1];
  325. handles[1] = mb[2];
  326. handles[2] = mb[3];
  327. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  328. handle_cnt = 4;
  329. mb[0] = MBA_SCSI_COMPLETION;
  330. break;
  331. case MBA_CMPLT_5_16BIT:
  332. handles[0] = mb[1];
  333. handles[1] = mb[2];
  334. handles[2] = mb[3];
  335. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  336. handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
  337. handle_cnt = 5;
  338. mb[0] = MBA_SCSI_COMPLETION;
  339. break;
  340. case MBA_CMPLT_2_32BIT:
  341. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  342. handles[1] = le32_to_cpu(
  343. ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
  344. RD_MAILBOX_REG(ha, reg, 6));
  345. handle_cnt = 2;
  346. mb[0] = MBA_SCSI_COMPLETION;
  347. break;
  348. default:
  349. break;
  350. }
  351. skip_rio:
  352. switch (mb[0]) {
  353. case MBA_SCSI_COMPLETION: /* Fast Post */
  354. if (!vha->flags.online)
  355. break;
  356. for (cnt = 0; cnt < handle_cnt; cnt++)
  357. qla2x00_process_completed_request(vha, rsp->req,
  358. handles[cnt]);
  359. break;
  360. case MBA_RESET: /* Reset */
  361. ql_dbg(ql_dbg_async, vha, 0x5002,
  362. "Asynchronous RESET.\n");
  363. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  364. break;
  365. case MBA_SYSTEM_ERR: /* System Error */
  366. mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha)) ?
  367. RD_REG_WORD(&reg24->mailbox7) : 0;
  368. ql_log(ql_log_warn, vha, 0x5003,
  369. "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
  370. "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
  371. ha->isp_ops->fw_dump(vha, 1);
  372. if (IS_FWI2_CAPABLE(ha)) {
  373. if (mb[1] == 0 && mb[2] == 0) {
  374. ql_log(ql_log_fatal, vha, 0x5004,
  375. "Unrecoverable Hardware Error: adapter "
  376. "marked OFFLINE!\n");
  377. vha->flags.online = 0;
  378. vha->device_flags |= DFLG_DEV_FAILED;
  379. } else {
  380. /* Check to see if MPI timeout occurred */
  381. if ((mbx & MBX_3) && (ha->flags.port0))
  382. set_bit(MPI_RESET_NEEDED,
  383. &vha->dpc_flags);
  384. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  385. }
  386. } else if (mb[1] == 0) {
  387. ql_log(ql_log_fatal, vha, 0x5005,
  388. "Unrecoverable Hardware Error: adapter marked "
  389. "OFFLINE!\n");
  390. vha->flags.online = 0;
  391. vha->device_flags |= DFLG_DEV_FAILED;
  392. } else
  393. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  394. break;
  395. case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */
  396. ql_log(ql_log_warn, vha, 0x5006,
  397. "ISP Request Transfer Error (%x).\n", mb[1]);
  398. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  399. break;
  400. case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */
  401. ql_log(ql_log_warn, vha, 0x5007,
  402. "ISP Response Transfer Error.\n");
  403. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  404. break;
  405. case MBA_WAKEUP_THRES: /* Request Queue Wake-up */
  406. ql_dbg(ql_dbg_async, vha, 0x5008,
  407. "Asynchronous WAKEUP_THRES.\n");
  408. break;
  409. case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */
  410. ql_dbg(ql_dbg_async, vha, 0x5009,
  411. "LIP occurred (%x).\n", mb[1]);
  412. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  413. atomic_set(&vha->loop_state, LOOP_DOWN);
  414. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  415. qla2x00_mark_all_devices_lost(vha, 1);
  416. }
  417. if (vha->vp_idx) {
  418. atomic_set(&vha->vp_state, VP_FAILED);
  419. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  420. }
  421. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  422. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  423. vha->flags.management_server_logged_in = 0;
  424. qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
  425. break;
  426. case MBA_LOOP_UP: /* Loop Up Event */
  427. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  428. link_speed = link_speeds[0];
  429. ha->link_data_rate = PORT_SPEED_1GB;
  430. } else {
  431. link_speed = link_speeds[LS_UNKNOWN];
  432. if (mb[1] < 6)
  433. link_speed = link_speeds[mb[1]];
  434. else if (mb[1] == 0x13)
  435. link_speed = link_speeds[6];
  436. ha->link_data_rate = mb[1];
  437. }
  438. ql_dbg(ql_dbg_async, vha, 0x500a,
  439. "LOOP UP detected (%s Gbps).\n", link_speed);
  440. vha->flags.management_server_logged_in = 0;
  441. qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
  442. break;
  443. case MBA_LOOP_DOWN: /* Loop Down Event */
  444. mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
  445. ? RD_REG_WORD(&reg24->mailbox4) : 0;
  446. mbx = IS_QLA82XX(ha) ? RD_REG_WORD(&reg82->mailbox_out[4]) : mbx;
  447. ql_dbg(ql_dbg_async, vha, 0x500b,
  448. "LOOP DOWN detected (%x %x %x %x).\n",
  449. mb[1], mb[2], mb[3], mbx);
  450. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  451. atomic_set(&vha->loop_state, LOOP_DOWN);
  452. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  453. vha->device_flags |= DFLG_NO_CABLE;
  454. qla2x00_mark_all_devices_lost(vha, 1);
  455. }
  456. if (vha->vp_idx) {
  457. atomic_set(&vha->vp_state, VP_FAILED);
  458. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  459. }
  460. vha->flags.management_server_logged_in = 0;
  461. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  462. qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
  463. break;
  464. case MBA_LIP_RESET: /* LIP reset occurred */
  465. ql_dbg(ql_dbg_async, vha, 0x500c,
  466. "LIP reset occurred (%x).\n", mb[1]);
  467. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  468. atomic_set(&vha->loop_state, LOOP_DOWN);
  469. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  470. qla2x00_mark_all_devices_lost(vha, 1);
  471. }
  472. if (vha->vp_idx) {
  473. atomic_set(&vha->vp_state, VP_FAILED);
  474. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  475. }
  476. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  477. ha->operating_mode = LOOP;
  478. vha->flags.management_server_logged_in = 0;
  479. qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
  480. break;
  481. /* case MBA_DCBX_COMPLETE: */
  482. case MBA_POINT_TO_POINT: /* Point-to-Point */
  483. if (IS_QLA2100(ha))
  484. break;
  485. if (IS_QLA81XX(ha) || IS_QLA82XX(ha) || IS_QLA8031(ha)) {
  486. ql_dbg(ql_dbg_async, vha, 0x500d,
  487. "DCBX Completed -- %04x %04x %04x.\n",
  488. mb[1], mb[2], mb[3]);
  489. if (ha->notify_dcbx_comp)
  490. complete(&ha->dcbx_comp);
  491. } else
  492. ql_dbg(ql_dbg_async, vha, 0x500e,
  493. "Asynchronous P2P MODE received.\n");
  494. /*
  495. * Until there's a transition from loop down to loop up, treat
  496. * this as loop down only.
  497. */
  498. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  499. atomic_set(&vha->loop_state, LOOP_DOWN);
  500. if (!atomic_read(&vha->loop_down_timer))
  501. atomic_set(&vha->loop_down_timer,
  502. LOOP_DOWN_TIME);
  503. qla2x00_mark_all_devices_lost(vha, 1);
  504. }
  505. if (vha->vp_idx) {
  506. atomic_set(&vha->vp_state, VP_FAILED);
  507. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  508. }
  509. if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
  510. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  511. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  512. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  513. ha->flags.gpsc_supported = 1;
  514. vha->flags.management_server_logged_in = 0;
  515. break;
  516. case MBA_CHG_IN_CONNECTION: /* Change in connection mode */
  517. if (IS_QLA2100(ha))
  518. break;
  519. ql_dbg(ql_dbg_async, vha, 0x500f,
  520. "Configuration change detected: value=%x.\n", mb[1]);
  521. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  522. atomic_set(&vha->loop_state, LOOP_DOWN);
  523. if (!atomic_read(&vha->loop_down_timer))
  524. atomic_set(&vha->loop_down_timer,
  525. LOOP_DOWN_TIME);
  526. qla2x00_mark_all_devices_lost(vha, 1);
  527. }
  528. if (vha->vp_idx) {
  529. atomic_set(&vha->vp_state, VP_FAILED);
  530. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  531. }
  532. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  533. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  534. break;
  535. case MBA_PORT_UPDATE: /* Port database update */
  536. /*
  537. * Handle only global and vn-port update events
  538. *
  539. * Relevant inputs:
  540. * mb[1] = N_Port handle of changed port
  541. * OR 0xffff for global event
  542. * mb[2] = New login state
  543. * 7 = Port logged out
  544. * mb[3] = LSB is vp_idx, 0xff = all vps
  545. *
  546. * Skip processing if:
  547. * Event is global, vp_idx is NOT all vps,
  548. * vp_idx does not match
  549. * Event is not global, vp_idx does not match
  550. */
  551. if (IS_QLA2XXX_MIDTYPE(ha) &&
  552. ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
  553. (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
  554. break;
  555. /* Global event -- port logout or port unavailable. */
  556. if (mb[1] == 0xffff && mb[2] == 0x7) {
  557. ql_dbg(ql_dbg_async, vha, 0x5010,
  558. "Port unavailable %04x %04x %04x.\n",
  559. mb[1], mb[2], mb[3]);
  560. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  561. atomic_set(&vha->loop_state, LOOP_DOWN);
  562. atomic_set(&vha->loop_down_timer,
  563. LOOP_DOWN_TIME);
  564. vha->device_flags |= DFLG_NO_CABLE;
  565. qla2x00_mark_all_devices_lost(vha, 1);
  566. }
  567. if (vha->vp_idx) {
  568. atomic_set(&vha->vp_state, VP_FAILED);
  569. fc_vport_set_state(vha->fc_vport,
  570. FC_VPORT_FAILED);
  571. qla2x00_mark_all_devices_lost(vha, 1);
  572. }
  573. vha->flags.management_server_logged_in = 0;
  574. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  575. break;
  576. }
  577. /*
  578. * If PORT UPDATE is global (received LIP_OCCURRED/LIP_RESET
  579. * event etc. earlier indicating loop is down) then process
  580. * it. Otherwise ignore it and Wait for RSCN to come in.
  581. */
  582. atomic_set(&vha->loop_down_timer, 0);
  583. if (atomic_read(&vha->loop_state) != LOOP_DOWN &&
  584. atomic_read(&vha->loop_state) != LOOP_DEAD) {
  585. ql_dbg(ql_dbg_async, vha, 0x5011,
  586. "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
  587. mb[1], mb[2], mb[3]);
  588. break;
  589. }
  590. ql_dbg(ql_dbg_async, vha, 0x5012,
  591. "Port database changed %04x %04x %04x.\n",
  592. mb[1], mb[2], mb[3]);
  593. /*
  594. * Mark all devices as missing so we will login again.
  595. */
  596. atomic_set(&vha->loop_state, LOOP_UP);
  597. qla2x00_mark_all_devices_lost(vha, 1);
  598. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  599. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  600. break;
  601. case MBA_RSCN_UPDATE: /* State Change Registration */
  602. /* Check if the Vport has issued a SCR */
  603. if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
  604. break;
  605. /* Only handle SCNs for our Vport index. */
  606. if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
  607. break;
  608. ql_dbg(ql_dbg_async, vha, 0x5013,
  609. "RSCN database changed -- %04x %04x %04x.\n",
  610. mb[1], mb[2], mb[3]);
  611. rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
  612. host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
  613. | vha->d_id.b.al_pa;
  614. if (rscn_entry == host_pid) {
  615. ql_dbg(ql_dbg_async, vha, 0x5014,
  616. "Ignoring RSCN update to local host "
  617. "port ID (%06x).\n", host_pid);
  618. break;
  619. }
  620. /* Ignore reserved bits from RSCN-payload. */
  621. rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
  622. atomic_set(&vha->loop_down_timer, 0);
  623. vha->flags.management_server_logged_in = 0;
  624. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  625. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  626. qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
  627. break;
  628. /* case MBA_RIO_RESPONSE: */
  629. case MBA_ZIO_RESPONSE:
  630. ql_dbg(ql_dbg_async, vha, 0x5015,
  631. "[R|Z]IO update completion.\n");
  632. if (IS_FWI2_CAPABLE(ha))
  633. qla24xx_process_response_queue(vha, rsp);
  634. else
  635. qla2x00_process_response_queue(rsp);
  636. break;
  637. case MBA_DISCARD_RND_FRAME:
  638. ql_dbg(ql_dbg_async, vha, 0x5016,
  639. "Discard RND Frame -- %04x %04x %04x.\n",
  640. mb[1], mb[2], mb[3]);
  641. break;
  642. case MBA_TRACE_NOTIFICATION:
  643. ql_dbg(ql_dbg_async, vha, 0x5017,
  644. "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
  645. break;
  646. case MBA_ISP84XX_ALERT:
  647. ql_dbg(ql_dbg_async, vha, 0x5018,
  648. "ISP84XX Alert Notification -- %04x %04x %04x.\n",
  649. mb[1], mb[2], mb[3]);
  650. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  651. switch (mb[1]) {
  652. case A84_PANIC_RECOVERY:
  653. ql_log(ql_log_info, vha, 0x5019,
  654. "Alert 84XX: panic recovery %04x %04x.\n",
  655. mb[2], mb[3]);
  656. break;
  657. case A84_OP_LOGIN_COMPLETE:
  658. ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
  659. ql_log(ql_log_info, vha, 0x501a,
  660. "Alert 84XX: firmware version %x.\n",
  661. ha->cs84xx->op_fw_version);
  662. break;
  663. case A84_DIAG_LOGIN_COMPLETE:
  664. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  665. ql_log(ql_log_info, vha, 0x501b,
  666. "Alert 84XX: diagnostic firmware version %x.\n",
  667. ha->cs84xx->diag_fw_version);
  668. break;
  669. case A84_GOLD_LOGIN_COMPLETE:
  670. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  671. ha->cs84xx->fw_update = 1;
  672. ql_log(ql_log_info, vha, 0x501c,
  673. "Alert 84XX: gold firmware version %x.\n",
  674. ha->cs84xx->gold_fw_version);
  675. break;
  676. default:
  677. ql_log(ql_log_warn, vha, 0x501d,
  678. "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
  679. mb[1], mb[2], mb[3]);
  680. }
  681. spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
  682. break;
  683. case MBA_DCBX_START:
  684. ql_dbg(ql_dbg_async, vha, 0x501e,
  685. "DCBX Started -- %04x %04x %04x.\n",
  686. mb[1], mb[2], mb[3]);
  687. break;
  688. case MBA_DCBX_PARAM_UPDATE:
  689. ql_dbg(ql_dbg_async, vha, 0x501f,
  690. "DCBX Parameters Updated -- %04x %04x %04x.\n",
  691. mb[1], mb[2], mb[3]);
  692. break;
  693. case MBA_FCF_CONF_ERR:
  694. ql_dbg(ql_dbg_async, vha, 0x5020,
  695. "FCF Configuration Error -- %04x %04x %04x.\n",
  696. mb[1], mb[2], mb[3]);
  697. break;
  698. case MBA_IDC_COMPLETE:
  699. case MBA_IDC_NOTIFY:
  700. case MBA_IDC_TIME_EXT:
  701. qla81xx_idc_event(vha, mb[0], mb[1]);
  702. break;
  703. default:
  704. ql_dbg(ql_dbg_async, vha, 0x5057,
  705. "Unknown AEN:%04x %04x %04x %04x\n",
  706. mb[0], mb[1], mb[2], mb[3]);
  707. }
  708. if (!vha->vp_idx && ha->num_vhosts)
  709. qla2x00_alert_all_vps(rsp, mb);
  710. }
  711. /**
  712. * qla2x00_process_completed_request() - Process a Fast Post response.
  713. * @ha: SCSI driver HA context
  714. * @index: SRB index
  715. */
  716. static void
  717. qla2x00_process_completed_request(struct scsi_qla_host *vha,
  718. struct req_que *req, uint32_t index)
  719. {
  720. srb_t *sp;
  721. struct qla_hw_data *ha = vha->hw;
  722. /* Validate handle. */
  723. if (index >= MAX_OUTSTANDING_COMMANDS) {
  724. ql_log(ql_log_warn, vha, 0x3014,
  725. "Invalid SCSI command index (%x).\n", index);
  726. if (IS_QLA82XX(ha))
  727. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  728. else
  729. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  730. return;
  731. }
  732. sp = req->outstanding_cmds[index];
  733. if (sp) {
  734. /* Free outstanding command slot. */
  735. req->outstanding_cmds[index] = NULL;
  736. /* Save ISP completion status */
  737. sp->done(ha, sp, DID_OK << 16);
  738. } else {
  739. ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
  740. if (IS_QLA82XX(ha))
  741. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  742. else
  743. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  744. }
  745. }
  746. static srb_t *
  747. qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
  748. struct req_que *req, void *iocb)
  749. {
  750. struct qla_hw_data *ha = vha->hw;
  751. sts_entry_t *pkt = iocb;
  752. srb_t *sp = NULL;
  753. uint16_t index;
  754. index = LSW(pkt->handle);
  755. if (index >= MAX_OUTSTANDING_COMMANDS) {
  756. ql_log(ql_log_warn, vha, 0x5031,
  757. "Invalid command index (%x).\n", index);
  758. if (IS_QLA82XX(ha))
  759. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  760. else
  761. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  762. goto done;
  763. }
  764. sp = req->outstanding_cmds[index];
  765. if (!sp) {
  766. ql_log(ql_log_warn, vha, 0x5032,
  767. "Invalid completion handle (%x) -- timed-out.\n", index);
  768. return sp;
  769. }
  770. if (sp->handle != index) {
  771. ql_log(ql_log_warn, vha, 0x5033,
  772. "SRB handle (%x) mismatch %x.\n", sp->handle, index);
  773. return NULL;
  774. }
  775. req->outstanding_cmds[index] = NULL;
  776. done:
  777. return sp;
  778. }
  779. static void
  780. qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  781. struct mbx_entry *mbx)
  782. {
  783. const char func[] = "MBX-IOCB";
  784. const char *type;
  785. fc_port_t *fcport;
  786. srb_t *sp;
  787. struct srb_iocb *lio;
  788. uint16_t *data;
  789. uint16_t status;
  790. sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
  791. if (!sp)
  792. return;
  793. lio = &sp->u.iocb_cmd;
  794. type = sp->name;
  795. fcport = sp->fcport;
  796. data = lio->u.logio.data;
  797. data[0] = MBS_COMMAND_ERROR;
  798. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  799. QLA_LOGIO_LOGIN_RETRIED : 0;
  800. if (mbx->entry_status) {
  801. ql_dbg(ql_dbg_async, vha, 0x5043,
  802. "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
  803. "entry-status=%x status=%x state-flag=%x "
  804. "status-flags=%x.\n", type, sp->handle,
  805. fcport->d_id.b.domain, fcport->d_id.b.area,
  806. fcport->d_id.b.al_pa, mbx->entry_status,
  807. le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
  808. le16_to_cpu(mbx->status_flags));
  809. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
  810. (uint8_t *)mbx, sizeof(*mbx));
  811. goto logio_done;
  812. }
  813. status = le16_to_cpu(mbx->status);
  814. if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
  815. le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
  816. status = 0;
  817. if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
  818. ql_dbg(ql_dbg_async, vha, 0x5045,
  819. "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
  820. type, sp->handle, fcport->d_id.b.domain,
  821. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  822. le16_to_cpu(mbx->mb1));
  823. data[0] = MBS_COMMAND_COMPLETE;
  824. if (sp->type == SRB_LOGIN_CMD) {
  825. fcport->port_type = FCT_TARGET;
  826. if (le16_to_cpu(mbx->mb1) & BIT_0)
  827. fcport->port_type = FCT_INITIATOR;
  828. else if (le16_to_cpu(mbx->mb1) & BIT_1)
  829. fcport->flags |= FCF_FCP2_DEVICE;
  830. }
  831. goto logio_done;
  832. }
  833. data[0] = le16_to_cpu(mbx->mb0);
  834. switch (data[0]) {
  835. case MBS_PORT_ID_USED:
  836. data[1] = le16_to_cpu(mbx->mb1);
  837. break;
  838. case MBS_LOOP_ID_USED:
  839. break;
  840. default:
  841. data[0] = MBS_COMMAND_ERROR;
  842. break;
  843. }
  844. ql_log(ql_log_warn, vha, 0x5046,
  845. "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
  846. "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
  847. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  848. status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
  849. le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
  850. le16_to_cpu(mbx->mb7));
  851. logio_done:
  852. sp->done(vha, sp, 0);
  853. }
  854. static void
  855. qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  856. sts_entry_t *pkt, int iocb_type)
  857. {
  858. const char func[] = "CT_IOCB";
  859. const char *type;
  860. srb_t *sp;
  861. struct fc_bsg_job *bsg_job;
  862. uint16_t comp_status;
  863. int res;
  864. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  865. if (!sp)
  866. return;
  867. bsg_job = sp->u.bsg_job;
  868. type = "ct pass-through";
  869. comp_status = le16_to_cpu(pkt->comp_status);
  870. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  871. * fc payload to the caller
  872. */
  873. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  874. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  875. if (comp_status != CS_COMPLETE) {
  876. if (comp_status == CS_DATA_UNDERRUN) {
  877. res = DID_OK << 16;
  878. bsg_job->reply->reply_payload_rcv_len =
  879. le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
  880. ql_log(ql_log_warn, vha, 0x5048,
  881. "CT pass-through-%s error "
  882. "comp_status-status=0x%x total_byte = 0x%x.\n",
  883. type, comp_status,
  884. bsg_job->reply->reply_payload_rcv_len);
  885. } else {
  886. ql_log(ql_log_warn, vha, 0x5049,
  887. "CT pass-through-%s error "
  888. "comp_status-status=0x%x.\n", type, comp_status);
  889. res = DID_ERROR << 16;
  890. bsg_job->reply->reply_payload_rcv_len = 0;
  891. }
  892. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
  893. (uint8_t *)pkt, sizeof(*pkt));
  894. } else {
  895. res = DID_OK << 16;
  896. bsg_job->reply->reply_payload_rcv_len =
  897. bsg_job->reply_payload.payload_len;
  898. bsg_job->reply_len = 0;
  899. }
  900. sp->done(vha, sp, res);
  901. }
  902. static void
  903. qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  904. struct sts_entry_24xx *pkt, int iocb_type)
  905. {
  906. const char func[] = "ELS_CT_IOCB";
  907. const char *type;
  908. srb_t *sp;
  909. struct fc_bsg_job *bsg_job;
  910. uint16_t comp_status;
  911. uint32_t fw_status[3];
  912. uint8_t* fw_sts_ptr;
  913. int res;
  914. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  915. if (!sp)
  916. return;
  917. bsg_job = sp->u.bsg_job;
  918. type = NULL;
  919. switch (sp->type) {
  920. case SRB_ELS_CMD_RPT:
  921. case SRB_ELS_CMD_HST:
  922. type = "els";
  923. break;
  924. case SRB_CT_CMD:
  925. type = "ct pass-through";
  926. break;
  927. default:
  928. ql_dbg(ql_dbg_user, vha, 0x503e,
  929. "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
  930. return;
  931. }
  932. comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
  933. fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
  934. fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
  935. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  936. * fc payload to the caller
  937. */
  938. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  939. bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
  940. if (comp_status != CS_COMPLETE) {
  941. if (comp_status == CS_DATA_UNDERRUN) {
  942. res = DID_OK << 16;
  943. bsg_job->reply->reply_payload_rcv_len =
  944. le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
  945. ql_dbg(ql_dbg_user, vha, 0x503f,
  946. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  947. "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
  948. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  949. le16_to_cpu(((struct els_sts_entry_24xx *)
  950. pkt)->total_byte_count));
  951. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  952. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  953. }
  954. else {
  955. ql_dbg(ql_dbg_user, vha, 0x5040,
  956. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  957. "error subcode 1=0x%x error subcode 2=0x%x.\n",
  958. type, sp->handle, comp_status,
  959. le16_to_cpu(((struct els_sts_entry_24xx *)
  960. pkt)->error_subcode_1),
  961. le16_to_cpu(((struct els_sts_entry_24xx *)
  962. pkt)->error_subcode_2));
  963. res = DID_ERROR << 16;
  964. bsg_job->reply->reply_payload_rcv_len = 0;
  965. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  966. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  967. }
  968. ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
  969. (uint8_t *)pkt, sizeof(*pkt));
  970. }
  971. else {
  972. res = DID_OK << 16;
  973. bsg_job->reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
  974. bsg_job->reply_len = 0;
  975. }
  976. sp->done(vha, sp, res);
  977. }
  978. static void
  979. qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
  980. struct logio_entry_24xx *logio)
  981. {
  982. const char func[] = "LOGIO-IOCB";
  983. const char *type;
  984. fc_port_t *fcport;
  985. srb_t *sp;
  986. struct srb_iocb *lio;
  987. uint16_t *data;
  988. uint32_t iop[2];
  989. sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
  990. if (!sp)
  991. return;
  992. lio = &sp->u.iocb_cmd;
  993. type = sp->name;
  994. fcport = sp->fcport;
  995. data = lio->u.logio.data;
  996. data[0] = MBS_COMMAND_ERROR;
  997. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  998. QLA_LOGIO_LOGIN_RETRIED : 0;
  999. if (logio->entry_status) {
  1000. ql_log(ql_log_warn, fcport->vha, 0x5034,
  1001. "Async-%s error entry - hdl=%x"
  1002. "portid=%02x%02x%02x entry-status=%x.\n",
  1003. type, sp->handle, fcport->d_id.b.domain,
  1004. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1005. logio->entry_status);
  1006. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
  1007. (uint8_t *)logio, sizeof(*logio));
  1008. goto logio_done;
  1009. }
  1010. if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
  1011. ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
  1012. "Async-%s complete - hdl=%x portid=%02x%02x%02x "
  1013. "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1014. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1015. le32_to_cpu(logio->io_parameter[0]));
  1016. data[0] = MBS_COMMAND_COMPLETE;
  1017. if (sp->type != SRB_LOGIN_CMD)
  1018. goto logio_done;
  1019. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1020. if (iop[0] & BIT_4) {
  1021. fcport->port_type = FCT_TARGET;
  1022. if (iop[0] & BIT_8)
  1023. fcport->flags |= FCF_FCP2_DEVICE;
  1024. } else if (iop[0] & BIT_5)
  1025. fcport->port_type = FCT_INITIATOR;
  1026. if (logio->io_parameter[7] || logio->io_parameter[8])
  1027. fcport->supported_classes |= FC_COS_CLASS2;
  1028. if (logio->io_parameter[9] || logio->io_parameter[10])
  1029. fcport->supported_classes |= FC_COS_CLASS3;
  1030. goto logio_done;
  1031. }
  1032. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1033. iop[1] = le32_to_cpu(logio->io_parameter[1]);
  1034. switch (iop[0]) {
  1035. case LSC_SCODE_PORTID_USED:
  1036. data[0] = MBS_PORT_ID_USED;
  1037. data[1] = LSW(iop[1]);
  1038. break;
  1039. case LSC_SCODE_NPORT_USED:
  1040. data[0] = MBS_LOOP_ID_USED;
  1041. break;
  1042. default:
  1043. data[0] = MBS_COMMAND_ERROR;
  1044. break;
  1045. }
  1046. ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
  1047. "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
  1048. "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1049. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1050. le16_to_cpu(logio->comp_status),
  1051. le32_to_cpu(logio->io_parameter[0]),
  1052. le32_to_cpu(logio->io_parameter[1]));
  1053. logio_done:
  1054. sp->done(vha, sp, 0);
  1055. }
  1056. static void
  1057. qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1058. struct tsk_mgmt_entry *tsk)
  1059. {
  1060. const char func[] = "TMF-IOCB";
  1061. const char *type;
  1062. fc_port_t *fcport;
  1063. srb_t *sp;
  1064. struct srb_iocb *iocb;
  1065. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1066. int error = 1;
  1067. sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
  1068. if (!sp)
  1069. return;
  1070. iocb = &sp->u.iocb_cmd;
  1071. type = sp->name;
  1072. fcport = sp->fcport;
  1073. if (sts->entry_status) {
  1074. ql_log(ql_log_warn, fcport->vha, 0x5038,
  1075. "Async-%s error - hdl=%x entry-status(%x).\n",
  1076. type, sp->handle, sts->entry_status);
  1077. } else if (sts->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1078. ql_log(ql_log_warn, fcport->vha, 0x5039,
  1079. "Async-%s error - hdl=%x completion status(%x).\n",
  1080. type, sp->handle, sts->comp_status);
  1081. } else if (!(le16_to_cpu(sts->scsi_status) &
  1082. SS_RESPONSE_INFO_LEN_VALID)) {
  1083. ql_log(ql_log_warn, fcport->vha, 0x503a,
  1084. "Async-%s error - hdl=%x no response info(%x).\n",
  1085. type, sp->handle, sts->scsi_status);
  1086. } else if (le32_to_cpu(sts->rsp_data_len) < 4) {
  1087. ql_log(ql_log_warn, fcport->vha, 0x503b,
  1088. "Async-%s error - hdl=%x not enough response(%d).\n",
  1089. type, sp->handle, sts->rsp_data_len);
  1090. } else if (sts->data[3]) {
  1091. ql_log(ql_log_warn, fcport->vha, 0x503c,
  1092. "Async-%s error - hdl=%x response(%x).\n",
  1093. type, sp->handle, sts->data[3]);
  1094. } else {
  1095. error = 0;
  1096. }
  1097. if (error) {
  1098. iocb->u.tmf.data = error;
  1099. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
  1100. (uint8_t *)sts, sizeof(*sts));
  1101. }
  1102. sp->done(vha, sp, 0);
  1103. }
  1104. /**
  1105. * qla2x00_process_response_queue() - Process response queue entries.
  1106. * @ha: SCSI driver HA context
  1107. */
  1108. void
  1109. qla2x00_process_response_queue(struct rsp_que *rsp)
  1110. {
  1111. struct scsi_qla_host *vha;
  1112. struct qla_hw_data *ha = rsp->hw;
  1113. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1114. sts_entry_t *pkt;
  1115. uint16_t handle_cnt;
  1116. uint16_t cnt;
  1117. vha = pci_get_drvdata(ha->pdev);
  1118. if (!vha->flags.online)
  1119. return;
  1120. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1121. pkt = (sts_entry_t *)rsp->ring_ptr;
  1122. rsp->ring_index++;
  1123. if (rsp->ring_index == rsp->length) {
  1124. rsp->ring_index = 0;
  1125. rsp->ring_ptr = rsp->ring;
  1126. } else {
  1127. rsp->ring_ptr++;
  1128. }
  1129. if (pkt->entry_status != 0) {
  1130. qla2x00_error_entry(vha, rsp, pkt);
  1131. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1132. wmb();
  1133. continue;
  1134. }
  1135. switch (pkt->entry_type) {
  1136. case STATUS_TYPE:
  1137. qla2x00_status_entry(vha, rsp, pkt);
  1138. break;
  1139. case STATUS_TYPE_21:
  1140. handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
  1141. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1142. qla2x00_process_completed_request(vha, rsp->req,
  1143. ((sts21_entry_t *)pkt)->handle[cnt]);
  1144. }
  1145. break;
  1146. case STATUS_TYPE_22:
  1147. handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
  1148. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1149. qla2x00_process_completed_request(vha, rsp->req,
  1150. ((sts22_entry_t *)pkt)->handle[cnt]);
  1151. }
  1152. break;
  1153. case STATUS_CONT_TYPE:
  1154. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1155. break;
  1156. case MBX_IOCB_TYPE:
  1157. qla2x00_mbx_iocb_entry(vha, rsp->req,
  1158. (struct mbx_entry *)pkt);
  1159. break;
  1160. case CT_IOCB_TYPE:
  1161. qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1162. break;
  1163. default:
  1164. /* Type Not Supported. */
  1165. ql_log(ql_log_warn, vha, 0x504a,
  1166. "Received unknown response pkt type %x "
  1167. "entry status=%x.\n",
  1168. pkt->entry_type, pkt->entry_status);
  1169. break;
  1170. }
  1171. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1172. wmb();
  1173. }
  1174. /* Adjust ring index */
  1175. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
  1176. }
  1177. static inline void
  1178. qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1179. uint32_t sense_len, struct rsp_que *rsp, int res)
  1180. {
  1181. struct scsi_qla_host *vha = sp->fcport->vha;
  1182. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1183. uint32_t track_sense_len;
  1184. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1185. sense_len = SCSI_SENSE_BUFFERSIZE;
  1186. SET_CMD_SENSE_LEN(sp, sense_len);
  1187. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1188. track_sense_len = sense_len;
  1189. if (sense_len > par_sense_len)
  1190. sense_len = par_sense_len;
  1191. memcpy(cp->sense_buffer, sense_data, sense_len);
  1192. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1193. track_sense_len -= sense_len;
  1194. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1195. if (track_sense_len != 0) {
  1196. rsp->status_srb = sp;
  1197. cp->result = res;
  1198. }
  1199. if (sense_len) {
  1200. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
  1201. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1202. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1203. cp);
  1204. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
  1205. cp->sense_buffer, sense_len);
  1206. }
  1207. }
  1208. struct scsi_dif_tuple {
  1209. __be16 guard; /* Checksum */
  1210. __be16 app_tag; /* APPL identifer */
  1211. __be32 ref_tag; /* Target LBA or indirect LBA */
  1212. };
  1213. /*
  1214. * Checks the guard or meta-data for the type of error
  1215. * detected by the HBA. In case of errors, we set the
  1216. * ASC/ASCQ fields in the sense buffer with ILLEGAL_REQUEST
  1217. * to indicate to the kernel that the HBA detected error.
  1218. */
  1219. static inline int
  1220. qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
  1221. {
  1222. struct scsi_qla_host *vha = sp->fcport->vha;
  1223. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  1224. uint8_t *ap = &sts24->data[12];
  1225. uint8_t *ep = &sts24->data[20];
  1226. uint32_t e_ref_tag, a_ref_tag;
  1227. uint16_t e_app_tag, a_app_tag;
  1228. uint16_t e_guard, a_guard;
  1229. /*
  1230. * swab32 of the "data" field in the beginning of qla2x00_status_entry()
  1231. * would make guard field appear at offset 2
  1232. */
  1233. a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
  1234. a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
  1235. a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
  1236. e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
  1237. e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
  1238. e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
  1239. ql_dbg(ql_dbg_io, vha, 0x3023,
  1240. "iocb(s) %p Returned STATUS.\n", sts24);
  1241. ql_dbg(ql_dbg_io, vha, 0x3024,
  1242. "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
  1243. " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
  1244. " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
  1245. cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
  1246. a_app_tag, e_app_tag, a_guard, e_guard);
  1247. /*
  1248. * Ignore sector if:
  1249. * For type 3: ref & app tag is all 'f's
  1250. * For type 0,1,2: app tag is all 'f's
  1251. */
  1252. if ((a_app_tag == 0xffff) &&
  1253. ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
  1254. (a_ref_tag == 0xffffffff))) {
  1255. uint32_t blocks_done, resid;
  1256. sector_t lba_s = scsi_get_lba(cmd);
  1257. /* 2TB boundary case covered automatically with this */
  1258. blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
  1259. resid = scsi_bufflen(cmd) - (blocks_done *
  1260. cmd->device->sector_size);
  1261. scsi_set_resid(cmd, resid);
  1262. cmd->result = DID_OK << 16;
  1263. /* Update protection tag */
  1264. if (scsi_prot_sg_count(cmd)) {
  1265. uint32_t i, j = 0, k = 0, num_ent;
  1266. struct scatterlist *sg;
  1267. struct sd_dif_tuple *spt;
  1268. /* Patch the corresponding protection tags */
  1269. scsi_for_each_prot_sg(cmd, sg,
  1270. scsi_prot_sg_count(cmd), i) {
  1271. num_ent = sg_dma_len(sg) / 8;
  1272. if (k + num_ent < blocks_done) {
  1273. k += num_ent;
  1274. continue;
  1275. }
  1276. j = blocks_done - k - 1;
  1277. k = blocks_done;
  1278. break;
  1279. }
  1280. if (k != blocks_done) {
  1281. ql_log(ql_log_warn, vha, 0x302f,
  1282. "unexpected tag values tag:lba=%x:%llx)\n",
  1283. e_ref_tag, (unsigned long long)lba_s);
  1284. return 1;
  1285. }
  1286. spt = page_address(sg_page(sg)) + sg->offset;
  1287. spt += j;
  1288. spt->app_tag = 0xffff;
  1289. if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
  1290. spt->ref_tag = 0xffffffff;
  1291. }
  1292. return 0;
  1293. }
  1294. /* check guard */
  1295. if (e_guard != a_guard) {
  1296. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1297. 0x10, 0x1);
  1298. set_driver_byte(cmd, DRIVER_SENSE);
  1299. set_host_byte(cmd, DID_ABORT);
  1300. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1301. return 1;
  1302. }
  1303. /* check ref tag */
  1304. if (e_ref_tag != a_ref_tag) {
  1305. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1306. 0x10, 0x3);
  1307. set_driver_byte(cmd, DRIVER_SENSE);
  1308. set_host_byte(cmd, DID_ABORT);
  1309. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1310. return 1;
  1311. }
  1312. /* check appl tag */
  1313. if (e_app_tag != a_app_tag) {
  1314. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1315. 0x10, 0x2);
  1316. set_driver_byte(cmd, DRIVER_SENSE);
  1317. set_host_byte(cmd, DID_ABORT);
  1318. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1319. return 1;
  1320. }
  1321. return 1;
  1322. }
  1323. /**
  1324. * qla2x00_status_entry() - Process a Status IOCB entry.
  1325. * @ha: SCSI driver HA context
  1326. * @pkt: Entry pointer
  1327. */
  1328. static void
  1329. qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1330. {
  1331. srb_t *sp;
  1332. fc_port_t *fcport;
  1333. struct scsi_cmnd *cp;
  1334. sts_entry_t *sts;
  1335. struct sts_entry_24xx *sts24;
  1336. uint16_t comp_status;
  1337. uint16_t scsi_status;
  1338. uint16_t ox_id;
  1339. uint8_t lscsi_status;
  1340. int32_t resid;
  1341. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1342. fw_resid_len;
  1343. uint8_t *rsp_info, *sense_data;
  1344. struct qla_hw_data *ha = vha->hw;
  1345. uint32_t handle;
  1346. uint16_t que;
  1347. struct req_que *req;
  1348. int logit = 1;
  1349. int res = 0;
  1350. sts = (sts_entry_t *) pkt;
  1351. sts24 = (struct sts_entry_24xx *) pkt;
  1352. if (IS_FWI2_CAPABLE(ha)) {
  1353. comp_status = le16_to_cpu(sts24->comp_status);
  1354. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1355. } else {
  1356. comp_status = le16_to_cpu(sts->comp_status);
  1357. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1358. }
  1359. handle = (uint32_t) LSW(sts->handle);
  1360. que = MSW(sts->handle);
  1361. req = ha->req_q_map[que];
  1362. /* Fast path completion. */
  1363. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1364. qla2x00_process_completed_request(vha, req, handle);
  1365. return;
  1366. }
  1367. /* Validate handle. */
  1368. if (handle < MAX_OUTSTANDING_COMMANDS) {
  1369. sp = req->outstanding_cmds[handle];
  1370. req->outstanding_cmds[handle] = NULL;
  1371. } else
  1372. sp = NULL;
  1373. if (sp == NULL) {
  1374. ql_dbg(ql_dbg_io, vha, 0x3017,
  1375. "Invalid status handle (0x%x).\n", sts->handle);
  1376. if (IS_QLA82XX(ha))
  1377. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1378. else
  1379. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1380. qla2xxx_wake_dpc(vha);
  1381. return;
  1382. }
  1383. cp = GET_CMD_SP(sp);
  1384. if (cp == NULL) {
  1385. ql_dbg(ql_dbg_io, vha, 0x3018,
  1386. "Command already returned (0x%x/%p).\n",
  1387. sts->handle, sp);
  1388. return;
  1389. }
  1390. lscsi_status = scsi_status & STATUS_MASK;
  1391. fcport = sp->fcport;
  1392. ox_id = 0;
  1393. sense_len = par_sense_len = rsp_info_len = resid_len =
  1394. fw_resid_len = 0;
  1395. if (IS_FWI2_CAPABLE(ha)) {
  1396. if (scsi_status & SS_SENSE_LEN_VALID)
  1397. sense_len = le32_to_cpu(sts24->sense_len);
  1398. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1399. rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
  1400. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  1401. resid_len = le32_to_cpu(sts24->rsp_residual_count);
  1402. if (comp_status == CS_DATA_UNDERRUN)
  1403. fw_resid_len = le32_to_cpu(sts24->residual_len);
  1404. rsp_info = sts24->data;
  1405. sense_data = sts24->data;
  1406. host_to_fcp_swap(sts24->data, sizeof(sts24->data));
  1407. ox_id = le16_to_cpu(sts24->ox_id);
  1408. par_sense_len = sizeof(sts24->data);
  1409. } else {
  1410. if (scsi_status & SS_SENSE_LEN_VALID)
  1411. sense_len = le16_to_cpu(sts->req_sense_length);
  1412. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1413. rsp_info_len = le16_to_cpu(sts->rsp_info_len);
  1414. resid_len = le32_to_cpu(sts->residual_length);
  1415. rsp_info = sts->rsp_info;
  1416. sense_data = sts->req_sense_data;
  1417. par_sense_len = sizeof(sts->req_sense_data);
  1418. }
  1419. /* Check for any FCP transport errors. */
  1420. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
  1421. /* Sense data lies beyond any FCP RESPONSE data. */
  1422. if (IS_FWI2_CAPABLE(ha)) {
  1423. sense_data += rsp_info_len;
  1424. par_sense_len -= rsp_info_len;
  1425. }
  1426. if (rsp_info_len > 3 && rsp_info[3]) {
  1427. ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
  1428. "FCP I/O protocol failure (0x%x/0x%x).\n",
  1429. rsp_info_len, rsp_info[3]);
  1430. res = DID_BUS_BUSY << 16;
  1431. goto out;
  1432. }
  1433. }
  1434. /* Check for overrun. */
  1435. if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
  1436. scsi_status & SS_RESIDUAL_OVER)
  1437. comp_status = CS_DATA_OVERRUN;
  1438. /*
  1439. * Based on Host and scsi status generate status code for Linux
  1440. */
  1441. switch (comp_status) {
  1442. case CS_COMPLETE:
  1443. case CS_QUEUE_FULL:
  1444. if (scsi_status == 0) {
  1445. res = DID_OK << 16;
  1446. break;
  1447. }
  1448. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  1449. resid = resid_len;
  1450. scsi_set_resid(cp, resid);
  1451. if (!lscsi_status &&
  1452. ((unsigned)(scsi_bufflen(cp) - resid) <
  1453. cp->underflow)) {
  1454. ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
  1455. "Mid-layer underflow "
  1456. "detected (0x%x of 0x%x bytes).\n",
  1457. resid, scsi_bufflen(cp));
  1458. res = DID_ERROR << 16;
  1459. break;
  1460. }
  1461. }
  1462. res = DID_OK << 16 | lscsi_status;
  1463. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1464. ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
  1465. "QUEUE FULL detected.\n");
  1466. break;
  1467. }
  1468. logit = 0;
  1469. if (lscsi_status != SS_CHECK_CONDITION)
  1470. break;
  1471. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1472. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1473. break;
  1474. qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  1475. rsp, res);
  1476. break;
  1477. case CS_DATA_UNDERRUN:
  1478. /* Use F/W calculated residual length. */
  1479. resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
  1480. scsi_set_resid(cp, resid);
  1481. if (scsi_status & SS_RESIDUAL_UNDER) {
  1482. if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
  1483. ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
  1484. "Dropped frame(s) detected "
  1485. "(0x%x of 0x%x bytes).\n",
  1486. resid, scsi_bufflen(cp));
  1487. res = DID_ERROR << 16 | lscsi_status;
  1488. goto check_scsi_status;
  1489. }
  1490. if (!lscsi_status &&
  1491. ((unsigned)(scsi_bufflen(cp) - resid) <
  1492. cp->underflow)) {
  1493. ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
  1494. "Mid-layer underflow "
  1495. "detected (0x%x of 0x%x bytes).\n",
  1496. resid, scsi_bufflen(cp));
  1497. res = DID_ERROR << 16;
  1498. break;
  1499. }
  1500. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  1501. lscsi_status != SAM_STAT_BUSY) {
  1502. /*
  1503. * scsi status of task set and busy are considered to be
  1504. * task not completed.
  1505. */
  1506. ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
  1507. "Dropped frame(s) detected (0x%x "
  1508. "of 0x%x bytes).\n", resid,
  1509. scsi_bufflen(cp));
  1510. res = DID_ERROR << 16 | lscsi_status;
  1511. goto check_scsi_status;
  1512. } else {
  1513. ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
  1514. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  1515. scsi_status, lscsi_status);
  1516. }
  1517. res = DID_OK << 16 | lscsi_status;
  1518. logit = 0;
  1519. check_scsi_status:
  1520. /*
  1521. * Check to see if SCSI Status is non zero. If so report SCSI
  1522. * Status.
  1523. */
  1524. if (lscsi_status != 0) {
  1525. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1526. ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
  1527. "QUEUE FULL detected.\n");
  1528. logit = 1;
  1529. break;
  1530. }
  1531. if (lscsi_status != SS_CHECK_CONDITION)
  1532. break;
  1533. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1534. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1535. break;
  1536. qla2x00_handle_sense(sp, sense_data, par_sense_len,
  1537. sense_len, rsp, res);
  1538. }
  1539. break;
  1540. case CS_PORT_LOGGED_OUT:
  1541. case CS_PORT_CONFIG_CHG:
  1542. case CS_PORT_BUSY:
  1543. case CS_INCOMPLETE:
  1544. case CS_PORT_UNAVAILABLE:
  1545. case CS_TIMEOUT:
  1546. case CS_RESET:
  1547. /*
  1548. * We are going to have the fc class block the rport
  1549. * while we try to recover so instruct the mid layer
  1550. * to requeue until the class decides how to handle this.
  1551. */
  1552. res = DID_TRANSPORT_DISRUPTED << 16;
  1553. if (comp_status == CS_TIMEOUT) {
  1554. if (IS_FWI2_CAPABLE(ha))
  1555. break;
  1556. else if ((le16_to_cpu(sts->status_flags) &
  1557. SF_LOGOUT_SENT) == 0)
  1558. break;
  1559. }
  1560. ql_dbg(ql_dbg_io, fcport->vha, 0x3021,
  1561. "Port down status: port-state=0x%x.\n",
  1562. atomic_read(&fcport->state));
  1563. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1564. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  1565. break;
  1566. case CS_ABORTED:
  1567. res = DID_RESET << 16;
  1568. break;
  1569. case CS_DIF_ERROR:
  1570. logit = qla2x00_handle_dif_error(sp, sts24);
  1571. break;
  1572. default:
  1573. res = DID_ERROR << 16;
  1574. break;
  1575. }
  1576. out:
  1577. if (logit)
  1578. ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
  1579. "FCP command status: 0x%x-0x%x (0x%x) "
  1580. "nexus=%ld:%d:%d portid=%02x%02x%02x oxid=0x%x "
  1581. "cdb=%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x len=0x%x "
  1582. "rsp_info=0x%x resid=0x%x fw_resid=0x%x.\n",
  1583. comp_status, scsi_status, res, vha->host_no,
  1584. cp->device->id, cp->device->lun, fcport->d_id.b.domain,
  1585. fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
  1586. cp->cmnd[0], cp->cmnd[1], cp->cmnd[2], cp->cmnd[3],
  1587. cp->cmnd[4], cp->cmnd[5], cp->cmnd[6], cp->cmnd[7],
  1588. cp->cmnd[8], cp->cmnd[9], scsi_bufflen(cp), rsp_info_len,
  1589. resid_len, fw_resid_len);
  1590. if (rsp->status_srb == NULL)
  1591. sp->done(ha, sp, res);
  1592. }
  1593. /**
  1594. * qla2x00_status_cont_entry() - Process a Status Continuations entry.
  1595. * @ha: SCSI driver HA context
  1596. * @pkt: Entry pointer
  1597. *
  1598. * Extended sense data.
  1599. */
  1600. static void
  1601. qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  1602. {
  1603. uint8_t sense_sz = 0;
  1604. struct qla_hw_data *ha = rsp->hw;
  1605. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  1606. srb_t *sp = rsp->status_srb;
  1607. struct scsi_cmnd *cp;
  1608. uint32_t sense_len;
  1609. uint8_t *sense_ptr;
  1610. if (!sp || !GET_CMD_SENSE_LEN(sp))
  1611. return;
  1612. sense_len = GET_CMD_SENSE_LEN(sp);
  1613. sense_ptr = GET_CMD_SENSE_PTR(sp);
  1614. cp = GET_CMD_SP(sp);
  1615. if (cp == NULL) {
  1616. ql_log(ql_log_warn, vha, 0x3025,
  1617. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  1618. rsp->status_srb = NULL;
  1619. return;
  1620. }
  1621. if (sense_len > sizeof(pkt->data))
  1622. sense_sz = sizeof(pkt->data);
  1623. else
  1624. sense_sz = sense_len;
  1625. /* Move sense data. */
  1626. if (IS_FWI2_CAPABLE(ha))
  1627. host_to_fcp_swap(pkt->data, sizeof(pkt->data));
  1628. memcpy(sense_ptr, pkt->data, sense_sz);
  1629. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
  1630. sense_ptr, sense_sz);
  1631. sense_len -= sense_sz;
  1632. sense_ptr += sense_sz;
  1633. SET_CMD_SENSE_PTR(sp, sense_ptr);
  1634. SET_CMD_SENSE_LEN(sp, sense_len);
  1635. /* Place command on done queue. */
  1636. if (sense_len == 0) {
  1637. rsp->status_srb = NULL;
  1638. sp->done(ha, sp, cp->result);
  1639. }
  1640. }
  1641. /**
  1642. * qla2x00_error_entry() - Process an error entry.
  1643. * @ha: SCSI driver HA context
  1644. * @pkt: Entry pointer
  1645. */
  1646. static void
  1647. qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
  1648. {
  1649. srb_t *sp;
  1650. struct qla_hw_data *ha = vha->hw;
  1651. const char func[] = "ERROR-IOCB";
  1652. uint16_t que = MSW(pkt->handle);
  1653. struct req_que *req = NULL;
  1654. int res = DID_ERROR << 16;
  1655. ql_dbg(ql_dbg_async, vha, 0x502a,
  1656. "type of error status in response: 0x%x\n", pkt->entry_status);
  1657. if (que >= ha->max_req_queues || !ha->req_q_map[que])
  1658. goto fatal;
  1659. req = ha->req_q_map[que];
  1660. if (pkt->entry_status & RF_BUSY)
  1661. res = DID_BUS_BUSY << 16;
  1662. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1663. if (sp) {
  1664. sp->done(ha, sp, res);
  1665. return;
  1666. }
  1667. fatal:
  1668. ql_log(ql_log_warn, vha, 0x5030,
  1669. "Error entry - invalid handle/queue.\n");
  1670. if (IS_QLA82XX(ha))
  1671. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1672. else
  1673. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1674. qla2xxx_wake_dpc(vha);
  1675. }
  1676. /**
  1677. * qla24xx_mbx_completion() - Process mailbox command completions.
  1678. * @ha: SCSI driver HA context
  1679. * @mb0: Mailbox0 register
  1680. */
  1681. static void
  1682. qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  1683. {
  1684. uint16_t cnt;
  1685. uint32_t mboxes;
  1686. uint16_t __iomem *wptr;
  1687. struct qla_hw_data *ha = vha->hw;
  1688. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1689. /* Read all mbox registers? */
  1690. mboxes = (1 << ha->mbx_count) - 1;
  1691. if (!ha->mcp)
  1692. ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERRROR.\n");
  1693. else
  1694. mboxes = ha->mcp->in_mb;
  1695. /* Load return mailbox registers. */
  1696. ha->flags.mbox_int = 1;
  1697. ha->mailbox_out[0] = mb0;
  1698. mboxes >>= 1;
  1699. wptr = (uint16_t __iomem *)&reg->mailbox1;
  1700. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  1701. if (mboxes & BIT_0)
  1702. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  1703. mboxes >>= 1;
  1704. wptr++;
  1705. }
  1706. }
  1707. /**
  1708. * qla24xx_process_response_queue() - Process response queue entries.
  1709. * @ha: SCSI driver HA context
  1710. */
  1711. void qla24xx_process_response_queue(struct scsi_qla_host *vha,
  1712. struct rsp_que *rsp)
  1713. {
  1714. struct sts_entry_24xx *pkt;
  1715. struct qla_hw_data *ha = vha->hw;
  1716. if (!vha->flags.online)
  1717. return;
  1718. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1719. pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
  1720. rsp->ring_index++;
  1721. if (rsp->ring_index == rsp->length) {
  1722. rsp->ring_index = 0;
  1723. rsp->ring_ptr = rsp->ring;
  1724. } else {
  1725. rsp->ring_ptr++;
  1726. }
  1727. if (pkt->entry_status != 0) {
  1728. qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt);
  1729. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1730. wmb();
  1731. continue;
  1732. }
  1733. switch (pkt->entry_type) {
  1734. case STATUS_TYPE:
  1735. qla2x00_status_entry(vha, rsp, pkt);
  1736. break;
  1737. case STATUS_CONT_TYPE:
  1738. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1739. break;
  1740. case VP_RPT_ID_IOCB_TYPE:
  1741. qla24xx_report_id_acquisition(vha,
  1742. (struct vp_rpt_id_entry_24xx *)pkt);
  1743. break;
  1744. case LOGINOUT_PORT_IOCB_TYPE:
  1745. qla24xx_logio_entry(vha, rsp->req,
  1746. (struct logio_entry_24xx *)pkt);
  1747. break;
  1748. case TSK_MGMT_IOCB_TYPE:
  1749. qla24xx_tm_iocb_entry(vha, rsp->req,
  1750. (struct tsk_mgmt_entry *)pkt);
  1751. break;
  1752. case CT_IOCB_TYPE:
  1753. qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1754. break;
  1755. case ELS_IOCB_TYPE:
  1756. qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
  1757. break;
  1758. case MARKER_TYPE:
  1759. /* Do nothing in this case, this check is to prevent it
  1760. * from falling into default case
  1761. */
  1762. break;
  1763. default:
  1764. /* Type Not Supported. */
  1765. ql_dbg(ql_dbg_async, vha, 0x5042,
  1766. "Received unknown response pkt type %x "
  1767. "entry status=%x.\n",
  1768. pkt->entry_type, pkt->entry_status);
  1769. break;
  1770. }
  1771. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1772. wmb();
  1773. }
  1774. /* Adjust ring index */
  1775. if (IS_QLA82XX(ha)) {
  1776. struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
  1777. WRT_REG_DWORD(&reg->rsp_q_out[0], rsp->ring_index);
  1778. } else
  1779. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  1780. }
  1781. static void
  1782. qla2xxx_check_risc_status(scsi_qla_host_t *vha)
  1783. {
  1784. int rval;
  1785. uint32_t cnt;
  1786. struct qla_hw_data *ha = vha->hw;
  1787. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1788. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  1789. return;
  1790. rval = QLA_SUCCESS;
  1791. WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
  1792. RD_REG_DWORD(&reg->iobase_addr);
  1793. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  1794. for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  1795. rval == QLA_SUCCESS; cnt--) {
  1796. if (cnt) {
  1797. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  1798. udelay(10);
  1799. } else
  1800. rval = QLA_FUNCTION_TIMEOUT;
  1801. }
  1802. if (rval == QLA_SUCCESS)
  1803. goto next_test;
  1804. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  1805. for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  1806. rval == QLA_SUCCESS; cnt--) {
  1807. if (cnt) {
  1808. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  1809. udelay(10);
  1810. } else
  1811. rval = QLA_FUNCTION_TIMEOUT;
  1812. }
  1813. if (rval != QLA_SUCCESS)
  1814. goto done;
  1815. next_test:
  1816. if (RD_REG_DWORD(&reg->iobase_c8) & BIT_3)
  1817. ql_log(ql_log_info, vha, 0x504c,
  1818. "Additional code -- 0x55AA.\n");
  1819. done:
  1820. WRT_REG_DWORD(&reg->iobase_window, 0x0000);
  1821. RD_REG_DWORD(&reg->iobase_window);
  1822. }
  1823. /**
  1824. * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
  1825. * @irq:
  1826. * @dev_id: SCSI driver HA context
  1827. *
  1828. * Called by system whenever the host adapter generates an interrupt.
  1829. *
  1830. * Returns handled flag.
  1831. */
  1832. irqreturn_t
  1833. qla24xx_intr_handler(int irq, void *dev_id)
  1834. {
  1835. scsi_qla_host_t *vha;
  1836. struct qla_hw_data *ha;
  1837. struct device_reg_24xx __iomem *reg;
  1838. int status;
  1839. unsigned long iter;
  1840. uint32_t stat;
  1841. uint32_t hccr;
  1842. uint16_t mb[4];
  1843. struct rsp_que *rsp;
  1844. unsigned long flags;
  1845. rsp = (struct rsp_que *) dev_id;
  1846. if (!rsp) {
  1847. ql_log(ql_log_info, NULL, 0x5059,
  1848. "%s: NULL response queue pointer.\n", __func__);
  1849. return IRQ_NONE;
  1850. }
  1851. ha = rsp->hw;
  1852. reg = &ha->iobase->isp24;
  1853. status = 0;
  1854. if (unlikely(pci_channel_offline(ha->pdev)))
  1855. return IRQ_HANDLED;
  1856. spin_lock_irqsave(&ha->hardware_lock, flags);
  1857. vha = pci_get_drvdata(ha->pdev);
  1858. for (iter = 50; iter--; ) {
  1859. stat = RD_REG_DWORD(&reg->host_status);
  1860. if (stat & HSRX_RISC_PAUSED) {
  1861. if (unlikely(pci_channel_offline(ha->pdev)))
  1862. break;
  1863. hccr = RD_REG_DWORD(&reg->hccr);
  1864. ql_log(ql_log_warn, vha, 0x504b,
  1865. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  1866. hccr);
  1867. qla2xxx_check_risc_status(vha);
  1868. ha->isp_ops->fw_dump(vha, 1);
  1869. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1870. break;
  1871. } else if ((stat & HSRX_RISC_INT) == 0)
  1872. break;
  1873. switch (stat & 0xff) {
  1874. case 0x1:
  1875. case 0x2:
  1876. case 0x10:
  1877. case 0x11:
  1878. qla24xx_mbx_completion(vha, MSW(stat));
  1879. status |= MBX_INTERRUPT;
  1880. break;
  1881. case 0x12:
  1882. mb[0] = MSW(stat);
  1883. mb[1] = RD_REG_WORD(&reg->mailbox1);
  1884. mb[2] = RD_REG_WORD(&reg->mailbox2);
  1885. mb[3] = RD_REG_WORD(&reg->mailbox3);
  1886. qla2x00_async_event(vha, rsp, mb);
  1887. break;
  1888. case 0x13:
  1889. case 0x14:
  1890. qla24xx_process_response_queue(vha, rsp);
  1891. break;
  1892. default:
  1893. ql_dbg(ql_dbg_async, vha, 0x504f,
  1894. "Unrecognized interrupt type (%d).\n", stat * 0xff);
  1895. break;
  1896. }
  1897. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  1898. RD_REG_DWORD_RELAXED(&reg->hccr);
  1899. }
  1900. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1901. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  1902. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  1903. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  1904. complete(&ha->mbx_intr_comp);
  1905. }
  1906. return IRQ_HANDLED;
  1907. }
  1908. static irqreturn_t
  1909. qla24xx_msix_rsp_q(int irq, void *dev_id)
  1910. {
  1911. struct qla_hw_data *ha;
  1912. struct rsp_que *rsp;
  1913. struct device_reg_24xx __iomem *reg;
  1914. struct scsi_qla_host *vha;
  1915. unsigned long flags;
  1916. rsp = (struct rsp_que *) dev_id;
  1917. if (!rsp) {
  1918. ql_log(ql_log_info, NULL, 0x505a,
  1919. "%s: NULL response queue pointer.\n", __func__);
  1920. return IRQ_NONE;
  1921. }
  1922. ha = rsp->hw;
  1923. reg = &ha->iobase->isp24;
  1924. spin_lock_irqsave(&ha->hardware_lock, flags);
  1925. vha = pci_get_drvdata(ha->pdev);
  1926. qla24xx_process_response_queue(vha, rsp);
  1927. if (!ha->flags.disable_msix_handshake) {
  1928. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  1929. RD_REG_DWORD_RELAXED(&reg->hccr);
  1930. }
  1931. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1932. return IRQ_HANDLED;
  1933. }
  1934. static irqreturn_t
  1935. qla25xx_msix_rsp_q(int irq, void *dev_id)
  1936. {
  1937. struct qla_hw_data *ha;
  1938. struct rsp_que *rsp;
  1939. struct device_reg_24xx __iomem *reg;
  1940. unsigned long flags;
  1941. rsp = (struct rsp_que *) dev_id;
  1942. if (!rsp) {
  1943. ql_log(ql_log_info, NULL, 0x505b,
  1944. "%s: NULL response queue pointer.\n", __func__);
  1945. return IRQ_NONE;
  1946. }
  1947. ha = rsp->hw;
  1948. /* Clear the interrupt, if enabled, for this response queue */
  1949. if (!ha->flags.disable_msix_handshake) {
  1950. reg = &ha->iobase->isp24;
  1951. spin_lock_irqsave(&ha->hardware_lock, flags);
  1952. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  1953. RD_REG_DWORD_RELAXED(&reg->hccr);
  1954. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1955. }
  1956. queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work);
  1957. return IRQ_HANDLED;
  1958. }
  1959. static irqreturn_t
  1960. qla24xx_msix_default(int irq, void *dev_id)
  1961. {
  1962. scsi_qla_host_t *vha;
  1963. struct qla_hw_data *ha;
  1964. struct rsp_que *rsp;
  1965. struct device_reg_24xx __iomem *reg;
  1966. int status;
  1967. uint32_t stat;
  1968. uint32_t hccr;
  1969. uint16_t mb[4];
  1970. unsigned long flags;
  1971. rsp = (struct rsp_que *) dev_id;
  1972. if (!rsp) {
  1973. ql_log(ql_log_info, NULL, 0x505c,
  1974. "%s: NULL response queue pointer.\n", __func__);
  1975. return IRQ_NONE;
  1976. }
  1977. ha = rsp->hw;
  1978. reg = &ha->iobase->isp24;
  1979. status = 0;
  1980. spin_lock_irqsave(&ha->hardware_lock, flags);
  1981. vha = pci_get_drvdata(ha->pdev);
  1982. do {
  1983. stat = RD_REG_DWORD(&reg->host_status);
  1984. if (stat & HSRX_RISC_PAUSED) {
  1985. if (unlikely(pci_channel_offline(ha->pdev)))
  1986. break;
  1987. hccr = RD_REG_DWORD(&reg->hccr);
  1988. ql_log(ql_log_info, vha, 0x5050,
  1989. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  1990. hccr);
  1991. qla2xxx_check_risc_status(vha);
  1992. ha->isp_ops->fw_dump(vha, 1);
  1993. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1994. break;
  1995. } else if ((stat & HSRX_RISC_INT) == 0)
  1996. break;
  1997. switch (stat & 0xff) {
  1998. case 0x1:
  1999. case 0x2:
  2000. case 0x10:
  2001. case 0x11:
  2002. qla24xx_mbx_completion(vha, MSW(stat));
  2003. status |= MBX_INTERRUPT;
  2004. break;
  2005. case 0x12:
  2006. mb[0] = MSW(stat);
  2007. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2008. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2009. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2010. qla2x00_async_event(vha, rsp, mb);
  2011. break;
  2012. case 0x13:
  2013. case 0x14:
  2014. qla24xx_process_response_queue(vha, rsp);
  2015. break;
  2016. default:
  2017. ql_dbg(ql_dbg_async, vha, 0x5051,
  2018. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  2019. break;
  2020. }
  2021. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2022. } while (0);
  2023. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2024. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2025. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2026. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2027. complete(&ha->mbx_intr_comp);
  2028. }
  2029. return IRQ_HANDLED;
  2030. }
  2031. /* Interrupt handling helpers. */
  2032. struct qla_init_msix_entry {
  2033. const char *name;
  2034. irq_handler_t handler;
  2035. };
  2036. static struct qla_init_msix_entry msix_entries[3] = {
  2037. { "qla2xxx (default)", qla24xx_msix_default },
  2038. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2039. { "qla2xxx (multiq)", qla25xx_msix_rsp_q },
  2040. };
  2041. static struct qla_init_msix_entry qla82xx_msix_entries[2] = {
  2042. { "qla2xxx (default)", qla82xx_msix_default },
  2043. { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
  2044. };
  2045. static void
  2046. qla24xx_disable_msix(struct qla_hw_data *ha)
  2047. {
  2048. int i;
  2049. struct qla_msix_entry *qentry;
  2050. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2051. for (i = 0; i < ha->msix_count; i++) {
  2052. qentry = &ha->msix_entries[i];
  2053. if (qentry->have_irq)
  2054. free_irq(qentry->vector, qentry->rsp);
  2055. }
  2056. pci_disable_msix(ha->pdev);
  2057. kfree(ha->msix_entries);
  2058. ha->msix_entries = NULL;
  2059. ha->flags.msix_enabled = 0;
  2060. ql_dbg(ql_dbg_init, vha, 0x0042,
  2061. "Disabled the MSI.\n");
  2062. }
  2063. static int
  2064. qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
  2065. {
  2066. #define MIN_MSIX_COUNT 2
  2067. int i, ret;
  2068. struct msix_entry *entries;
  2069. struct qla_msix_entry *qentry;
  2070. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2071. entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count,
  2072. GFP_KERNEL);
  2073. if (!entries) {
  2074. ql_log(ql_log_warn, vha, 0x00bc,
  2075. "Failed to allocate memory for msix_entry.\n");
  2076. return -ENOMEM;
  2077. }
  2078. for (i = 0; i < ha->msix_count; i++)
  2079. entries[i].entry = i;
  2080. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2081. if (ret) {
  2082. if (ret < MIN_MSIX_COUNT)
  2083. goto msix_failed;
  2084. ql_log(ql_log_warn, vha, 0x00c6,
  2085. "MSI-X: Failed to enable support "
  2086. "-- %d/%d\n Retry with %d vectors.\n",
  2087. ha->msix_count, ret, ret);
  2088. ha->msix_count = ret;
  2089. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2090. if (ret) {
  2091. msix_failed:
  2092. ql_log(ql_log_fatal, vha, 0x00c7,
  2093. "MSI-X: Failed to enable support, "
  2094. "giving up -- %d/%d.\n",
  2095. ha->msix_count, ret);
  2096. goto msix_out;
  2097. }
  2098. ha->max_rsp_queues = ha->msix_count - 1;
  2099. }
  2100. ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
  2101. ha->msix_count, GFP_KERNEL);
  2102. if (!ha->msix_entries) {
  2103. ql_log(ql_log_fatal, vha, 0x00c8,
  2104. "Failed to allocate memory for ha->msix_entries.\n");
  2105. ret = -ENOMEM;
  2106. goto msix_out;
  2107. }
  2108. ha->flags.msix_enabled = 1;
  2109. for (i = 0; i < ha->msix_count; i++) {
  2110. qentry = &ha->msix_entries[i];
  2111. qentry->vector = entries[i].vector;
  2112. qentry->entry = entries[i].entry;
  2113. qentry->have_irq = 0;
  2114. qentry->rsp = NULL;
  2115. }
  2116. /* Enable MSI-X vectors for the base queue */
  2117. for (i = 0; i < 2; i++) {
  2118. qentry = &ha->msix_entries[i];
  2119. if (IS_QLA82XX(ha)) {
  2120. ret = request_irq(qentry->vector,
  2121. qla82xx_msix_entries[i].handler,
  2122. 0, qla82xx_msix_entries[i].name, rsp);
  2123. } else {
  2124. ret = request_irq(qentry->vector,
  2125. msix_entries[i].handler,
  2126. 0, msix_entries[i].name, rsp);
  2127. }
  2128. if (ret) {
  2129. ql_log(ql_log_fatal, vha, 0x00cb,
  2130. "MSI-X: unable to register handler -- %x/%d.\n",
  2131. qentry->vector, ret);
  2132. qla24xx_disable_msix(ha);
  2133. ha->mqenable = 0;
  2134. goto msix_out;
  2135. }
  2136. qentry->have_irq = 1;
  2137. qentry->rsp = rsp;
  2138. rsp->msix = qentry;
  2139. }
  2140. /* Enable MSI-X vector for response queue update for queue 0 */
  2141. if (IS_QLA83XX(ha)) {
  2142. if (ha->msixbase && ha->mqiobase &&
  2143. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2144. ha->mqenable = 1;
  2145. } else
  2146. if (ha->mqiobase
  2147. && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2148. ha->mqenable = 1;
  2149. ql_dbg(ql_dbg_multiq, vha, 0xc005,
  2150. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2151. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2152. ql_dbg(ql_dbg_init, vha, 0x0055,
  2153. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2154. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2155. msix_out:
  2156. kfree(entries);
  2157. return ret;
  2158. }
  2159. int
  2160. qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
  2161. {
  2162. int ret;
  2163. device_reg_t __iomem *reg = ha->iobase;
  2164. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2165. /* If possible, enable MSI-X. */
  2166. if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2167. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
  2168. goto skip_msi;
  2169. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  2170. (ha->pdev->subsystem_device == 0x7040 ||
  2171. ha->pdev->subsystem_device == 0x7041 ||
  2172. ha->pdev->subsystem_device == 0x1705)) {
  2173. ql_log(ql_log_warn, vha, 0x0034,
  2174. "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
  2175. ha->pdev->subsystem_vendor,
  2176. ha->pdev->subsystem_device);
  2177. goto skip_msi;
  2178. }
  2179. if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
  2180. ql_log(ql_log_warn, vha, 0x0035,
  2181. "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
  2182. ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
  2183. goto skip_msix;
  2184. }
  2185. ret = qla24xx_enable_msix(ha, rsp);
  2186. if (!ret) {
  2187. ql_dbg(ql_dbg_init, vha, 0x0036,
  2188. "MSI-X: Enabled (0x%X, 0x%X).\n",
  2189. ha->chip_revision, ha->fw_attributes);
  2190. goto clear_risc_ints;
  2191. }
  2192. ql_log(ql_log_info, vha, 0x0037,
  2193. "MSI-X Falling back-to MSI mode -%d.\n", ret);
  2194. skip_msix:
  2195. if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2196. !IS_QLA8001(ha))
  2197. goto skip_msi;
  2198. ret = pci_enable_msi(ha->pdev);
  2199. if (!ret) {
  2200. ql_dbg(ql_dbg_init, vha, 0x0038,
  2201. "MSI: Enabled.\n");
  2202. ha->flags.msi_enabled = 1;
  2203. } else
  2204. ql_log(ql_log_warn, vha, 0x0039,
  2205. "MSI-X; Falling back-to INTa mode -- %d.\n", ret);
  2206. skip_msi:
  2207. ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
  2208. ha->flags.msi_enabled ? 0 : IRQF_SHARED,
  2209. QLA2XXX_DRIVER_NAME, rsp);
  2210. if (ret) {
  2211. ql_log(ql_log_warn, vha, 0x003a,
  2212. "Failed to reserve interrupt %d already in use.\n",
  2213. ha->pdev->irq);
  2214. goto fail;
  2215. }
  2216. clear_risc_ints:
  2217. /*
  2218. * FIXME: Noted that 8014s were being dropped during NK testing.
  2219. * Timing deltas during MSI-X/INTa transitions?
  2220. */
  2221. if (IS_QLA81XX(ha) || IS_QLA82XX(ha) || IS_QLA83XX(ha))
  2222. goto fail;
  2223. spin_lock_irq(&ha->hardware_lock);
  2224. if (IS_FWI2_CAPABLE(ha)) {
  2225. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_CLR_HOST_INT);
  2226. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_CLR_RISC_INT);
  2227. } else {
  2228. WRT_REG_WORD(&reg->isp.semaphore, 0);
  2229. WRT_REG_WORD(&reg->isp.hccr, HCCR_CLR_RISC_INT);
  2230. WRT_REG_WORD(&reg->isp.hccr, HCCR_CLR_HOST_INT);
  2231. }
  2232. spin_unlock_irq(&ha->hardware_lock);
  2233. fail:
  2234. return ret;
  2235. }
  2236. void
  2237. qla2x00_free_irqs(scsi_qla_host_t *vha)
  2238. {
  2239. struct qla_hw_data *ha = vha->hw;
  2240. struct rsp_que *rsp = ha->rsp_q_map[0];
  2241. if (ha->flags.msix_enabled)
  2242. qla24xx_disable_msix(ha);
  2243. else if (ha->flags.msi_enabled) {
  2244. free_irq(ha->pdev->irq, rsp);
  2245. pci_disable_msi(ha->pdev);
  2246. } else
  2247. free_irq(ha->pdev->irq, rsp);
  2248. }
  2249. int qla25xx_request_irq(struct rsp_que *rsp)
  2250. {
  2251. struct qla_hw_data *ha = rsp->hw;
  2252. struct qla_init_msix_entry *intr = &msix_entries[2];
  2253. struct qla_msix_entry *msix = rsp->msix;
  2254. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2255. int ret;
  2256. ret = request_irq(msix->vector, intr->handler, 0, intr->name, rsp);
  2257. if (ret) {
  2258. ql_log(ql_log_fatal, vha, 0x00e6,
  2259. "MSI-X: Unable to register handler -- %x/%d.\n",
  2260. msix->vector, ret);
  2261. return ret;
  2262. }
  2263. msix->have_irq = 1;
  2264. msix->rsp = rsp;
  2265. return ret;
  2266. }