i915_reg.h 139 KB

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  1. /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  2. * All Rights Reserved.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the
  6. * "Software"), to deal in the Software without restriction, including
  7. * without limitation the rights to use, copy, modify, merge, publish,
  8. * distribute, sub license, and/or sell copies of the Software, and to
  9. * permit persons to whom the Software is furnished to do so, subject to
  10. * the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the
  13. * next paragraph) shall be included in all copies or substantial portions
  14. * of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  20. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. #ifndef _I915_REG_H_
  25. #define _I915_REG_H_
  26. #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
  27. #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
  28. /*
  29. * The Bridge device's PCI config space has information about the
  30. * fb aperture size and the amount of pre-reserved memory.
  31. * This is all handled in the intel-gtt.ko module. i915.ko only
  32. * cares about the vga bit for the vga rbiter.
  33. */
  34. #define INTEL_GMCH_CTRL 0x52
  35. #define INTEL_GMCH_VGA_DISABLE (1 << 1)
  36. /* PCI config space */
  37. #define HPLLCC 0xc0 /* 855 only */
  38. #define GC_CLOCK_CONTROL_MASK (0xf << 0)
  39. #define GC_CLOCK_133_200 (0 << 0)
  40. #define GC_CLOCK_100_200 (1 << 0)
  41. #define GC_CLOCK_100_133 (2 << 0)
  42. #define GC_CLOCK_166_250 (3 << 0)
  43. #define GCFGC2 0xda
  44. #define GCFGC 0xf0 /* 915+ only */
  45. #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
  46. #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
  47. #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
  48. #define GC_DISPLAY_CLOCK_MASK (7 << 4)
  49. #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
  50. #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
  51. #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
  52. #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
  53. #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
  54. #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
  55. #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
  56. #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
  57. #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
  58. #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
  59. #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
  60. #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
  61. #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
  62. #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
  63. #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
  64. #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
  65. #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
  66. #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
  67. #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
  68. #define LBB 0xf4
  69. /* Graphics reset regs */
  70. #define I965_GDRST 0xc0 /* PCI config register */
  71. #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
  72. #define GRDOM_FULL (0<<2)
  73. #define GRDOM_RENDER (1<<2)
  74. #define GRDOM_MEDIA (3<<2)
  75. #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
  76. #define GEN6_MBC_SNPCR_SHIFT 21
  77. #define GEN6_MBC_SNPCR_MASK (3<<21)
  78. #define GEN6_MBC_SNPCR_MAX (0<<21)
  79. #define GEN6_MBC_SNPCR_MED (1<<21)
  80. #define GEN6_MBC_SNPCR_LOW (2<<21)
  81. #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
  82. #define GEN6_MBCTL 0x0907c
  83. #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
  84. #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
  85. #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
  86. #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
  87. #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
  88. #define GEN6_GDRST 0x941c
  89. #define GEN6_GRDOM_FULL (1 << 0)
  90. #define GEN6_GRDOM_RENDER (1 << 1)
  91. #define GEN6_GRDOM_MEDIA (1 << 2)
  92. #define GEN6_GRDOM_BLT (1 << 3)
  93. /* PPGTT stuff */
  94. #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
  95. #define GEN6_PDE_VALID (1 << 0)
  96. #define GEN6_PDE_LARGE_PAGE (2 << 0) /* use 32kb pages */
  97. /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  98. #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
  99. #define GEN6_PTE_VALID (1 << 0)
  100. #define GEN6_PTE_UNCACHED (1 << 1)
  101. #define GEN6_PTE_CACHE_LLC (2 << 1)
  102. #define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
  103. #define GEN6_PTE_CACHE_BITS (3 << 1)
  104. #define GEN6_PTE_GFDT (1 << 3)
  105. #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
  106. #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
  107. #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
  108. #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
  109. #define PP_DIR_DCLV_2G 0xffffffff
  110. #define GAM_ECOCHK 0x4090
  111. #define ECOCHK_SNB_BIT (1<<10)
  112. #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
  113. #define ECOCHK_PPGTT_CACHE4B (0x0<<3)
  114. /* VGA stuff */
  115. #define VGA_ST01_MDA 0x3ba
  116. #define VGA_ST01_CGA 0x3da
  117. #define VGA_MSR_WRITE 0x3c2
  118. #define VGA_MSR_READ 0x3cc
  119. #define VGA_MSR_MEM_EN (1<<1)
  120. #define VGA_MSR_CGA_MODE (1<<0)
  121. #define VGA_SR_INDEX 0x3c4
  122. #define VGA_SR_DATA 0x3c5
  123. #define VGA_AR_INDEX 0x3c0
  124. #define VGA_AR_VID_EN (1<<5)
  125. #define VGA_AR_DATA_WRITE 0x3c0
  126. #define VGA_AR_DATA_READ 0x3c1
  127. #define VGA_GR_INDEX 0x3ce
  128. #define VGA_GR_DATA 0x3cf
  129. /* GR05 */
  130. #define VGA_GR_MEM_READ_MODE_SHIFT 3
  131. #define VGA_GR_MEM_READ_MODE_PLANE 1
  132. /* GR06 */
  133. #define VGA_GR_MEM_MODE_MASK 0xc
  134. #define VGA_GR_MEM_MODE_SHIFT 2
  135. #define VGA_GR_MEM_A0000_AFFFF 0
  136. #define VGA_GR_MEM_A0000_BFFFF 1
  137. #define VGA_GR_MEM_B0000_B7FFF 2
  138. #define VGA_GR_MEM_B0000_BFFFF 3
  139. #define VGA_DACMASK 0x3c6
  140. #define VGA_DACRX 0x3c7
  141. #define VGA_DACWX 0x3c8
  142. #define VGA_DACDATA 0x3c9
  143. #define VGA_CR_INDEX_MDA 0x3b4
  144. #define VGA_CR_DATA_MDA 0x3b5
  145. #define VGA_CR_INDEX_CGA 0x3d4
  146. #define VGA_CR_DATA_CGA 0x3d5
  147. /*
  148. * Memory interface instructions used by the kernel
  149. */
  150. #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
  151. #define MI_NOOP MI_INSTR(0, 0)
  152. #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
  153. #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
  154. #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
  155. #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
  156. #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
  157. #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
  158. #define MI_FLUSH MI_INSTR(0x04, 0)
  159. #define MI_READ_FLUSH (1 << 0)
  160. #define MI_EXE_FLUSH (1 << 1)
  161. #define MI_NO_WRITE_FLUSH (1 << 2)
  162. #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
  163. #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
  164. #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
  165. #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
  166. #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
  167. #define MI_SUSPEND_FLUSH_EN (1<<0)
  168. #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
  169. #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
  170. #define MI_OVERLAY_CONTINUE (0x0<<21)
  171. #define MI_OVERLAY_ON (0x1<<21)
  172. #define MI_OVERLAY_OFF (0x2<<21)
  173. #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
  174. #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
  175. #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
  176. #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
  177. /* IVB has funny definitions for which plane to flip. */
  178. #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
  179. #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
  180. #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
  181. #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
  182. #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
  183. #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
  184. #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
  185. #define MI_MM_SPACE_GTT (1<<8)
  186. #define MI_MM_SPACE_PHYSICAL (0<<8)
  187. #define MI_SAVE_EXT_STATE_EN (1<<3)
  188. #define MI_RESTORE_EXT_STATE_EN (1<<2)
  189. #define MI_FORCE_RESTORE (1<<1)
  190. #define MI_RESTORE_INHIBIT (1<<0)
  191. #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
  192. #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
  193. #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
  194. #define MI_STORE_DWORD_INDEX_SHIFT 2
  195. /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
  196. * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
  197. * simply ignores the register load under certain conditions.
  198. * - One can actually load arbitrary many arbitrary registers: Simply issue x
  199. * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
  200. */
  201. #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
  202. #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
  203. #define MI_INVALIDATE_TLB (1<<18)
  204. #define MI_INVALIDATE_BSD (1<<7)
  205. #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
  206. #define MI_BATCH_NON_SECURE (1)
  207. #define MI_BATCH_NON_SECURE_I965 (1<<8)
  208. #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
  209. #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
  210. #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
  211. #define MI_SEMAPHORE_UPDATE (1<<21)
  212. #define MI_SEMAPHORE_COMPARE (1<<20)
  213. #define MI_SEMAPHORE_REGISTER (1<<18)
  214. #define MI_SEMAPHORE_SYNC_RV (2<<16)
  215. #define MI_SEMAPHORE_SYNC_RB (0<<16)
  216. #define MI_SEMAPHORE_SYNC_VR (0<<16)
  217. #define MI_SEMAPHORE_SYNC_VB (2<<16)
  218. #define MI_SEMAPHORE_SYNC_BR (2<<16)
  219. #define MI_SEMAPHORE_SYNC_BV (0<<16)
  220. #define MI_SEMAPHORE_SYNC_INVALID (1<<0)
  221. /*
  222. * 3D instructions used by the kernel
  223. */
  224. #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
  225. #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
  226. #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
  227. #define SC_UPDATE_SCISSOR (0x1<<1)
  228. #define SC_ENABLE_MASK (0x1<<0)
  229. #define SC_ENABLE (0x1<<0)
  230. #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
  231. #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
  232. #define SCI_YMIN_MASK (0xffff<<16)
  233. #define SCI_XMIN_MASK (0xffff<<0)
  234. #define SCI_YMAX_MASK (0xffff<<16)
  235. #define SCI_XMAX_MASK (0xffff<<0)
  236. #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
  237. #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
  238. #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
  239. #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
  240. #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
  241. #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
  242. #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
  243. #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
  244. #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
  245. #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
  246. #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
  247. #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
  248. #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
  249. #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
  250. #define BLT_DEPTH_8 (0<<24)
  251. #define BLT_DEPTH_16_565 (1<<24)
  252. #define BLT_DEPTH_16_1555 (2<<24)
  253. #define BLT_DEPTH_32 (3<<24)
  254. #define BLT_ROP_GXCOPY (0xcc<<16)
  255. #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
  256. #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
  257. #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
  258. #define ASYNC_FLIP (1<<22)
  259. #define DISPLAY_PLANE_A (0<<20)
  260. #define DISPLAY_PLANE_B (1<<20)
  261. #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
  262. #define PIPE_CONTROL_CS_STALL (1<<20)
  263. #define PIPE_CONTROL_QW_WRITE (1<<14)
  264. #define PIPE_CONTROL_DEPTH_STALL (1<<13)
  265. #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
  266. #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
  267. #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
  268. #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
  269. #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
  270. #define PIPE_CONTROL_NOTIFY (1<<8)
  271. #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
  272. #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
  273. #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
  274. #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
  275. #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
  276. #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
  277. /*
  278. * Reset registers
  279. */
  280. #define DEBUG_RESET_I830 0x6070
  281. #define DEBUG_RESET_FULL (1<<7)
  282. #define DEBUG_RESET_RENDER (1<<8)
  283. #define DEBUG_RESET_DISPLAY (1<<9)
  284. /*
  285. * Fence registers
  286. */
  287. #define FENCE_REG_830_0 0x2000
  288. #define FENCE_REG_945_8 0x3000
  289. #define I830_FENCE_START_MASK 0x07f80000
  290. #define I830_FENCE_TILING_Y_SHIFT 12
  291. #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
  292. #define I830_FENCE_PITCH_SHIFT 4
  293. #define I830_FENCE_REG_VALID (1<<0)
  294. #define I915_FENCE_MAX_PITCH_VAL 4
  295. #define I830_FENCE_MAX_PITCH_VAL 6
  296. #define I830_FENCE_MAX_SIZE_VAL (1<<8)
  297. #define I915_FENCE_START_MASK 0x0ff00000
  298. #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
  299. #define FENCE_REG_965_0 0x03000
  300. #define I965_FENCE_PITCH_SHIFT 2
  301. #define I965_FENCE_TILING_Y_SHIFT 1
  302. #define I965_FENCE_REG_VALID (1<<0)
  303. #define I965_FENCE_MAX_PITCH_VAL 0x0400
  304. #define FENCE_REG_SANDYBRIDGE_0 0x100000
  305. #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
  306. /* control register for cpu gtt access */
  307. #define TILECTL 0x101000
  308. #define TILECTL_SWZCTL (1 << 0)
  309. #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
  310. #define TILECTL_BACKSNOOP_DIS (1 << 3)
  311. /*
  312. * Instruction and interrupt control regs
  313. */
  314. #define PGTBL_ER 0x02024
  315. #define RENDER_RING_BASE 0x02000
  316. #define BSD_RING_BASE 0x04000
  317. #define GEN6_BSD_RING_BASE 0x12000
  318. #define BLT_RING_BASE 0x22000
  319. #define RING_TAIL(base) ((base)+0x30)
  320. #define RING_HEAD(base) ((base)+0x34)
  321. #define RING_START(base) ((base)+0x38)
  322. #define RING_CTL(base) ((base)+0x3c)
  323. #define RING_SYNC_0(base) ((base)+0x40)
  324. #define RING_SYNC_1(base) ((base)+0x44)
  325. #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
  326. #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
  327. #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
  328. #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
  329. #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
  330. #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
  331. #define RING_MAX_IDLE(base) ((base)+0x54)
  332. #define RING_HWS_PGA(base) ((base)+0x80)
  333. #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
  334. #define ARB_MODE 0x04030
  335. #define ARB_MODE_SWIZZLE_SNB (1<<4)
  336. #define ARB_MODE_SWIZZLE_IVB (1<<5)
  337. #define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x)
  338. #define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x)
  339. #define RENDER_HWS_PGA_GEN7 (0x04080)
  340. #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
  341. #define DONE_REG 0x40b0
  342. #define BSD_HWS_PGA_GEN7 (0x04180)
  343. #define BLT_HWS_PGA_GEN7 (0x04280)
  344. #define RING_ACTHD(base) ((base)+0x74)
  345. #define RING_NOPID(base) ((base)+0x94)
  346. #define RING_IMR(base) ((base)+0xa8)
  347. #define TAIL_ADDR 0x001FFFF8
  348. #define HEAD_WRAP_COUNT 0xFFE00000
  349. #define HEAD_WRAP_ONE 0x00200000
  350. #define HEAD_ADDR 0x001FFFFC
  351. #define RING_NR_PAGES 0x001FF000
  352. #define RING_REPORT_MASK 0x00000006
  353. #define RING_REPORT_64K 0x00000002
  354. #define RING_REPORT_128K 0x00000004
  355. #define RING_NO_REPORT 0x00000000
  356. #define RING_VALID_MASK 0x00000001
  357. #define RING_VALID 0x00000001
  358. #define RING_INVALID 0x00000000
  359. #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
  360. #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
  361. #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
  362. #if 0
  363. #define PRB0_TAIL 0x02030
  364. #define PRB0_HEAD 0x02034
  365. #define PRB0_START 0x02038
  366. #define PRB0_CTL 0x0203c
  367. #define PRB1_TAIL 0x02040 /* 915+ only */
  368. #define PRB1_HEAD 0x02044 /* 915+ only */
  369. #define PRB1_START 0x02048 /* 915+ only */
  370. #define PRB1_CTL 0x0204c /* 915+ only */
  371. #endif
  372. #define IPEIR_I965 0x02064
  373. #define IPEHR_I965 0x02068
  374. #define INSTDONE_I965 0x0206c
  375. #define RING_IPEIR(base) ((base)+0x64)
  376. #define RING_IPEHR(base) ((base)+0x68)
  377. #define RING_INSTDONE(base) ((base)+0x6c)
  378. #define RING_INSTPS(base) ((base)+0x70)
  379. #define RING_DMA_FADD(base) ((base)+0x78)
  380. #define RING_INSTPM(base) ((base)+0xc0)
  381. #define INSTPS 0x02070 /* 965+ only */
  382. #define INSTDONE1 0x0207c /* 965+ only */
  383. #define ACTHD_I965 0x02074
  384. #define HWS_PGA 0x02080
  385. #define HWS_ADDRESS_MASK 0xfffff000
  386. #define HWS_START_ADDRESS_SHIFT 4
  387. #define PWRCTXA 0x2088 /* 965GM+ only */
  388. #define PWRCTX_EN (1<<0)
  389. #define IPEIR 0x02088
  390. #define IPEHR 0x0208c
  391. #define INSTDONE 0x02090
  392. #define NOPID 0x02094
  393. #define HWSTAM 0x02098
  394. #define ERROR_GEN6 0x040a0
  395. /* GM45+ chicken bits -- debug workaround bits that may be required
  396. * for various sorts of correct behavior. The top 16 bits of each are
  397. * the enables for writing to the corresponding low bit.
  398. */
  399. #define _3D_CHICKEN 0x02084
  400. #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
  401. #define _3D_CHICKEN2 0x0208c
  402. /* Disables pipelining of read flushes past the SF-WIZ interface.
  403. * Required on all Ironlake steppings according to the B-Spec, but the
  404. * particular danger of not doing so is not specified.
  405. */
  406. # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
  407. #define _3D_CHICKEN3 0x02090
  408. #define MI_MODE 0x0209c
  409. # define VS_TIMER_DISPATCH (1 << 6)
  410. # define MI_FLUSH_ENABLE (1 << 12)
  411. #define GEN6_GT_MODE 0x20d0
  412. #define GEN6_GT_MODE_HI (1 << 9)
  413. #define GFX_MODE 0x02520
  414. #define GFX_MODE_GEN7 0x0229c
  415. #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
  416. #define GFX_RUN_LIST_ENABLE (1<<15)
  417. #define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
  418. #define GFX_SURFACE_FAULT_ENABLE (1<<12)
  419. #define GFX_REPLAY_MODE (1<<11)
  420. #define GFX_PSMI_GRANULARITY (1<<10)
  421. #define GFX_PPGTT_ENABLE (1<<9)
  422. #define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit))
  423. #define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0))
  424. #define SCPD0 0x0209c /* 915+ only */
  425. #define IER 0x020a0
  426. #define IIR 0x020a4
  427. #define IMR 0x020a8
  428. #define ISR 0x020ac
  429. #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
  430. #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
  431. #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
  432. #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
  433. #define I915_HWB_OOM_INTERRUPT (1<<13)
  434. #define I915_SYNC_STATUS_INTERRUPT (1<<12)
  435. #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
  436. #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
  437. #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
  438. #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
  439. #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
  440. #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
  441. #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
  442. #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
  443. #define I915_DEBUG_INTERRUPT (1<<2)
  444. #define I915_USER_INTERRUPT (1<<1)
  445. #define I915_ASLE_INTERRUPT (1<<0)
  446. #define I915_BSD_USER_INTERRUPT (1<<25)
  447. #define EIR 0x020b0
  448. #define EMR 0x020b4
  449. #define ESR 0x020b8
  450. #define GM45_ERROR_PAGE_TABLE (1<<5)
  451. #define GM45_ERROR_MEM_PRIV (1<<4)
  452. #define I915_ERROR_PAGE_TABLE (1<<4)
  453. #define GM45_ERROR_CP_PRIV (1<<3)
  454. #define I915_ERROR_MEMORY_REFRESH (1<<1)
  455. #define I915_ERROR_INSTRUCTION (1<<0)
  456. #define INSTPM 0x020c0
  457. #define INSTPM_SELF_EN (1<<12) /* 915GM only */
  458. #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
  459. will not assert AGPBUSY# and will only
  460. be delivered when out of C3. */
  461. #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
  462. #define INSTPM_TLB_INVALIDATE (1<<9)
  463. #define INSTPM_SYNC_FLUSH (1<<5)
  464. #define ACTHD 0x020c8
  465. #define FW_BLC 0x020d8
  466. #define FW_BLC2 0x020dc
  467. #define FW_BLC_SELF 0x020e0 /* 915+ only */
  468. #define FW_BLC_SELF_EN_MASK (1<<31)
  469. #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
  470. #define FW_BLC_SELF_EN (1<<15) /* 945 only */
  471. #define MM_BURST_LENGTH 0x00700000
  472. #define MM_FIFO_WATERMARK 0x0001F000
  473. #define LM_BURST_LENGTH 0x00000700
  474. #define LM_FIFO_WATERMARK 0x0000001F
  475. #define MI_ARB_STATE 0x020e4 /* 915+ only */
  476. #define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
  477. /* Make render/texture TLB fetches lower priorty than associated data
  478. * fetches. This is not turned on by default
  479. */
  480. #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
  481. /* Isoch request wait on GTT enable (Display A/B/C streams).
  482. * Make isoch requests stall on the TLB update. May cause
  483. * display underruns (test mode only)
  484. */
  485. #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
  486. /* Block grant count for isoch requests when block count is
  487. * set to a finite value.
  488. */
  489. #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
  490. #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
  491. #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
  492. #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
  493. #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
  494. /* Enable render writes to complete in C2/C3/C4 power states.
  495. * If this isn't enabled, render writes are prevented in low
  496. * power states. That seems bad to me.
  497. */
  498. #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
  499. /* This acknowledges an async flip immediately instead
  500. * of waiting for 2TLB fetches.
  501. */
  502. #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
  503. /* Enables non-sequential data reads through arbiter
  504. */
  505. #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
  506. /* Disable FSB snooping of cacheable write cycles from binner/render
  507. * command stream
  508. */
  509. #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
  510. /* Arbiter time slice for non-isoch streams */
  511. #define MI_ARB_TIME_SLICE_MASK (7 << 5)
  512. #define MI_ARB_TIME_SLICE_1 (0 << 5)
  513. #define MI_ARB_TIME_SLICE_2 (1 << 5)
  514. #define MI_ARB_TIME_SLICE_4 (2 << 5)
  515. #define MI_ARB_TIME_SLICE_6 (3 << 5)
  516. #define MI_ARB_TIME_SLICE_8 (4 << 5)
  517. #define MI_ARB_TIME_SLICE_10 (5 << 5)
  518. #define MI_ARB_TIME_SLICE_14 (6 << 5)
  519. #define MI_ARB_TIME_SLICE_16 (7 << 5)
  520. /* Low priority grace period page size */
  521. #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
  522. #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
  523. /* Disable display A/B trickle feed */
  524. #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
  525. /* Set display plane priority */
  526. #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
  527. #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
  528. #define CACHE_MODE_0 0x02120 /* 915+ only */
  529. #define CM0_MASK_SHIFT 16
  530. #define CM0_IZ_OPT_DISABLE (1<<6)
  531. #define CM0_ZR_OPT_DISABLE (1<<5)
  532. #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
  533. #define CM0_DEPTH_EVICT_DISABLE (1<<4)
  534. #define CM0_COLOR_EVICT_DISABLE (1<<3)
  535. #define CM0_DEPTH_WRITE_DISABLE (1<<1)
  536. #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
  537. #define BB_ADDR 0x02140 /* 8 bytes */
  538. #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
  539. #define ECOSKPD 0x021d0
  540. #define ECO_GATING_CX_ONLY (1<<3)
  541. #define ECO_FLIP_DONE (1<<0)
  542. /* GEN6 interrupt control */
  543. #define GEN6_RENDER_HWSTAM 0x2098
  544. #define GEN6_RENDER_IMR 0x20a8
  545. #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
  546. #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
  547. #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
  548. #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
  549. #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
  550. #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
  551. #define GEN6_RENDER_SYNC_STATUS (1 << 2)
  552. #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
  553. #define GEN6_RENDER_USER_INTERRUPT (1 << 0)
  554. #define GEN6_BLITTER_HWSTAM 0x22098
  555. #define GEN6_BLITTER_IMR 0x220a8
  556. #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
  557. #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
  558. #define GEN6_BLITTER_SYNC_STATUS (1 << 24)
  559. #define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
  560. #define GEN6_BLITTER_ECOSKPD 0x221d0
  561. #define GEN6_BLITTER_LOCK_SHIFT 16
  562. #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
  563. #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
  564. #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16)
  565. #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0)
  566. #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0
  567. #define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
  568. #define GEN6_BSD_HWSTAM 0x12098
  569. #define GEN6_BSD_IMR 0x120a8
  570. #define GEN6_BSD_USER_INTERRUPT (1 << 12)
  571. #define GEN6_BSD_RNCID 0x12198
  572. #define GEN7_FF_THREAD_MODE 0x20a0
  573. #define GEN7_FF_SCHED_MASK 0x0077070
  574. #define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
  575. #define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
  576. #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
  577. #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
  578. #define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
  579. #define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
  580. #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
  581. #define GEN7_FF_VS_SCHED_HW (0x0<<12)
  582. #define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
  583. #define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
  584. #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
  585. #define GEN7_FF_DS_SCHED_HW (0x0<<4)
  586. /*
  587. * Framebuffer compression (915+ only)
  588. */
  589. #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
  590. #define FBC_LL_BASE 0x03204 /* 4k page aligned */
  591. #define FBC_CONTROL 0x03208
  592. #define FBC_CTL_EN (1<<31)
  593. #define FBC_CTL_PERIODIC (1<<30)
  594. #define FBC_CTL_INTERVAL_SHIFT (16)
  595. #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
  596. #define FBC_CTL_C3_IDLE (1<<13)
  597. #define FBC_CTL_STRIDE_SHIFT (5)
  598. #define FBC_CTL_FENCENO (1<<0)
  599. #define FBC_COMMAND 0x0320c
  600. #define FBC_CMD_COMPRESS (1<<0)
  601. #define FBC_STATUS 0x03210
  602. #define FBC_STAT_COMPRESSING (1<<31)
  603. #define FBC_STAT_COMPRESSED (1<<30)
  604. #define FBC_STAT_MODIFIED (1<<29)
  605. #define FBC_STAT_CURRENT_LINE (1<<0)
  606. #define FBC_CONTROL2 0x03214
  607. #define FBC_CTL_FENCE_DBL (0<<4)
  608. #define FBC_CTL_IDLE_IMM (0<<2)
  609. #define FBC_CTL_IDLE_FULL (1<<2)
  610. #define FBC_CTL_IDLE_LINE (2<<2)
  611. #define FBC_CTL_IDLE_DEBUG (3<<2)
  612. #define FBC_CTL_CPU_FENCE (1<<1)
  613. #define FBC_CTL_PLANEA (0<<0)
  614. #define FBC_CTL_PLANEB (1<<0)
  615. #define FBC_FENCE_OFF 0x0321b
  616. #define FBC_TAG 0x03300
  617. #define FBC_LL_SIZE (1536)
  618. /* Framebuffer compression for GM45+ */
  619. #define DPFC_CB_BASE 0x3200
  620. #define DPFC_CONTROL 0x3208
  621. #define DPFC_CTL_EN (1<<31)
  622. #define DPFC_CTL_PLANEA (0<<30)
  623. #define DPFC_CTL_PLANEB (1<<30)
  624. #define DPFC_CTL_FENCE_EN (1<<29)
  625. #define DPFC_CTL_PERSISTENT_MODE (1<<25)
  626. #define DPFC_SR_EN (1<<10)
  627. #define DPFC_CTL_LIMIT_1X (0<<6)
  628. #define DPFC_CTL_LIMIT_2X (1<<6)
  629. #define DPFC_CTL_LIMIT_4X (2<<6)
  630. #define DPFC_RECOMP_CTL 0x320c
  631. #define DPFC_RECOMP_STALL_EN (1<<27)
  632. #define DPFC_RECOMP_STALL_WM_SHIFT (16)
  633. #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
  634. #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
  635. #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
  636. #define DPFC_STATUS 0x3210
  637. #define DPFC_INVAL_SEG_SHIFT (16)
  638. #define DPFC_INVAL_SEG_MASK (0x07ff0000)
  639. #define DPFC_COMP_SEG_SHIFT (0)
  640. #define DPFC_COMP_SEG_MASK (0x000003ff)
  641. #define DPFC_STATUS2 0x3214
  642. #define DPFC_FENCE_YOFF 0x3218
  643. #define DPFC_CHICKEN 0x3224
  644. #define DPFC_HT_MODIFY (1<<31)
  645. /* Framebuffer compression for Ironlake */
  646. #define ILK_DPFC_CB_BASE 0x43200
  647. #define ILK_DPFC_CONTROL 0x43208
  648. /* The bit 28-8 is reserved */
  649. #define DPFC_RESERVED (0x1FFFFF00)
  650. #define ILK_DPFC_RECOMP_CTL 0x4320c
  651. #define ILK_DPFC_STATUS 0x43210
  652. #define ILK_DPFC_FENCE_YOFF 0x43218
  653. #define ILK_DPFC_CHICKEN 0x43224
  654. #define ILK_FBC_RT_BASE 0x2128
  655. #define ILK_FBC_RT_VALID (1<<0)
  656. #define ILK_DISPLAY_CHICKEN1 0x42000
  657. #define ILK_FBCQ_DIS (1<<22)
  658. #define ILK_PABSTRETCH_DIS (1<<21)
  659. /*
  660. * Framebuffer compression for Sandybridge
  661. *
  662. * The following two registers are of type GTTMMADR
  663. */
  664. #define SNB_DPFC_CTL_SA 0x100100
  665. #define SNB_CPU_FENCE_ENABLE (1<<29)
  666. #define DPFC_CPU_FENCE_OFFSET 0x100104
  667. /*
  668. * GPIO regs
  669. */
  670. #define GPIOA 0x5010
  671. #define GPIOB 0x5014
  672. #define GPIOC 0x5018
  673. #define GPIOD 0x501c
  674. #define GPIOE 0x5020
  675. #define GPIOF 0x5024
  676. #define GPIOG 0x5028
  677. #define GPIOH 0x502c
  678. # define GPIO_CLOCK_DIR_MASK (1 << 0)
  679. # define GPIO_CLOCK_DIR_IN (0 << 1)
  680. # define GPIO_CLOCK_DIR_OUT (1 << 1)
  681. # define GPIO_CLOCK_VAL_MASK (1 << 2)
  682. # define GPIO_CLOCK_VAL_OUT (1 << 3)
  683. # define GPIO_CLOCK_VAL_IN (1 << 4)
  684. # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
  685. # define GPIO_DATA_DIR_MASK (1 << 8)
  686. # define GPIO_DATA_DIR_IN (0 << 9)
  687. # define GPIO_DATA_DIR_OUT (1 << 9)
  688. # define GPIO_DATA_VAL_MASK (1 << 10)
  689. # define GPIO_DATA_VAL_OUT (1 << 11)
  690. # define GPIO_DATA_VAL_IN (1 << 12)
  691. # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
  692. #define GMBUS0 0x5100 /* clock/port select */
  693. #define GMBUS_RATE_100KHZ (0<<8)
  694. #define GMBUS_RATE_50KHZ (1<<8)
  695. #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
  696. #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
  697. #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
  698. #define GMBUS_PORT_DISABLED 0
  699. #define GMBUS_PORT_SSC 1
  700. #define GMBUS_PORT_VGADDC 2
  701. #define GMBUS_PORT_PANEL 3
  702. #define GMBUS_PORT_DPC 4 /* HDMIC */
  703. #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
  704. /* 6 reserved */
  705. #define GMBUS_PORT_DPD 7 /* HDMID */
  706. #define GMBUS_NUM_PORTS 8
  707. #define GMBUS1 0x5104 /* command/status */
  708. #define GMBUS_SW_CLR_INT (1<<31)
  709. #define GMBUS_SW_RDY (1<<30)
  710. #define GMBUS_ENT (1<<29) /* enable timeout */
  711. #define GMBUS_CYCLE_NONE (0<<25)
  712. #define GMBUS_CYCLE_WAIT (1<<25)
  713. #define GMBUS_CYCLE_INDEX (2<<25)
  714. #define GMBUS_CYCLE_STOP (4<<25)
  715. #define GMBUS_BYTE_COUNT_SHIFT 16
  716. #define GMBUS_SLAVE_INDEX_SHIFT 8
  717. #define GMBUS_SLAVE_ADDR_SHIFT 1
  718. #define GMBUS_SLAVE_READ (1<<0)
  719. #define GMBUS_SLAVE_WRITE (0<<0)
  720. #define GMBUS2 0x5108 /* status */
  721. #define GMBUS_INUSE (1<<15)
  722. #define GMBUS_HW_WAIT_PHASE (1<<14)
  723. #define GMBUS_STALL_TIMEOUT (1<<13)
  724. #define GMBUS_INT (1<<12)
  725. #define GMBUS_HW_RDY (1<<11)
  726. #define GMBUS_SATOER (1<<10)
  727. #define GMBUS_ACTIVE (1<<9)
  728. #define GMBUS3 0x510c /* data buffer bytes 3-0 */
  729. #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
  730. #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
  731. #define GMBUS_NAK_EN (1<<3)
  732. #define GMBUS_IDLE_EN (1<<2)
  733. #define GMBUS_HW_WAIT_EN (1<<1)
  734. #define GMBUS_HW_RDY_EN (1<<0)
  735. #define GMBUS5 0x5120 /* byte index */
  736. #define GMBUS_2BYTE_INDEX_EN (1<<31)
  737. /*
  738. * Clock control & power management
  739. */
  740. #define VGA0 0x6000
  741. #define VGA1 0x6004
  742. #define VGA_PD 0x6010
  743. #define VGA0_PD_P2_DIV_4 (1 << 7)
  744. #define VGA0_PD_P1_DIV_2 (1 << 5)
  745. #define VGA0_PD_P1_SHIFT 0
  746. #define VGA0_PD_P1_MASK (0x1f << 0)
  747. #define VGA1_PD_P2_DIV_4 (1 << 15)
  748. #define VGA1_PD_P1_DIV_2 (1 << 13)
  749. #define VGA1_PD_P1_SHIFT 8
  750. #define VGA1_PD_P1_MASK (0x1f << 8)
  751. #define _DPLL_A 0x06014
  752. #define _DPLL_B 0x06018
  753. #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
  754. #define DPLL_VCO_ENABLE (1 << 31)
  755. #define DPLL_DVO_HIGH_SPEED (1 << 30)
  756. #define DPLL_SYNCLOCK_ENABLE (1 << 29)
  757. #define DPLL_VGA_MODE_DIS (1 << 28)
  758. #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
  759. #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
  760. #define DPLL_MODE_MASK (3 << 26)
  761. #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
  762. #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
  763. #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
  764. #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
  765. #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
  766. #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
  767. #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
  768. #define SRX_INDEX 0x3c4
  769. #define SRX_DATA 0x3c5
  770. #define SR01 1
  771. #define SR01_SCREEN_OFF (1<<5)
  772. #define PPCR 0x61204
  773. #define PPCR_ON (1<<0)
  774. #define DVOB 0x61140
  775. #define DVOB_ON (1<<31)
  776. #define DVOC 0x61160
  777. #define DVOC_ON (1<<31)
  778. #define LVDS 0x61180
  779. #define LVDS_ON (1<<31)
  780. /* Scratch pad debug 0 reg:
  781. */
  782. #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
  783. /*
  784. * The i830 generation, in LVDS mode, defines P1 as the bit number set within
  785. * this field (only one bit may be set).
  786. */
  787. #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
  788. #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
  789. #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
  790. /* i830, required in DVO non-gang */
  791. #define PLL_P2_DIVIDE_BY_4 (1 << 23)
  792. #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
  793. #define PLL_REF_INPUT_DREFCLK (0 << 13)
  794. #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
  795. #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
  796. #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
  797. #define PLL_REF_INPUT_MASK (3 << 13)
  798. #define PLL_LOAD_PULSE_PHASE_SHIFT 9
  799. /* Ironlake */
  800. # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
  801. # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
  802. # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
  803. # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
  804. # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
  805. /*
  806. * Parallel to Serial Load Pulse phase selection.
  807. * Selects the phase for the 10X DPLL clock for the PCIe
  808. * digital display port. The range is 4 to 13; 10 or more
  809. * is just a flip delay. The default is 6
  810. */
  811. #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
  812. #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
  813. /*
  814. * SDVO multiplier for 945G/GM. Not used on 965.
  815. */
  816. #define SDVO_MULTIPLIER_MASK 0x000000ff
  817. #define SDVO_MULTIPLIER_SHIFT_HIRES 4
  818. #define SDVO_MULTIPLIER_SHIFT_VGA 0
  819. #define _DPLL_A_MD 0x0601c /* 965+ only */
  820. /*
  821. * UDI pixel divider, controlling how many pixels are stuffed into a packet.
  822. *
  823. * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
  824. */
  825. #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
  826. #define DPLL_MD_UDI_DIVIDER_SHIFT 24
  827. /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
  828. #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
  829. #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
  830. /*
  831. * SDVO/UDI pixel multiplier.
  832. *
  833. * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
  834. * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
  835. * modes, the bus rate would be below the limits, so SDVO allows for stuffing
  836. * dummy bytes in the datastream at an increased clock rate, with both sides of
  837. * the link knowing how many bytes are fill.
  838. *
  839. * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
  840. * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
  841. * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
  842. * through an SDVO command.
  843. *
  844. * This register field has values of multiplication factor minus 1, with
  845. * a maximum multiplier of 5 for SDVO.
  846. */
  847. #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
  848. #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
  849. /*
  850. * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
  851. * This best be set to the default value (3) or the CRT won't work. No,
  852. * I don't entirely understand what this does...
  853. */
  854. #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
  855. #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
  856. #define _DPLL_B_MD 0x06020 /* 965+ only */
  857. #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
  858. #define _FPA0 0x06040
  859. #define _FPA1 0x06044
  860. #define _FPB0 0x06048
  861. #define _FPB1 0x0604c
  862. #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
  863. #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
  864. #define FP_N_DIV_MASK 0x003f0000
  865. #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
  866. #define FP_N_DIV_SHIFT 16
  867. #define FP_M1_DIV_MASK 0x00003f00
  868. #define FP_M1_DIV_SHIFT 8
  869. #define FP_M2_DIV_MASK 0x0000003f
  870. #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
  871. #define FP_M2_DIV_SHIFT 0
  872. #define DPLL_TEST 0x606c
  873. #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
  874. #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
  875. #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
  876. #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
  877. #define DPLLB_TEST_N_BYPASS (1 << 19)
  878. #define DPLLB_TEST_M_BYPASS (1 << 18)
  879. #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
  880. #define DPLLA_TEST_N_BYPASS (1 << 3)
  881. #define DPLLA_TEST_M_BYPASS (1 << 2)
  882. #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
  883. #define D_STATE 0x6104
  884. #define DSTATE_GFX_RESET_I830 (1<<6)
  885. #define DSTATE_PLL_D3_OFF (1<<3)
  886. #define DSTATE_GFX_CLOCK_GATING (1<<1)
  887. #define DSTATE_DOT_CLOCK_GATING (1<<0)
  888. #define DSPCLK_GATE_D 0x6200
  889. # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
  890. # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
  891. # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
  892. # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
  893. # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
  894. # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
  895. # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
  896. # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
  897. # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
  898. # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
  899. # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
  900. # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
  901. # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
  902. # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
  903. # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
  904. # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
  905. # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
  906. # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
  907. # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
  908. # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
  909. # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
  910. # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
  911. # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
  912. # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
  913. # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
  914. # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
  915. # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
  916. # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
  917. /**
  918. * This bit must be set on the 830 to prevent hangs when turning off the
  919. * overlay scaler.
  920. */
  921. # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
  922. # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
  923. # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
  924. # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
  925. # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
  926. #define RENCLK_GATE_D1 0x6204
  927. # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
  928. # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
  929. # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
  930. # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
  931. # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
  932. # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
  933. # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
  934. # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
  935. # define MAG_CLOCK_GATE_DISABLE (1 << 5)
  936. /** This bit must be unset on 855,865 */
  937. # define MECI_CLOCK_GATE_DISABLE (1 << 4)
  938. # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
  939. # define MEC_CLOCK_GATE_DISABLE (1 << 2)
  940. # define MECO_CLOCK_GATE_DISABLE (1 << 1)
  941. /** This bit must be set on 855,865. */
  942. # define SV_CLOCK_GATE_DISABLE (1 << 0)
  943. # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
  944. # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
  945. # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
  946. # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
  947. # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
  948. # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
  949. # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
  950. # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
  951. # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
  952. # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
  953. # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
  954. # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
  955. # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
  956. # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
  957. # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
  958. # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
  959. # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
  960. # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
  961. /** This bit must always be set on 965G/965GM */
  962. # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
  963. # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
  964. # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
  965. # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
  966. # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
  967. # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
  968. /** This bit must always be set on 965G */
  969. # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
  970. # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
  971. # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
  972. # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
  973. # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
  974. # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
  975. # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
  976. # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
  977. # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
  978. # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
  979. # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
  980. # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
  981. # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
  982. # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
  983. # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
  984. # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
  985. # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
  986. # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
  987. # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
  988. #define RENCLK_GATE_D2 0x6208
  989. #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
  990. #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
  991. #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
  992. #define RAMCLK_GATE_D 0x6210 /* CRL only */
  993. #define DEUC 0x6214 /* CRL only */
  994. /*
  995. * Palette regs
  996. */
  997. #define _PALETTE_A 0x0a000
  998. #define _PALETTE_B 0x0a800
  999. #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
  1000. /* MCH MMIO space */
  1001. /*
  1002. * MCHBAR mirror.
  1003. *
  1004. * This mirrors the MCHBAR MMIO space whose location is determined by
  1005. * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
  1006. * every way. It is not accessible from the CP register read instructions.
  1007. *
  1008. */
  1009. #define MCHBAR_MIRROR_BASE 0x10000
  1010. #define MCHBAR_MIRROR_BASE_SNB 0x140000
  1011. /** 915-945 and GM965 MCH register controlling DRAM channel access */
  1012. #define DCC 0x10200
  1013. #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
  1014. #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
  1015. #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
  1016. #define DCC_ADDRESSING_MODE_MASK (3 << 0)
  1017. #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
  1018. #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
  1019. /** Pineview MCH register contains DDR3 setting */
  1020. #define CSHRDDR3CTL 0x101a8
  1021. #define CSHRDDR3CTL_DDR3 (1 << 2)
  1022. /** 965 MCH register controlling DRAM channel configuration */
  1023. #define C0DRB3 0x10206
  1024. #define C1DRB3 0x10606
  1025. /** snb MCH registers for reading the DRAM channel configuration */
  1026. #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
  1027. #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
  1028. #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
  1029. #define MAD_DIMM_ECC_MASK (0x3 << 24)
  1030. #define MAD_DIMM_ECC_OFF (0x0 << 24)
  1031. #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
  1032. #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
  1033. #define MAD_DIMM_ECC_ON (0x3 << 24)
  1034. #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
  1035. #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
  1036. #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
  1037. #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
  1038. #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
  1039. #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
  1040. #define MAD_DIMM_A_SELECT (0x1 << 16)
  1041. /* DIMM sizes are in multiples of 256mb. */
  1042. #define MAD_DIMM_B_SIZE_SHIFT 8
  1043. #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
  1044. #define MAD_DIMM_A_SIZE_SHIFT 0
  1045. #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
  1046. /* Clocking configuration register */
  1047. #define CLKCFG 0x10c00
  1048. #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
  1049. #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
  1050. #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
  1051. #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
  1052. #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
  1053. #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
  1054. /* Note, below two are guess */
  1055. #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
  1056. #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
  1057. #define CLKCFG_FSB_MASK (7 << 0)
  1058. #define CLKCFG_MEM_533 (1 << 4)
  1059. #define CLKCFG_MEM_667 (2 << 4)
  1060. #define CLKCFG_MEM_800 (3 << 4)
  1061. #define CLKCFG_MEM_MASK (7 << 4)
  1062. #define TSC1 0x11001
  1063. #define TSE (1<<0)
  1064. #define TR1 0x11006
  1065. #define TSFS 0x11020
  1066. #define TSFS_SLOPE_MASK 0x0000ff00
  1067. #define TSFS_SLOPE_SHIFT 8
  1068. #define TSFS_INTR_MASK 0x000000ff
  1069. #define CRSTANDVID 0x11100
  1070. #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
  1071. #define PXVFREQ_PX_MASK 0x7f000000
  1072. #define PXVFREQ_PX_SHIFT 24
  1073. #define VIDFREQ_BASE 0x11110
  1074. #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
  1075. #define VIDFREQ2 0x11114
  1076. #define VIDFREQ3 0x11118
  1077. #define VIDFREQ4 0x1111c
  1078. #define VIDFREQ_P0_MASK 0x1f000000
  1079. #define VIDFREQ_P0_SHIFT 24
  1080. #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
  1081. #define VIDFREQ_P0_CSCLK_SHIFT 20
  1082. #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
  1083. #define VIDFREQ_P0_CRCLK_SHIFT 16
  1084. #define VIDFREQ_P1_MASK 0x00001f00
  1085. #define VIDFREQ_P1_SHIFT 8
  1086. #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
  1087. #define VIDFREQ_P1_CSCLK_SHIFT 4
  1088. #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
  1089. #define INTTOEXT_BASE_ILK 0x11300
  1090. #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
  1091. #define INTTOEXT_MAP3_SHIFT 24
  1092. #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
  1093. #define INTTOEXT_MAP2_SHIFT 16
  1094. #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
  1095. #define INTTOEXT_MAP1_SHIFT 8
  1096. #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
  1097. #define INTTOEXT_MAP0_SHIFT 0
  1098. #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
  1099. #define MEMSWCTL 0x11170 /* Ironlake only */
  1100. #define MEMCTL_CMD_MASK 0xe000
  1101. #define MEMCTL_CMD_SHIFT 13
  1102. #define MEMCTL_CMD_RCLK_OFF 0
  1103. #define MEMCTL_CMD_RCLK_ON 1
  1104. #define MEMCTL_CMD_CHFREQ 2
  1105. #define MEMCTL_CMD_CHVID 3
  1106. #define MEMCTL_CMD_VMMOFF 4
  1107. #define MEMCTL_CMD_VMMON 5
  1108. #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
  1109. when command complete */
  1110. #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
  1111. #define MEMCTL_FREQ_SHIFT 8
  1112. #define MEMCTL_SFCAVM (1<<7)
  1113. #define MEMCTL_TGT_VID_MASK 0x007f
  1114. #define MEMIHYST 0x1117c
  1115. #define MEMINTREN 0x11180 /* 16 bits */
  1116. #define MEMINT_RSEXIT_EN (1<<8)
  1117. #define MEMINT_CX_SUPR_EN (1<<7)
  1118. #define MEMINT_CONT_BUSY_EN (1<<6)
  1119. #define MEMINT_AVG_BUSY_EN (1<<5)
  1120. #define MEMINT_EVAL_CHG_EN (1<<4)
  1121. #define MEMINT_MON_IDLE_EN (1<<3)
  1122. #define MEMINT_UP_EVAL_EN (1<<2)
  1123. #define MEMINT_DOWN_EVAL_EN (1<<1)
  1124. #define MEMINT_SW_CMD_EN (1<<0)
  1125. #define MEMINTRSTR 0x11182 /* 16 bits */
  1126. #define MEM_RSEXIT_MASK 0xc000
  1127. #define MEM_RSEXIT_SHIFT 14
  1128. #define MEM_CONT_BUSY_MASK 0x3000
  1129. #define MEM_CONT_BUSY_SHIFT 12
  1130. #define MEM_AVG_BUSY_MASK 0x0c00
  1131. #define MEM_AVG_BUSY_SHIFT 10
  1132. #define MEM_EVAL_CHG_MASK 0x0300
  1133. #define MEM_EVAL_BUSY_SHIFT 8
  1134. #define MEM_MON_IDLE_MASK 0x00c0
  1135. #define MEM_MON_IDLE_SHIFT 6
  1136. #define MEM_UP_EVAL_MASK 0x0030
  1137. #define MEM_UP_EVAL_SHIFT 4
  1138. #define MEM_DOWN_EVAL_MASK 0x000c
  1139. #define MEM_DOWN_EVAL_SHIFT 2
  1140. #define MEM_SW_CMD_MASK 0x0003
  1141. #define MEM_INT_STEER_GFX 0
  1142. #define MEM_INT_STEER_CMR 1
  1143. #define MEM_INT_STEER_SMI 2
  1144. #define MEM_INT_STEER_SCI 3
  1145. #define MEMINTRSTS 0x11184
  1146. #define MEMINT_RSEXIT (1<<7)
  1147. #define MEMINT_CONT_BUSY (1<<6)
  1148. #define MEMINT_AVG_BUSY (1<<5)
  1149. #define MEMINT_EVAL_CHG (1<<4)
  1150. #define MEMINT_MON_IDLE (1<<3)
  1151. #define MEMINT_UP_EVAL (1<<2)
  1152. #define MEMINT_DOWN_EVAL (1<<1)
  1153. #define MEMINT_SW_CMD (1<<0)
  1154. #define MEMMODECTL 0x11190
  1155. #define MEMMODE_BOOST_EN (1<<31)
  1156. #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
  1157. #define MEMMODE_BOOST_FREQ_SHIFT 24
  1158. #define MEMMODE_IDLE_MODE_MASK 0x00030000
  1159. #define MEMMODE_IDLE_MODE_SHIFT 16
  1160. #define MEMMODE_IDLE_MODE_EVAL 0
  1161. #define MEMMODE_IDLE_MODE_CONT 1
  1162. #define MEMMODE_HWIDLE_EN (1<<15)
  1163. #define MEMMODE_SWMODE_EN (1<<14)
  1164. #define MEMMODE_RCLK_GATE (1<<13)
  1165. #define MEMMODE_HW_UPDATE (1<<12)
  1166. #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
  1167. #define MEMMODE_FSTART_SHIFT 8
  1168. #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
  1169. #define MEMMODE_FMAX_SHIFT 4
  1170. #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
  1171. #define RCBMAXAVG 0x1119c
  1172. #define MEMSWCTL2 0x1119e /* Cantiga only */
  1173. #define SWMEMCMD_RENDER_OFF (0 << 13)
  1174. #define SWMEMCMD_RENDER_ON (1 << 13)
  1175. #define SWMEMCMD_SWFREQ (2 << 13)
  1176. #define SWMEMCMD_TARVID (3 << 13)
  1177. #define SWMEMCMD_VRM_OFF (4 << 13)
  1178. #define SWMEMCMD_VRM_ON (5 << 13)
  1179. #define CMDSTS (1<<12)
  1180. #define SFCAVM (1<<11)
  1181. #define SWFREQ_MASK 0x0380 /* P0-7 */
  1182. #define SWFREQ_SHIFT 7
  1183. #define TARVID_MASK 0x001f
  1184. #define MEMSTAT_CTG 0x111a0
  1185. #define RCBMINAVG 0x111a0
  1186. #define RCUPEI 0x111b0
  1187. #define RCDNEI 0x111b4
  1188. #define RSTDBYCTL 0x111b8
  1189. #define RS1EN (1<<31)
  1190. #define RS2EN (1<<30)
  1191. #define RS3EN (1<<29)
  1192. #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
  1193. #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
  1194. #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
  1195. #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
  1196. #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
  1197. #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
  1198. #define RSX_STATUS_MASK (7<<20)
  1199. #define RSX_STATUS_ON (0<<20)
  1200. #define RSX_STATUS_RC1 (1<<20)
  1201. #define RSX_STATUS_RC1E (2<<20)
  1202. #define RSX_STATUS_RS1 (3<<20)
  1203. #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
  1204. #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
  1205. #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
  1206. #define RSX_STATUS_RSVD2 (7<<20)
  1207. #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
  1208. #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
  1209. #define JRSC (1<<17) /* rsx coupled to cpu c-state */
  1210. #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
  1211. #define RS1CONTSAV_MASK (3<<14)
  1212. #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
  1213. #define RS1CONTSAV_RSVD (1<<14)
  1214. #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
  1215. #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
  1216. #define NORMSLEXLAT_MASK (3<<12)
  1217. #define SLOW_RS123 (0<<12)
  1218. #define SLOW_RS23 (1<<12)
  1219. #define SLOW_RS3 (2<<12)
  1220. #define NORMAL_RS123 (3<<12)
  1221. #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
  1222. #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
  1223. #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
  1224. #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
  1225. #define RS_CSTATE_MASK (3<<4)
  1226. #define RS_CSTATE_C367_RS1 (0<<4)
  1227. #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
  1228. #define RS_CSTATE_RSVD (2<<4)
  1229. #define RS_CSTATE_C367_RS2 (3<<4)
  1230. #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
  1231. #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
  1232. #define VIDCTL 0x111c0
  1233. #define VIDSTS 0x111c8
  1234. #define VIDSTART 0x111cc /* 8 bits */
  1235. #define MEMSTAT_ILK 0x111f8
  1236. #define MEMSTAT_VID_MASK 0x7f00
  1237. #define MEMSTAT_VID_SHIFT 8
  1238. #define MEMSTAT_PSTATE_MASK 0x00f8
  1239. #define MEMSTAT_PSTATE_SHIFT 3
  1240. #define MEMSTAT_MON_ACTV (1<<2)
  1241. #define MEMSTAT_SRC_CTL_MASK 0x0003
  1242. #define MEMSTAT_SRC_CTL_CORE 0
  1243. #define MEMSTAT_SRC_CTL_TRB 1
  1244. #define MEMSTAT_SRC_CTL_THM 2
  1245. #define MEMSTAT_SRC_CTL_STDBY 3
  1246. #define RCPREVBSYTUPAVG 0x113b8
  1247. #define RCPREVBSYTDNAVG 0x113bc
  1248. #define PMMISC 0x11214
  1249. #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
  1250. #define SDEW 0x1124c
  1251. #define CSIEW0 0x11250
  1252. #define CSIEW1 0x11254
  1253. #define CSIEW2 0x11258
  1254. #define PEW 0x1125c
  1255. #define DEW 0x11270
  1256. #define MCHAFE 0x112c0
  1257. #define CSIEC 0x112e0
  1258. #define DMIEC 0x112e4
  1259. #define DDREC 0x112e8
  1260. #define PEG0EC 0x112ec
  1261. #define PEG1EC 0x112f0
  1262. #define GFXEC 0x112f4
  1263. #define RPPREVBSYTUPAVG 0x113b8
  1264. #define RPPREVBSYTDNAVG 0x113bc
  1265. #define ECR 0x11600
  1266. #define ECR_GPFE (1<<31)
  1267. #define ECR_IMONE (1<<30)
  1268. #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
  1269. #define OGW0 0x11608
  1270. #define OGW1 0x1160c
  1271. #define EG0 0x11610
  1272. #define EG1 0x11614
  1273. #define EG2 0x11618
  1274. #define EG3 0x1161c
  1275. #define EG4 0x11620
  1276. #define EG5 0x11624
  1277. #define EG6 0x11628
  1278. #define EG7 0x1162c
  1279. #define PXW 0x11664
  1280. #define PXWL 0x11680
  1281. #define LCFUSE02 0x116c0
  1282. #define LCFUSE_HIV_MASK 0x000000ff
  1283. #define CSIPLL0 0x12c10
  1284. #define DDRMPLL1 0X12c20
  1285. #define PEG_BAND_GAP_DATA 0x14d68
  1286. #define GEN6_GT_PERF_STATUS 0x145948
  1287. #define GEN6_RP_STATE_LIMITS 0x145994
  1288. #define GEN6_RP_STATE_CAP 0x145998
  1289. /*
  1290. * Logical Context regs
  1291. */
  1292. #define CCID 0x2180
  1293. #define CCID_EN (1<<0)
  1294. /*
  1295. * Overlay regs
  1296. */
  1297. #define OVADD 0x30000
  1298. #define DOVSTA 0x30008
  1299. #define OC_BUF (0x3<<20)
  1300. #define OGAMC5 0x30010
  1301. #define OGAMC4 0x30014
  1302. #define OGAMC3 0x30018
  1303. #define OGAMC2 0x3001c
  1304. #define OGAMC1 0x30020
  1305. #define OGAMC0 0x30024
  1306. /*
  1307. * Display engine regs
  1308. */
  1309. /* Pipe A timing regs */
  1310. #define _HTOTAL_A 0x60000
  1311. #define _HBLANK_A 0x60004
  1312. #define _HSYNC_A 0x60008
  1313. #define _VTOTAL_A 0x6000c
  1314. #define _VBLANK_A 0x60010
  1315. #define _VSYNC_A 0x60014
  1316. #define _PIPEASRC 0x6001c
  1317. #define _BCLRPAT_A 0x60020
  1318. #define _VSYNCSHIFT_A 0x60028
  1319. /* Pipe B timing regs */
  1320. #define _HTOTAL_B 0x61000
  1321. #define _HBLANK_B 0x61004
  1322. #define _HSYNC_B 0x61008
  1323. #define _VTOTAL_B 0x6100c
  1324. #define _VBLANK_B 0x61010
  1325. #define _VSYNC_B 0x61014
  1326. #define _PIPEBSRC 0x6101c
  1327. #define _BCLRPAT_B 0x61020
  1328. #define _VSYNCSHIFT_B 0x61028
  1329. #define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
  1330. #define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
  1331. #define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
  1332. #define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
  1333. #define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
  1334. #define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
  1335. #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
  1336. #define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
  1337. /* VGA port control */
  1338. #define ADPA 0x61100
  1339. #define ADPA_DAC_ENABLE (1<<31)
  1340. #define ADPA_DAC_DISABLE 0
  1341. #define ADPA_PIPE_SELECT_MASK (1<<30)
  1342. #define ADPA_PIPE_A_SELECT 0
  1343. #define ADPA_PIPE_B_SELECT (1<<30)
  1344. #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
  1345. #define ADPA_USE_VGA_HVPOLARITY (1<<15)
  1346. #define ADPA_SETS_HVPOLARITY 0
  1347. #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
  1348. #define ADPA_VSYNC_CNTL_ENABLE 0
  1349. #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
  1350. #define ADPA_HSYNC_CNTL_ENABLE 0
  1351. #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
  1352. #define ADPA_VSYNC_ACTIVE_LOW 0
  1353. #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
  1354. #define ADPA_HSYNC_ACTIVE_LOW 0
  1355. #define ADPA_DPMS_MASK (~(3<<10))
  1356. #define ADPA_DPMS_ON (0<<10)
  1357. #define ADPA_DPMS_SUSPEND (1<<10)
  1358. #define ADPA_DPMS_STANDBY (2<<10)
  1359. #define ADPA_DPMS_OFF (3<<10)
  1360. /* Hotplug control (945+ only) */
  1361. #define PORT_HOTPLUG_EN 0x61110
  1362. #define HDMIB_HOTPLUG_INT_EN (1 << 29)
  1363. #define DPB_HOTPLUG_INT_EN (1 << 29)
  1364. #define HDMIC_HOTPLUG_INT_EN (1 << 28)
  1365. #define DPC_HOTPLUG_INT_EN (1 << 28)
  1366. #define HDMID_HOTPLUG_INT_EN (1 << 27)
  1367. #define DPD_HOTPLUG_INT_EN (1 << 27)
  1368. #define SDVOB_HOTPLUG_INT_EN (1 << 26)
  1369. #define SDVOC_HOTPLUG_INT_EN (1 << 25)
  1370. #define TV_HOTPLUG_INT_EN (1 << 18)
  1371. #define CRT_HOTPLUG_INT_EN (1 << 9)
  1372. #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
  1373. #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
  1374. /* must use period 64 on GM45 according to docs */
  1375. #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
  1376. #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
  1377. #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
  1378. #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
  1379. #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
  1380. #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
  1381. #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
  1382. #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
  1383. #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
  1384. #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
  1385. #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
  1386. #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
  1387. #define PORT_HOTPLUG_STAT 0x61114
  1388. #define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
  1389. #define DPB_HOTPLUG_INT_STATUS (1 << 29)
  1390. #define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
  1391. #define DPC_HOTPLUG_INT_STATUS (1 << 28)
  1392. #define HDMID_HOTPLUG_INT_STATUS (1 << 27)
  1393. #define DPD_HOTPLUG_INT_STATUS (1 << 27)
  1394. /* CRT/TV common between gen3+ */
  1395. #define CRT_HOTPLUG_INT_STATUS (1 << 11)
  1396. #define TV_HOTPLUG_INT_STATUS (1 << 10)
  1397. #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
  1398. #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
  1399. #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
  1400. #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
  1401. /* SDVO is different across gen3/4 */
  1402. #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
  1403. #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
  1404. #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
  1405. #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
  1406. #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
  1407. #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
  1408. /* SDVO port control */
  1409. #define SDVOB 0x61140
  1410. #define SDVOC 0x61160
  1411. #define SDVO_ENABLE (1 << 31)
  1412. #define SDVO_PIPE_B_SELECT (1 << 30)
  1413. #define SDVO_STALL_SELECT (1 << 29)
  1414. #define SDVO_INTERRUPT_ENABLE (1 << 26)
  1415. /**
  1416. * 915G/GM SDVO pixel multiplier.
  1417. *
  1418. * Programmed value is multiplier - 1, up to 5x.
  1419. *
  1420. * \sa DPLL_MD_UDI_MULTIPLIER_MASK
  1421. */
  1422. #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
  1423. #define SDVO_PORT_MULTIPLY_SHIFT 23
  1424. #define SDVO_PHASE_SELECT_MASK (15 << 19)
  1425. #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
  1426. #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
  1427. #define SDVOC_GANG_MODE (1 << 16)
  1428. #define SDVO_ENCODING_SDVO (0x0 << 10)
  1429. #define SDVO_ENCODING_HDMI (0x2 << 10)
  1430. /** Requird for HDMI operation */
  1431. #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
  1432. #define SDVO_COLOR_RANGE_16_235 (1 << 8)
  1433. #define SDVO_BORDER_ENABLE (1 << 7)
  1434. #define SDVO_AUDIO_ENABLE (1 << 6)
  1435. /** New with 965, default is to be set */
  1436. #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
  1437. /** New with 965, default is to be set */
  1438. #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
  1439. #define SDVOB_PCIE_CONCURRENCY (1 << 3)
  1440. #define SDVO_DETECTED (1 << 2)
  1441. /* Bits to be preserved when writing */
  1442. #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
  1443. #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
  1444. /* DVO port control */
  1445. #define DVOA 0x61120
  1446. #define DVOB 0x61140
  1447. #define DVOC 0x61160
  1448. #define DVO_ENABLE (1 << 31)
  1449. #define DVO_PIPE_B_SELECT (1 << 30)
  1450. #define DVO_PIPE_STALL_UNUSED (0 << 28)
  1451. #define DVO_PIPE_STALL (1 << 28)
  1452. #define DVO_PIPE_STALL_TV (2 << 28)
  1453. #define DVO_PIPE_STALL_MASK (3 << 28)
  1454. #define DVO_USE_VGA_SYNC (1 << 15)
  1455. #define DVO_DATA_ORDER_I740 (0 << 14)
  1456. #define DVO_DATA_ORDER_FP (1 << 14)
  1457. #define DVO_VSYNC_DISABLE (1 << 11)
  1458. #define DVO_HSYNC_DISABLE (1 << 10)
  1459. #define DVO_VSYNC_TRISTATE (1 << 9)
  1460. #define DVO_HSYNC_TRISTATE (1 << 8)
  1461. #define DVO_BORDER_ENABLE (1 << 7)
  1462. #define DVO_DATA_ORDER_GBRG (1 << 6)
  1463. #define DVO_DATA_ORDER_RGGB (0 << 6)
  1464. #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
  1465. #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
  1466. #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
  1467. #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
  1468. #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
  1469. #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
  1470. #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
  1471. #define DVO_PRESERVE_MASK (0x7<<24)
  1472. #define DVOA_SRCDIM 0x61124
  1473. #define DVOB_SRCDIM 0x61144
  1474. #define DVOC_SRCDIM 0x61164
  1475. #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
  1476. #define DVO_SRCDIM_VERTICAL_SHIFT 0
  1477. /* LVDS port control */
  1478. #define LVDS 0x61180
  1479. /*
  1480. * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
  1481. * the DPLL semantics change when the LVDS is assigned to that pipe.
  1482. */
  1483. #define LVDS_PORT_EN (1 << 31)
  1484. /* Selects pipe B for LVDS data. Must be set on pre-965. */
  1485. #define LVDS_PIPEB_SELECT (1 << 30)
  1486. #define LVDS_PIPE_MASK (1 << 30)
  1487. #define LVDS_PIPE(pipe) ((pipe) << 30)
  1488. /* LVDS dithering flag on 965/g4x platform */
  1489. #define LVDS_ENABLE_DITHER (1 << 25)
  1490. /* LVDS sync polarity flags. Set to invert (i.e. negative) */
  1491. #define LVDS_VSYNC_POLARITY (1 << 21)
  1492. #define LVDS_HSYNC_POLARITY (1 << 20)
  1493. /* Enable border for unscaled (or aspect-scaled) display */
  1494. #define LVDS_BORDER_ENABLE (1 << 15)
  1495. /*
  1496. * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
  1497. * pixel.
  1498. */
  1499. #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
  1500. #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
  1501. #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
  1502. /*
  1503. * Controls the A3 data pair, which contains the additional LSBs for 24 bit
  1504. * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
  1505. * on.
  1506. */
  1507. #define LVDS_A3_POWER_MASK (3 << 6)
  1508. #define LVDS_A3_POWER_DOWN (0 << 6)
  1509. #define LVDS_A3_POWER_UP (3 << 6)
  1510. /*
  1511. * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
  1512. * is set.
  1513. */
  1514. #define LVDS_CLKB_POWER_MASK (3 << 4)
  1515. #define LVDS_CLKB_POWER_DOWN (0 << 4)
  1516. #define LVDS_CLKB_POWER_UP (3 << 4)
  1517. /*
  1518. * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
  1519. * setting for whether we are in dual-channel mode. The B3 pair will
  1520. * additionally only be powered up when LVDS_A3_POWER_UP is set.
  1521. */
  1522. #define LVDS_B0B3_POWER_MASK (3 << 2)
  1523. #define LVDS_B0B3_POWER_DOWN (0 << 2)
  1524. #define LVDS_B0B3_POWER_UP (3 << 2)
  1525. /* Video Data Island Packet control */
  1526. #define VIDEO_DIP_DATA 0x61178
  1527. #define VIDEO_DIP_CTL 0x61170
  1528. #define VIDEO_DIP_ENABLE (1 << 31)
  1529. #define VIDEO_DIP_PORT_B (1 << 29)
  1530. #define VIDEO_DIP_PORT_C (2 << 29)
  1531. #define VIDEO_DIP_ENABLE_AVI (1 << 21)
  1532. #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
  1533. #define VIDEO_DIP_ENABLE_SPD (8 << 21)
  1534. #define VIDEO_DIP_SELECT_AVI (0 << 19)
  1535. #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
  1536. #define VIDEO_DIP_SELECT_SPD (3 << 19)
  1537. #define VIDEO_DIP_SELECT_MASK (3 << 19)
  1538. #define VIDEO_DIP_FREQ_ONCE (0 << 16)
  1539. #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
  1540. #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
  1541. /* Panel power sequencing */
  1542. #define PP_STATUS 0x61200
  1543. #define PP_ON (1 << 31)
  1544. /*
  1545. * Indicates that all dependencies of the panel are on:
  1546. *
  1547. * - PLL enabled
  1548. * - pipe enabled
  1549. * - LVDS/DVOB/DVOC on
  1550. */
  1551. #define PP_READY (1 << 30)
  1552. #define PP_SEQUENCE_NONE (0 << 28)
  1553. #define PP_SEQUENCE_POWER_UP (1 << 28)
  1554. #define PP_SEQUENCE_POWER_DOWN (2 << 28)
  1555. #define PP_SEQUENCE_MASK (3 << 28)
  1556. #define PP_SEQUENCE_SHIFT 28
  1557. #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
  1558. #define PP_SEQUENCE_STATE_MASK 0x0000000f
  1559. #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
  1560. #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
  1561. #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
  1562. #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
  1563. #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
  1564. #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
  1565. #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
  1566. #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
  1567. #define PP_SEQUENCE_STATE_RESET (0xf << 0)
  1568. #define PP_CONTROL 0x61204
  1569. #define POWER_TARGET_ON (1 << 0)
  1570. #define PP_ON_DELAYS 0x61208
  1571. #define PP_OFF_DELAYS 0x6120c
  1572. #define PP_DIVISOR 0x61210
  1573. /* Panel fitting */
  1574. #define PFIT_CONTROL 0x61230
  1575. #define PFIT_ENABLE (1 << 31)
  1576. #define PFIT_PIPE_MASK (3 << 29)
  1577. #define PFIT_PIPE_SHIFT 29
  1578. #define VERT_INTERP_DISABLE (0 << 10)
  1579. #define VERT_INTERP_BILINEAR (1 << 10)
  1580. #define VERT_INTERP_MASK (3 << 10)
  1581. #define VERT_AUTO_SCALE (1 << 9)
  1582. #define HORIZ_INTERP_DISABLE (0 << 6)
  1583. #define HORIZ_INTERP_BILINEAR (1 << 6)
  1584. #define HORIZ_INTERP_MASK (3 << 6)
  1585. #define HORIZ_AUTO_SCALE (1 << 5)
  1586. #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
  1587. #define PFIT_FILTER_FUZZY (0 << 24)
  1588. #define PFIT_SCALING_AUTO (0 << 26)
  1589. #define PFIT_SCALING_PROGRAMMED (1 << 26)
  1590. #define PFIT_SCALING_PILLAR (2 << 26)
  1591. #define PFIT_SCALING_LETTER (3 << 26)
  1592. #define PFIT_PGM_RATIOS 0x61234
  1593. #define PFIT_VERT_SCALE_MASK 0xfff00000
  1594. #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
  1595. /* Pre-965 */
  1596. #define PFIT_VERT_SCALE_SHIFT 20
  1597. #define PFIT_VERT_SCALE_MASK 0xfff00000
  1598. #define PFIT_HORIZ_SCALE_SHIFT 4
  1599. #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
  1600. /* 965+ */
  1601. #define PFIT_VERT_SCALE_SHIFT_965 16
  1602. #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
  1603. #define PFIT_HORIZ_SCALE_SHIFT_965 0
  1604. #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
  1605. #define PFIT_AUTO_RATIOS 0x61238
  1606. /* Backlight control */
  1607. #define BLC_PWM_CTL 0x61254
  1608. #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
  1609. #define BLC_PWM_CTL2 0x61250 /* 965+ only */
  1610. #define BLM_COMBINATION_MODE (1 << 30)
  1611. /*
  1612. * This is the most significant 15 bits of the number of backlight cycles in a
  1613. * complete cycle of the modulated backlight control.
  1614. *
  1615. * The actual value is this field multiplied by two.
  1616. */
  1617. #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
  1618. #define BLM_LEGACY_MODE (1 << 16)
  1619. /*
  1620. * This is the number of cycles out of the backlight modulation cycle for which
  1621. * the backlight is on.
  1622. *
  1623. * This field must be no greater than the number of cycles in the complete
  1624. * backlight modulation cycle.
  1625. */
  1626. #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
  1627. #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
  1628. #define BLC_HIST_CTL 0x61260
  1629. /* TV port control */
  1630. #define TV_CTL 0x68000
  1631. /** Enables the TV encoder */
  1632. # define TV_ENC_ENABLE (1 << 31)
  1633. /** Sources the TV encoder input from pipe B instead of A. */
  1634. # define TV_ENC_PIPEB_SELECT (1 << 30)
  1635. /** Outputs composite video (DAC A only) */
  1636. # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
  1637. /** Outputs SVideo video (DAC B/C) */
  1638. # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
  1639. /** Outputs Component video (DAC A/B/C) */
  1640. # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
  1641. /** Outputs Composite and SVideo (DAC A/B/C) */
  1642. # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
  1643. # define TV_TRILEVEL_SYNC (1 << 21)
  1644. /** Enables slow sync generation (945GM only) */
  1645. # define TV_SLOW_SYNC (1 << 20)
  1646. /** Selects 4x oversampling for 480i and 576p */
  1647. # define TV_OVERSAMPLE_4X (0 << 18)
  1648. /** Selects 2x oversampling for 720p and 1080i */
  1649. # define TV_OVERSAMPLE_2X (1 << 18)
  1650. /** Selects no oversampling for 1080p */
  1651. # define TV_OVERSAMPLE_NONE (2 << 18)
  1652. /** Selects 8x oversampling */
  1653. # define TV_OVERSAMPLE_8X (3 << 18)
  1654. /** Selects progressive mode rather than interlaced */
  1655. # define TV_PROGRESSIVE (1 << 17)
  1656. /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
  1657. # define TV_PAL_BURST (1 << 16)
  1658. /** Field for setting delay of Y compared to C */
  1659. # define TV_YC_SKEW_MASK (7 << 12)
  1660. /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
  1661. # define TV_ENC_SDP_FIX (1 << 11)
  1662. /**
  1663. * Enables a fix for the 915GM only.
  1664. *
  1665. * Not sure what it does.
  1666. */
  1667. # define TV_ENC_C0_FIX (1 << 10)
  1668. /** Bits that must be preserved by software */
  1669. # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
  1670. # define TV_FUSE_STATE_MASK (3 << 4)
  1671. /** Read-only state that reports all features enabled */
  1672. # define TV_FUSE_STATE_ENABLED (0 << 4)
  1673. /** Read-only state that reports that Macrovision is disabled in hardware*/
  1674. # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
  1675. /** Read-only state that reports that TV-out is disabled in hardware. */
  1676. # define TV_FUSE_STATE_DISABLED (2 << 4)
  1677. /** Normal operation */
  1678. # define TV_TEST_MODE_NORMAL (0 << 0)
  1679. /** Encoder test pattern 1 - combo pattern */
  1680. # define TV_TEST_MODE_PATTERN_1 (1 << 0)
  1681. /** Encoder test pattern 2 - full screen vertical 75% color bars */
  1682. # define TV_TEST_MODE_PATTERN_2 (2 << 0)
  1683. /** Encoder test pattern 3 - full screen horizontal 75% color bars */
  1684. # define TV_TEST_MODE_PATTERN_3 (3 << 0)
  1685. /** Encoder test pattern 4 - random noise */
  1686. # define TV_TEST_MODE_PATTERN_4 (4 << 0)
  1687. /** Encoder test pattern 5 - linear color ramps */
  1688. # define TV_TEST_MODE_PATTERN_5 (5 << 0)
  1689. /**
  1690. * This test mode forces the DACs to 50% of full output.
  1691. *
  1692. * This is used for load detection in combination with TVDAC_SENSE_MASK
  1693. */
  1694. # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
  1695. # define TV_TEST_MODE_MASK (7 << 0)
  1696. #define TV_DAC 0x68004
  1697. # define TV_DAC_SAVE 0x00ffff00
  1698. /**
  1699. * Reports that DAC state change logic has reported change (RO).
  1700. *
  1701. * This gets cleared when TV_DAC_STATE_EN is cleared
  1702. */
  1703. # define TVDAC_STATE_CHG (1 << 31)
  1704. # define TVDAC_SENSE_MASK (7 << 28)
  1705. /** Reports that DAC A voltage is above the detect threshold */
  1706. # define TVDAC_A_SENSE (1 << 30)
  1707. /** Reports that DAC B voltage is above the detect threshold */
  1708. # define TVDAC_B_SENSE (1 << 29)
  1709. /** Reports that DAC C voltage is above the detect threshold */
  1710. # define TVDAC_C_SENSE (1 << 28)
  1711. /**
  1712. * Enables DAC state detection logic, for load-based TV detection.
  1713. *
  1714. * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
  1715. * to off, for load detection to work.
  1716. */
  1717. # define TVDAC_STATE_CHG_EN (1 << 27)
  1718. /** Sets the DAC A sense value to high */
  1719. # define TVDAC_A_SENSE_CTL (1 << 26)
  1720. /** Sets the DAC B sense value to high */
  1721. # define TVDAC_B_SENSE_CTL (1 << 25)
  1722. /** Sets the DAC C sense value to high */
  1723. # define TVDAC_C_SENSE_CTL (1 << 24)
  1724. /** Overrides the ENC_ENABLE and DAC voltage levels */
  1725. # define DAC_CTL_OVERRIDE (1 << 7)
  1726. /** Sets the slew rate. Must be preserved in software */
  1727. # define ENC_TVDAC_SLEW_FAST (1 << 6)
  1728. # define DAC_A_1_3_V (0 << 4)
  1729. # define DAC_A_1_1_V (1 << 4)
  1730. # define DAC_A_0_7_V (2 << 4)
  1731. # define DAC_A_MASK (3 << 4)
  1732. # define DAC_B_1_3_V (0 << 2)
  1733. # define DAC_B_1_1_V (1 << 2)
  1734. # define DAC_B_0_7_V (2 << 2)
  1735. # define DAC_B_MASK (3 << 2)
  1736. # define DAC_C_1_3_V (0 << 0)
  1737. # define DAC_C_1_1_V (1 << 0)
  1738. # define DAC_C_0_7_V (2 << 0)
  1739. # define DAC_C_MASK (3 << 0)
  1740. /**
  1741. * CSC coefficients are stored in a floating point format with 9 bits of
  1742. * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
  1743. * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
  1744. * -1 (0x3) being the only legal negative value.
  1745. */
  1746. #define TV_CSC_Y 0x68010
  1747. # define TV_RY_MASK 0x07ff0000
  1748. # define TV_RY_SHIFT 16
  1749. # define TV_GY_MASK 0x00000fff
  1750. # define TV_GY_SHIFT 0
  1751. #define TV_CSC_Y2 0x68014
  1752. # define TV_BY_MASK 0x07ff0000
  1753. # define TV_BY_SHIFT 16
  1754. /**
  1755. * Y attenuation for component video.
  1756. *
  1757. * Stored in 1.9 fixed point.
  1758. */
  1759. # define TV_AY_MASK 0x000003ff
  1760. # define TV_AY_SHIFT 0
  1761. #define TV_CSC_U 0x68018
  1762. # define TV_RU_MASK 0x07ff0000
  1763. # define TV_RU_SHIFT 16
  1764. # define TV_GU_MASK 0x000007ff
  1765. # define TV_GU_SHIFT 0
  1766. #define TV_CSC_U2 0x6801c
  1767. # define TV_BU_MASK 0x07ff0000
  1768. # define TV_BU_SHIFT 16
  1769. /**
  1770. * U attenuation for component video.
  1771. *
  1772. * Stored in 1.9 fixed point.
  1773. */
  1774. # define TV_AU_MASK 0x000003ff
  1775. # define TV_AU_SHIFT 0
  1776. #define TV_CSC_V 0x68020
  1777. # define TV_RV_MASK 0x0fff0000
  1778. # define TV_RV_SHIFT 16
  1779. # define TV_GV_MASK 0x000007ff
  1780. # define TV_GV_SHIFT 0
  1781. #define TV_CSC_V2 0x68024
  1782. # define TV_BV_MASK 0x07ff0000
  1783. # define TV_BV_SHIFT 16
  1784. /**
  1785. * V attenuation for component video.
  1786. *
  1787. * Stored in 1.9 fixed point.
  1788. */
  1789. # define TV_AV_MASK 0x000007ff
  1790. # define TV_AV_SHIFT 0
  1791. #define TV_CLR_KNOBS 0x68028
  1792. /** 2s-complement brightness adjustment */
  1793. # define TV_BRIGHTNESS_MASK 0xff000000
  1794. # define TV_BRIGHTNESS_SHIFT 24
  1795. /** Contrast adjustment, as a 2.6 unsigned floating point number */
  1796. # define TV_CONTRAST_MASK 0x00ff0000
  1797. # define TV_CONTRAST_SHIFT 16
  1798. /** Saturation adjustment, as a 2.6 unsigned floating point number */
  1799. # define TV_SATURATION_MASK 0x0000ff00
  1800. # define TV_SATURATION_SHIFT 8
  1801. /** Hue adjustment, as an integer phase angle in degrees */
  1802. # define TV_HUE_MASK 0x000000ff
  1803. # define TV_HUE_SHIFT 0
  1804. #define TV_CLR_LEVEL 0x6802c
  1805. /** Controls the DAC level for black */
  1806. # define TV_BLACK_LEVEL_MASK 0x01ff0000
  1807. # define TV_BLACK_LEVEL_SHIFT 16
  1808. /** Controls the DAC level for blanking */
  1809. # define TV_BLANK_LEVEL_MASK 0x000001ff
  1810. # define TV_BLANK_LEVEL_SHIFT 0
  1811. #define TV_H_CTL_1 0x68030
  1812. /** Number of pixels in the hsync. */
  1813. # define TV_HSYNC_END_MASK 0x1fff0000
  1814. # define TV_HSYNC_END_SHIFT 16
  1815. /** Total number of pixels minus one in the line (display and blanking). */
  1816. # define TV_HTOTAL_MASK 0x00001fff
  1817. # define TV_HTOTAL_SHIFT 0
  1818. #define TV_H_CTL_2 0x68034
  1819. /** Enables the colorburst (needed for non-component color) */
  1820. # define TV_BURST_ENA (1 << 31)
  1821. /** Offset of the colorburst from the start of hsync, in pixels minus one. */
  1822. # define TV_HBURST_START_SHIFT 16
  1823. # define TV_HBURST_START_MASK 0x1fff0000
  1824. /** Length of the colorburst */
  1825. # define TV_HBURST_LEN_SHIFT 0
  1826. # define TV_HBURST_LEN_MASK 0x0001fff
  1827. #define TV_H_CTL_3 0x68038
  1828. /** End of hblank, measured in pixels minus one from start of hsync */
  1829. # define TV_HBLANK_END_SHIFT 16
  1830. # define TV_HBLANK_END_MASK 0x1fff0000
  1831. /** Start of hblank, measured in pixels minus one from start of hsync */
  1832. # define TV_HBLANK_START_SHIFT 0
  1833. # define TV_HBLANK_START_MASK 0x0001fff
  1834. #define TV_V_CTL_1 0x6803c
  1835. /** XXX */
  1836. # define TV_NBR_END_SHIFT 16
  1837. # define TV_NBR_END_MASK 0x07ff0000
  1838. /** XXX */
  1839. # define TV_VI_END_F1_SHIFT 8
  1840. # define TV_VI_END_F1_MASK 0x00003f00
  1841. /** XXX */
  1842. # define TV_VI_END_F2_SHIFT 0
  1843. # define TV_VI_END_F2_MASK 0x0000003f
  1844. #define TV_V_CTL_2 0x68040
  1845. /** Length of vsync, in half lines */
  1846. # define TV_VSYNC_LEN_MASK 0x07ff0000
  1847. # define TV_VSYNC_LEN_SHIFT 16
  1848. /** Offset of the start of vsync in field 1, measured in one less than the
  1849. * number of half lines.
  1850. */
  1851. # define TV_VSYNC_START_F1_MASK 0x00007f00
  1852. # define TV_VSYNC_START_F1_SHIFT 8
  1853. /**
  1854. * Offset of the start of vsync in field 2, measured in one less than the
  1855. * number of half lines.
  1856. */
  1857. # define TV_VSYNC_START_F2_MASK 0x0000007f
  1858. # define TV_VSYNC_START_F2_SHIFT 0
  1859. #define TV_V_CTL_3 0x68044
  1860. /** Enables generation of the equalization signal */
  1861. # define TV_EQUAL_ENA (1 << 31)
  1862. /** Length of vsync, in half lines */
  1863. # define TV_VEQ_LEN_MASK 0x007f0000
  1864. # define TV_VEQ_LEN_SHIFT 16
  1865. /** Offset of the start of equalization in field 1, measured in one less than
  1866. * the number of half lines.
  1867. */
  1868. # define TV_VEQ_START_F1_MASK 0x0007f00
  1869. # define TV_VEQ_START_F1_SHIFT 8
  1870. /**
  1871. * Offset of the start of equalization in field 2, measured in one less than
  1872. * the number of half lines.
  1873. */
  1874. # define TV_VEQ_START_F2_MASK 0x000007f
  1875. # define TV_VEQ_START_F2_SHIFT 0
  1876. #define TV_V_CTL_4 0x68048
  1877. /**
  1878. * Offset to start of vertical colorburst, measured in one less than the
  1879. * number of lines from vertical start.
  1880. */
  1881. # define TV_VBURST_START_F1_MASK 0x003f0000
  1882. # define TV_VBURST_START_F1_SHIFT 16
  1883. /**
  1884. * Offset to the end of vertical colorburst, measured in one less than the
  1885. * number of lines from the start of NBR.
  1886. */
  1887. # define TV_VBURST_END_F1_MASK 0x000000ff
  1888. # define TV_VBURST_END_F1_SHIFT 0
  1889. #define TV_V_CTL_5 0x6804c
  1890. /**
  1891. * Offset to start of vertical colorburst, measured in one less than the
  1892. * number of lines from vertical start.
  1893. */
  1894. # define TV_VBURST_START_F2_MASK 0x003f0000
  1895. # define TV_VBURST_START_F2_SHIFT 16
  1896. /**
  1897. * Offset to the end of vertical colorburst, measured in one less than the
  1898. * number of lines from the start of NBR.
  1899. */
  1900. # define TV_VBURST_END_F2_MASK 0x000000ff
  1901. # define TV_VBURST_END_F2_SHIFT 0
  1902. #define TV_V_CTL_6 0x68050
  1903. /**
  1904. * Offset to start of vertical colorburst, measured in one less than the
  1905. * number of lines from vertical start.
  1906. */
  1907. # define TV_VBURST_START_F3_MASK 0x003f0000
  1908. # define TV_VBURST_START_F3_SHIFT 16
  1909. /**
  1910. * Offset to the end of vertical colorburst, measured in one less than the
  1911. * number of lines from the start of NBR.
  1912. */
  1913. # define TV_VBURST_END_F3_MASK 0x000000ff
  1914. # define TV_VBURST_END_F3_SHIFT 0
  1915. #define TV_V_CTL_7 0x68054
  1916. /**
  1917. * Offset to start of vertical colorburst, measured in one less than the
  1918. * number of lines from vertical start.
  1919. */
  1920. # define TV_VBURST_START_F4_MASK 0x003f0000
  1921. # define TV_VBURST_START_F4_SHIFT 16
  1922. /**
  1923. * Offset to the end of vertical colorburst, measured in one less than the
  1924. * number of lines from the start of NBR.
  1925. */
  1926. # define TV_VBURST_END_F4_MASK 0x000000ff
  1927. # define TV_VBURST_END_F4_SHIFT 0
  1928. #define TV_SC_CTL_1 0x68060
  1929. /** Turns on the first subcarrier phase generation DDA */
  1930. # define TV_SC_DDA1_EN (1 << 31)
  1931. /** Turns on the first subcarrier phase generation DDA */
  1932. # define TV_SC_DDA2_EN (1 << 30)
  1933. /** Turns on the first subcarrier phase generation DDA */
  1934. # define TV_SC_DDA3_EN (1 << 29)
  1935. /** Sets the subcarrier DDA to reset frequency every other field */
  1936. # define TV_SC_RESET_EVERY_2 (0 << 24)
  1937. /** Sets the subcarrier DDA to reset frequency every fourth field */
  1938. # define TV_SC_RESET_EVERY_4 (1 << 24)
  1939. /** Sets the subcarrier DDA to reset frequency every eighth field */
  1940. # define TV_SC_RESET_EVERY_8 (2 << 24)
  1941. /** Sets the subcarrier DDA to never reset the frequency */
  1942. # define TV_SC_RESET_NEVER (3 << 24)
  1943. /** Sets the peak amplitude of the colorburst.*/
  1944. # define TV_BURST_LEVEL_MASK 0x00ff0000
  1945. # define TV_BURST_LEVEL_SHIFT 16
  1946. /** Sets the increment of the first subcarrier phase generation DDA */
  1947. # define TV_SCDDA1_INC_MASK 0x00000fff
  1948. # define TV_SCDDA1_INC_SHIFT 0
  1949. #define TV_SC_CTL_2 0x68064
  1950. /** Sets the rollover for the second subcarrier phase generation DDA */
  1951. # define TV_SCDDA2_SIZE_MASK 0x7fff0000
  1952. # define TV_SCDDA2_SIZE_SHIFT 16
  1953. /** Sets the increent of the second subcarrier phase generation DDA */
  1954. # define TV_SCDDA2_INC_MASK 0x00007fff
  1955. # define TV_SCDDA2_INC_SHIFT 0
  1956. #define TV_SC_CTL_3 0x68068
  1957. /** Sets the rollover for the third subcarrier phase generation DDA */
  1958. # define TV_SCDDA3_SIZE_MASK 0x7fff0000
  1959. # define TV_SCDDA3_SIZE_SHIFT 16
  1960. /** Sets the increent of the third subcarrier phase generation DDA */
  1961. # define TV_SCDDA3_INC_MASK 0x00007fff
  1962. # define TV_SCDDA3_INC_SHIFT 0
  1963. #define TV_WIN_POS 0x68070
  1964. /** X coordinate of the display from the start of horizontal active */
  1965. # define TV_XPOS_MASK 0x1fff0000
  1966. # define TV_XPOS_SHIFT 16
  1967. /** Y coordinate of the display from the start of vertical active (NBR) */
  1968. # define TV_YPOS_MASK 0x00000fff
  1969. # define TV_YPOS_SHIFT 0
  1970. #define TV_WIN_SIZE 0x68074
  1971. /** Horizontal size of the display window, measured in pixels*/
  1972. # define TV_XSIZE_MASK 0x1fff0000
  1973. # define TV_XSIZE_SHIFT 16
  1974. /**
  1975. * Vertical size of the display window, measured in pixels.
  1976. *
  1977. * Must be even for interlaced modes.
  1978. */
  1979. # define TV_YSIZE_MASK 0x00000fff
  1980. # define TV_YSIZE_SHIFT 0
  1981. #define TV_FILTER_CTL_1 0x68080
  1982. /**
  1983. * Enables automatic scaling calculation.
  1984. *
  1985. * If set, the rest of the registers are ignored, and the calculated values can
  1986. * be read back from the register.
  1987. */
  1988. # define TV_AUTO_SCALE (1 << 31)
  1989. /**
  1990. * Disables the vertical filter.
  1991. *
  1992. * This is required on modes more than 1024 pixels wide */
  1993. # define TV_V_FILTER_BYPASS (1 << 29)
  1994. /** Enables adaptive vertical filtering */
  1995. # define TV_VADAPT (1 << 28)
  1996. # define TV_VADAPT_MODE_MASK (3 << 26)
  1997. /** Selects the least adaptive vertical filtering mode */
  1998. # define TV_VADAPT_MODE_LEAST (0 << 26)
  1999. /** Selects the moderately adaptive vertical filtering mode */
  2000. # define TV_VADAPT_MODE_MODERATE (1 << 26)
  2001. /** Selects the most adaptive vertical filtering mode */
  2002. # define TV_VADAPT_MODE_MOST (3 << 26)
  2003. /**
  2004. * Sets the horizontal scaling factor.
  2005. *
  2006. * This should be the fractional part of the horizontal scaling factor divided
  2007. * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
  2008. *
  2009. * (src width - 1) / ((oversample * dest width) - 1)
  2010. */
  2011. # define TV_HSCALE_FRAC_MASK 0x00003fff
  2012. # define TV_HSCALE_FRAC_SHIFT 0
  2013. #define TV_FILTER_CTL_2 0x68084
  2014. /**
  2015. * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
  2016. *
  2017. * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
  2018. */
  2019. # define TV_VSCALE_INT_MASK 0x00038000
  2020. # define TV_VSCALE_INT_SHIFT 15
  2021. /**
  2022. * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
  2023. *
  2024. * \sa TV_VSCALE_INT_MASK
  2025. */
  2026. # define TV_VSCALE_FRAC_MASK 0x00007fff
  2027. # define TV_VSCALE_FRAC_SHIFT 0
  2028. #define TV_FILTER_CTL_3 0x68088
  2029. /**
  2030. * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
  2031. *
  2032. * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
  2033. *
  2034. * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
  2035. */
  2036. # define TV_VSCALE_IP_INT_MASK 0x00038000
  2037. # define TV_VSCALE_IP_INT_SHIFT 15
  2038. /**
  2039. * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
  2040. *
  2041. * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
  2042. *
  2043. * \sa TV_VSCALE_IP_INT_MASK
  2044. */
  2045. # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
  2046. # define TV_VSCALE_IP_FRAC_SHIFT 0
  2047. #define TV_CC_CONTROL 0x68090
  2048. # define TV_CC_ENABLE (1 << 31)
  2049. /**
  2050. * Specifies which field to send the CC data in.
  2051. *
  2052. * CC data is usually sent in field 0.
  2053. */
  2054. # define TV_CC_FID_MASK (1 << 27)
  2055. # define TV_CC_FID_SHIFT 27
  2056. /** Sets the horizontal position of the CC data. Usually 135. */
  2057. # define TV_CC_HOFF_MASK 0x03ff0000
  2058. # define TV_CC_HOFF_SHIFT 16
  2059. /** Sets the vertical position of the CC data. Usually 21 */
  2060. # define TV_CC_LINE_MASK 0x0000003f
  2061. # define TV_CC_LINE_SHIFT 0
  2062. #define TV_CC_DATA 0x68094
  2063. # define TV_CC_RDY (1 << 31)
  2064. /** Second word of CC data to be transmitted. */
  2065. # define TV_CC_DATA_2_MASK 0x007f0000
  2066. # define TV_CC_DATA_2_SHIFT 16
  2067. /** First word of CC data to be transmitted. */
  2068. # define TV_CC_DATA_1_MASK 0x0000007f
  2069. # define TV_CC_DATA_1_SHIFT 0
  2070. #define TV_H_LUMA_0 0x68100
  2071. #define TV_H_LUMA_59 0x681ec
  2072. #define TV_H_CHROMA_0 0x68200
  2073. #define TV_H_CHROMA_59 0x682ec
  2074. #define TV_V_LUMA_0 0x68300
  2075. #define TV_V_LUMA_42 0x683a8
  2076. #define TV_V_CHROMA_0 0x68400
  2077. #define TV_V_CHROMA_42 0x684a8
  2078. /* Display Port */
  2079. #define DP_A 0x64000 /* eDP */
  2080. #define DP_B 0x64100
  2081. #define DP_C 0x64200
  2082. #define DP_D 0x64300
  2083. #define DP_PORT_EN (1 << 31)
  2084. #define DP_PIPEB_SELECT (1 << 30)
  2085. #define DP_PIPE_MASK (1 << 30)
  2086. /* Link training mode - select a suitable mode for each stage */
  2087. #define DP_LINK_TRAIN_PAT_1 (0 << 28)
  2088. #define DP_LINK_TRAIN_PAT_2 (1 << 28)
  2089. #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
  2090. #define DP_LINK_TRAIN_OFF (3 << 28)
  2091. #define DP_LINK_TRAIN_MASK (3 << 28)
  2092. #define DP_LINK_TRAIN_SHIFT 28
  2093. /* CPT Link training mode */
  2094. #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
  2095. #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
  2096. #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
  2097. #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
  2098. #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
  2099. #define DP_LINK_TRAIN_SHIFT_CPT 8
  2100. /* Signal voltages. These are mostly controlled by the other end */
  2101. #define DP_VOLTAGE_0_4 (0 << 25)
  2102. #define DP_VOLTAGE_0_6 (1 << 25)
  2103. #define DP_VOLTAGE_0_8 (2 << 25)
  2104. #define DP_VOLTAGE_1_2 (3 << 25)
  2105. #define DP_VOLTAGE_MASK (7 << 25)
  2106. #define DP_VOLTAGE_SHIFT 25
  2107. /* Signal pre-emphasis levels, like voltages, the other end tells us what
  2108. * they want
  2109. */
  2110. #define DP_PRE_EMPHASIS_0 (0 << 22)
  2111. #define DP_PRE_EMPHASIS_3_5 (1 << 22)
  2112. #define DP_PRE_EMPHASIS_6 (2 << 22)
  2113. #define DP_PRE_EMPHASIS_9_5 (3 << 22)
  2114. #define DP_PRE_EMPHASIS_MASK (7 << 22)
  2115. #define DP_PRE_EMPHASIS_SHIFT 22
  2116. /* How many wires to use. I guess 3 was too hard */
  2117. #define DP_PORT_WIDTH_1 (0 << 19)
  2118. #define DP_PORT_WIDTH_2 (1 << 19)
  2119. #define DP_PORT_WIDTH_4 (3 << 19)
  2120. #define DP_PORT_WIDTH_MASK (7 << 19)
  2121. /* Mystic DPCD version 1.1 special mode */
  2122. #define DP_ENHANCED_FRAMING (1 << 18)
  2123. /* eDP */
  2124. #define DP_PLL_FREQ_270MHZ (0 << 16)
  2125. #define DP_PLL_FREQ_160MHZ (1 << 16)
  2126. #define DP_PLL_FREQ_MASK (3 << 16)
  2127. /** locked once port is enabled */
  2128. #define DP_PORT_REVERSAL (1 << 15)
  2129. /* eDP */
  2130. #define DP_PLL_ENABLE (1 << 14)
  2131. /** sends the clock on lane 15 of the PEG for debug */
  2132. #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
  2133. #define DP_SCRAMBLING_DISABLE (1 << 12)
  2134. #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
  2135. /** limit RGB values to avoid confusing TVs */
  2136. #define DP_COLOR_RANGE_16_235 (1 << 8)
  2137. /** Turn on the audio link */
  2138. #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
  2139. /** vs and hs sync polarity */
  2140. #define DP_SYNC_VS_HIGH (1 << 4)
  2141. #define DP_SYNC_HS_HIGH (1 << 3)
  2142. /** A fantasy */
  2143. #define DP_DETECTED (1 << 2)
  2144. /** The aux channel provides a way to talk to the
  2145. * signal sink for DDC etc. Max packet size supported
  2146. * is 20 bytes in each direction, hence the 5 fixed
  2147. * data registers
  2148. */
  2149. #define DPA_AUX_CH_CTL 0x64010
  2150. #define DPA_AUX_CH_DATA1 0x64014
  2151. #define DPA_AUX_CH_DATA2 0x64018
  2152. #define DPA_AUX_CH_DATA3 0x6401c
  2153. #define DPA_AUX_CH_DATA4 0x64020
  2154. #define DPA_AUX_CH_DATA5 0x64024
  2155. #define DPB_AUX_CH_CTL 0x64110
  2156. #define DPB_AUX_CH_DATA1 0x64114
  2157. #define DPB_AUX_CH_DATA2 0x64118
  2158. #define DPB_AUX_CH_DATA3 0x6411c
  2159. #define DPB_AUX_CH_DATA4 0x64120
  2160. #define DPB_AUX_CH_DATA5 0x64124
  2161. #define DPC_AUX_CH_CTL 0x64210
  2162. #define DPC_AUX_CH_DATA1 0x64214
  2163. #define DPC_AUX_CH_DATA2 0x64218
  2164. #define DPC_AUX_CH_DATA3 0x6421c
  2165. #define DPC_AUX_CH_DATA4 0x64220
  2166. #define DPC_AUX_CH_DATA5 0x64224
  2167. #define DPD_AUX_CH_CTL 0x64310
  2168. #define DPD_AUX_CH_DATA1 0x64314
  2169. #define DPD_AUX_CH_DATA2 0x64318
  2170. #define DPD_AUX_CH_DATA3 0x6431c
  2171. #define DPD_AUX_CH_DATA4 0x64320
  2172. #define DPD_AUX_CH_DATA5 0x64324
  2173. #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
  2174. #define DP_AUX_CH_CTL_DONE (1 << 30)
  2175. #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
  2176. #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
  2177. #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
  2178. #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
  2179. #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
  2180. #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
  2181. #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
  2182. #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
  2183. #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
  2184. #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
  2185. #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
  2186. #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
  2187. #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
  2188. #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
  2189. #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
  2190. #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
  2191. #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
  2192. #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
  2193. #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
  2194. /*
  2195. * Computing GMCH M and N values for the Display Port link
  2196. *
  2197. * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
  2198. *
  2199. * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
  2200. *
  2201. * The GMCH value is used internally
  2202. *
  2203. * bytes_per_pixel is the number of bytes coming out of the plane,
  2204. * which is after the LUTs, so we want the bytes for our color format.
  2205. * For our current usage, this is always 3, one byte for R, G and B.
  2206. */
  2207. #define _PIPEA_GMCH_DATA_M 0x70050
  2208. #define _PIPEB_GMCH_DATA_M 0x71050
  2209. /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
  2210. #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
  2211. #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
  2212. #define PIPE_GMCH_DATA_M_MASK (0xffffff)
  2213. #define _PIPEA_GMCH_DATA_N 0x70054
  2214. #define _PIPEB_GMCH_DATA_N 0x71054
  2215. #define PIPE_GMCH_DATA_N_MASK (0xffffff)
  2216. /*
  2217. * Computing Link M and N values for the Display Port link
  2218. *
  2219. * Link M / N = pixel_clock / ls_clk
  2220. *
  2221. * (the DP spec calls pixel_clock the 'strm_clk')
  2222. *
  2223. * The Link value is transmitted in the Main Stream
  2224. * Attributes and VB-ID.
  2225. */
  2226. #define _PIPEA_DP_LINK_M 0x70060
  2227. #define _PIPEB_DP_LINK_M 0x71060
  2228. #define PIPEA_DP_LINK_M_MASK (0xffffff)
  2229. #define _PIPEA_DP_LINK_N 0x70064
  2230. #define _PIPEB_DP_LINK_N 0x71064
  2231. #define PIPEA_DP_LINK_N_MASK (0xffffff)
  2232. #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
  2233. #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
  2234. #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
  2235. #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
  2236. /* Display & cursor control */
  2237. /* Pipe A */
  2238. #define _PIPEADSL 0x70000
  2239. #define DSL_LINEMASK 0x00000fff
  2240. #define _PIPEACONF 0x70008
  2241. #define PIPECONF_ENABLE (1<<31)
  2242. #define PIPECONF_DISABLE 0
  2243. #define PIPECONF_DOUBLE_WIDE (1<<30)
  2244. #define I965_PIPECONF_ACTIVE (1<<30)
  2245. #define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
  2246. #define PIPECONF_SINGLE_WIDE 0
  2247. #define PIPECONF_PIPE_UNLOCKED 0
  2248. #define PIPECONF_PIPE_LOCKED (1<<25)
  2249. #define PIPECONF_PALETTE 0
  2250. #define PIPECONF_GAMMA (1<<24)
  2251. #define PIPECONF_FORCE_BORDER (1<<25)
  2252. #define PIPECONF_INTERLACE_MASK (7 << 21)
  2253. /* Note that pre-gen3 does not support interlaced display directly. Panel
  2254. * fitting must be disabled on pre-ilk for interlaced. */
  2255. #define PIPECONF_PROGRESSIVE (0 << 21)
  2256. #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
  2257. #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
  2258. #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
  2259. #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
  2260. /* Ironlake and later have a complete new set of values for interlaced. PFIT
  2261. * means panel fitter required, PF means progressive fetch, DBL means power
  2262. * saving pixel doubling. */
  2263. #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
  2264. #define PIPECONF_INTERLACED_ILK (3 << 21)
  2265. #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
  2266. #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
  2267. #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
  2268. #define PIPECONF_BPP_MASK (0x000000e0)
  2269. #define PIPECONF_BPP_8 (0<<5)
  2270. #define PIPECONF_BPP_10 (1<<5)
  2271. #define PIPECONF_BPP_6 (2<<5)
  2272. #define PIPECONF_BPP_12 (3<<5)
  2273. #define PIPECONF_DITHER_EN (1<<4)
  2274. #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
  2275. #define PIPECONF_DITHER_TYPE_SP (0<<2)
  2276. #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
  2277. #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
  2278. #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
  2279. #define _PIPEASTAT 0x70024
  2280. #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
  2281. #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
  2282. #define PIPE_CRC_DONE_ENABLE (1UL<<28)
  2283. #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
  2284. #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
  2285. #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
  2286. #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
  2287. #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
  2288. #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
  2289. #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
  2290. #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
  2291. #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
  2292. #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
  2293. #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
  2294. #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
  2295. #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
  2296. #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
  2297. #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
  2298. #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
  2299. #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
  2300. #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
  2301. #define PIPE_DPST_EVENT_STATUS (1UL<<7)
  2302. #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
  2303. #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
  2304. #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
  2305. #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
  2306. #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
  2307. #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
  2308. #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
  2309. #define PIPE_BPC_MASK (7 << 5) /* Ironlake */
  2310. #define PIPE_8BPC (0 << 5)
  2311. #define PIPE_10BPC (1 << 5)
  2312. #define PIPE_6BPC (2 << 5)
  2313. #define PIPE_12BPC (3 << 5)
  2314. #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
  2315. #define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
  2316. #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
  2317. #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
  2318. #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
  2319. #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
  2320. #define DSPARB 0x70030
  2321. #define DSPARB_CSTART_MASK (0x7f << 7)
  2322. #define DSPARB_CSTART_SHIFT 7
  2323. #define DSPARB_BSTART_MASK (0x7f)
  2324. #define DSPARB_BSTART_SHIFT 0
  2325. #define DSPARB_BEND_SHIFT 9 /* on 855 */
  2326. #define DSPARB_AEND_SHIFT 0
  2327. #define DSPFW1 0x70034
  2328. #define DSPFW_SR_SHIFT 23
  2329. #define DSPFW_SR_MASK (0x1ff<<23)
  2330. #define DSPFW_CURSORB_SHIFT 16
  2331. #define DSPFW_CURSORB_MASK (0x3f<<16)
  2332. #define DSPFW_PLANEB_SHIFT 8
  2333. #define DSPFW_PLANEB_MASK (0x7f<<8)
  2334. #define DSPFW_PLANEA_MASK (0x7f)
  2335. #define DSPFW2 0x70038
  2336. #define DSPFW_CURSORA_MASK 0x00003f00
  2337. #define DSPFW_CURSORA_SHIFT 8
  2338. #define DSPFW_PLANEC_MASK (0x7f)
  2339. #define DSPFW3 0x7003c
  2340. #define DSPFW_HPLL_SR_EN (1<<31)
  2341. #define DSPFW_CURSOR_SR_SHIFT 24
  2342. #define PINEVIEW_SELF_REFRESH_EN (1<<30)
  2343. #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
  2344. #define DSPFW_HPLL_CURSOR_SHIFT 16
  2345. #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
  2346. #define DSPFW_HPLL_SR_MASK (0x1ff)
  2347. /* FIFO watermark sizes etc */
  2348. #define G4X_FIFO_LINE_SIZE 64
  2349. #define I915_FIFO_LINE_SIZE 64
  2350. #define I830_FIFO_LINE_SIZE 32
  2351. #define G4X_FIFO_SIZE 127
  2352. #define I965_FIFO_SIZE 512
  2353. #define I945_FIFO_SIZE 127
  2354. #define I915_FIFO_SIZE 95
  2355. #define I855GM_FIFO_SIZE 127 /* In cachelines */
  2356. #define I830_FIFO_SIZE 95
  2357. #define G4X_MAX_WM 0x3f
  2358. #define I915_MAX_WM 0x3f
  2359. #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
  2360. #define PINEVIEW_FIFO_LINE_SIZE 64
  2361. #define PINEVIEW_MAX_WM 0x1ff
  2362. #define PINEVIEW_DFT_WM 0x3f
  2363. #define PINEVIEW_DFT_HPLLOFF_WM 0
  2364. #define PINEVIEW_GUARD_WM 10
  2365. #define PINEVIEW_CURSOR_FIFO 64
  2366. #define PINEVIEW_CURSOR_MAX_WM 0x3f
  2367. #define PINEVIEW_CURSOR_DFT_WM 0
  2368. #define PINEVIEW_CURSOR_GUARD_WM 5
  2369. #define I965_CURSOR_FIFO 64
  2370. #define I965_CURSOR_MAX_WM 32
  2371. #define I965_CURSOR_DFT_WM 8
  2372. /* define the Watermark register on Ironlake */
  2373. #define WM0_PIPEA_ILK 0x45100
  2374. #define WM0_PIPE_PLANE_MASK (0x7f<<16)
  2375. #define WM0_PIPE_PLANE_SHIFT 16
  2376. #define WM0_PIPE_SPRITE_MASK (0x3f<<8)
  2377. #define WM0_PIPE_SPRITE_SHIFT 8
  2378. #define WM0_PIPE_CURSOR_MASK (0x1f)
  2379. #define WM0_PIPEB_ILK 0x45104
  2380. #define WM0_PIPEC_IVB 0x45200
  2381. #define WM1_LP_ILK 0x45108
  2382. #define WM1_LP_SR_EN (1<<31)
  2383. #define WM1_LP_LATENCY_SHIFT 24
  2384. #define WM1_LP_LATENCY_MASK (0x7f<<24)
  2385. #define WM1_LP_FBC_MASK (0xf<<20)
  2386. #define WM1_LP_FBC_SHIFT 20
  2387. #define WM1_LP_SR_MASK (0x1ff<<8)
  2388. #define WM1_LP_SR_SHIFT 8
  2389. #define WM1_LP_CURSOR_MASK (0x3f)
  2390. #define WM2_LP_ILK 0x4510c
  2391. #define WM2_LP_EN (1<<31)
  2392. #define WM3_LP_ILK 0x45110
  2393. #define WM3_LP_EN (1<<31)
  2394. #define WM1S_LP_ILK 0x45120
  2395. #define WM2S_LP_IVB 0x45124
  2396. #define WM3S_LP_IVB 0x45128
  2397. #define WM1S_LP_EN (1<<31)
  2398. /* Memory latency timer register */
  2399. #define MLTR_ILK 0x11222
  2400. #define MLTR_WM1_SHIFT 0
  2401. #define MLTR_WM2_SHIFT 8
  2402. /* the unit of memory self-refresh latency time is 0.5us */
  2403. #define ILK_SRLT_MASK 0x3f
  2404. #define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
  2405. #define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT)
  2406. #define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT)
  2407. /* define the fifo size on Ironlake */
  2408. #define ILK_DISPLAY_FIFO 128
  2409. #define ILK_DISPLAY_MAXWM 64
  2410. #define ILK_DISPLAY_DFTWM 8
  2411. #define ILK_CURSOR_FIFO 32
  2412. #define ILK_CURSOR_MAXWM 16
  2413. #define ILK_CURSOR_DFTWM 8
  2414. #define ILK_DISPLAY_SR_FIFO 512
  2415. #define ILK_DISPLAY_MAX_SRWM 0x1ff
  2416. #define ILK_DISPLAY_DFT_SRWM 0x3f
  2417. #define ILK_CURSOR_SR_FIFO 64
  2418. #define ILK_CURSOR_MAX_SRWM 0x3f
  2419. #define ILK_CURSOR_DFT_SRWM 8
  2420. #define ILK_FIFO_LINE_SIZE 64
  2421. /* define the WM info on Sandybridge */
  2422. #define SNB_DISPLAY_FIFO 128
  2423. #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
  2424. #define SNB_DISPLAY_DFTWM 8
  2425. #define SNB_CURSOR_FIFO 32
  2426. #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
  2427. #define SNB_CURSOR_DFTWM 8
  2428. #define SNB_DISPLAY_SR_FIFO 512
  2429. #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
  2430. #define SNB_DISPLAY_DFT_SRWM 0x3f
  2431. #define SNB_CURSOR_SR_FIFO 64
  2432. #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
  2433. #define SNB_CURSOR_DFT_SRWM 8
  2434. #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
  2435. #define SNB_FIFO_LINE_SIZE 64
  2436. /* the address where we get all kinds of latency value */
  2437. #define SSKPD 0x5d10
  2438. #define SSKPD_WM_MASK 0x3f
  2439. #define SSKPD_WM0_SHIFT 0
  2440. #define SSKPD_WM1_SHIFT 8
  2441. #define SSKPD_WM2_SHIFT 16
  2442. #define SSKPD_WM3_SHIFT 24
  2443. #define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
  2444. #define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
  2445. #define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
  2446. #define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
  2447. #define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
  2448. /*
  2449. * The two pipe frame counter registers are not synchronized, so
  2450. * reading a stable value is somewhat tricky. The following code
  2451. * should work:
  2452. *
  2453. * do {
  2454. * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
  2455. * PIPE_FRAME_HIGH_SHIFT;
  2456. * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
  2457. * PIPE_FRAME_LOW_SHIFT);
  2458. * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
  2459. * PIPE_FRAME_HIGH_SHIFT);
  2460. * } while (high1 != high2);
  2461. * frame = (high1 << 8) | low1;
  2462. */
  2463. #define _PIPEAFRAMEHIGH 0x70040
  2464. #define PIPE_FRAME_HIGH_MASK 0x0000ffff
  2465. #define PIPE_FRAME_HIGH_SHIFT 0
  2466. #define _PIPEAFRAMEPIXEL 0x70044
  2467. #define PIPE_FRAME_LOW_MASK 0xff000000
  2468. #define PIPE_FRAME_LOW_SHIFT 24
  2469. #define PIPE_PIXEL_MASK 0x00ffffff
  2470. #define PIPE_PIXEL_SHIFT 0
  2471. /* GM45+ just has to be different */
  2472. #define _PIPEA_FRMCOUNT_GM45 0x70040
  2473. #define _PIPEA_FLIPCOUNT_GM45 0x70044
  2474. #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
  2475. /* Cursor A & B regs */
  2476. #define _CURACNTR 0x70080
  2477. /* Old style CUR*CNTR flags (desktop 8xx) */
  2478. #define CURSOR_ENABLE 0x80000000
  2479. #define CURSOR_GAMMA_ENABLE 0x40000000
  2480. #define CURSOR_STRIDE_MASK 0x30000000
  2481. #define CURSOR_FORMAT_SHIFT 24
  2482. #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
  2483. #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
  2484. #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
  2485. #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
  2486. #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
  2487. #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
  2488. /* New style CUR*CNTR flags */
  2489. #define CURSOR_MODE 0x27
  2490. #define CURSOR_MODE_DISABLE 0x00
  2491. #define CURSOR_MODE_64_32B_AX 0x07
  2492. #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
  2493. #define MCURSOR_PIPE_SELECT (1 << 28)
  2494. #define MCURSOR_PIPE_A 0x00
  2495. #define MCURSOR_PIPE_B (1 << 28)
  2496. #define MCURSOR_GAMMA_ENABLE (1 << 26)
  2497. #define _CURABASE 0x70084
  2498. #define _CURAPOS 0x70088
  2499. #define CURSOR_POS_MASK 0x007FF
  2500. #define CURSOR_POS_SIGN 0x8000
  2501. #define CURSOR_X_SHIFT 0
  2502. #define CURSOR_Y_SHIFT 16
  2503. #define CURSIZE 0x700a0
  2504. #define _CURBCNTR 0x700c0
  2505. #define _CURBBASE 0x700c4
  2506. #define _CURBPOS 0x700c8
  2507. #define _CURBCNTR_IVB 0x71080
  2508. #define _CURBBASE_IVB 0x71084
  2509. #define _CURBPOS_IVB 0x71088
  2510. #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
  2511. #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
  2512. #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
  2513. #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
  2514. #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
  2515. #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
  2516. /* Display A control */
  2517. #define _DSPACNTR 0x70180
  2518. #define DISPLAY_PLANE_ENABLE (1<<31)
  2519. #define DISPLAY_PLANE_DISABLE 0
  2520. #define DISPPLANE_GAMMA_ENABLE (1<<30)
  2521. #define DISPPLANE_GAMMA_DISABLE 0
  2522. #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
  2523. #define DISPPLANE_8BPP (0x2<<26)
  2524. #define DISPPLANE_15_16BPP (0x4<<26)
  2525. #define DISPPLANE_16BPP (0x5<<26)
  2526. #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
  2527. #define DISPPLANE_32BPP (0x7<<26)
  2528. #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
  2529. #define DISPPLANE_STEREO_ENABLE (1<<25)
  2530. #define DISPPLANE_STEREO_DISABLE 0
  2531. #define DISPPLANE_SEL_PIPE_SHIFT 24
  2532. #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
  2533. #define DISPPLANE_SEL_PIPE_A 0
  2534. #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
  2535. #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
  2536. #define DISPPLANE_SRC_KEY_DISABLE 0
  2537. #define DISPPLANE_LINE_DOUBLE (1<<20)
  2538. #define DISPPLANE_NO_LINE_DOUBLE 0
  2539. #define DISPPLANE_STEREO_POLARITY_FIRST 0
  2540. #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
  2541. #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
  2542. #define DISPPLANE_TILED (1<<10)
  2543. #define _DSPAADDR 0x70184
  2544. #define _DSPASTRIDE 0x70188
  2545. #define _DSPAPOS 0x7018C /* reserved */
  2546. #define _DSPASIZE 0x70190
  2547. #define _DSPASURF 0x7019C /* 965+ only */
  2548. #define _DSPATILEOFF 0x701A4 /* 965+ only */
  2549. #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
  2550. #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
  2551. #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
  2552. #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
  2553. #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
  2554. #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
  2555. #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
  2556. /* VBIOS flags */
  2557. #define SWF00 0x71410
  2558. #define SWF01 0x71414
  2559. #define SWF02 0x71418
  2560. #define SWF03 0x7141c
  2561. #define SWF04 0x71420
  2562. #define SWF05 0x71424
  2563. #define SWF06 0x71428
  2564. #define SWF10 0x70410
  2565. #define SWF11 0x70414
  2566. #define SWF14 0x71420
  2567. #define SWF30 0x72414
  2568. #define SWF31 0x72418
  2569. #define SWF32 0x7241c
  2570. /* Pipe B */
  2571. #define _PIPEBDSL 0x71000
  2572. #define _PIPEBCONF 0x71008
  2573. #define _PIPEBSTAT 0x71024
  2574. #define _PIPEBFRAMEHIGH 0x71040
  2575. #define _PIPEBFRAMEPIXEL 0x71044
  2576. #define _PIPEB_FRMCOUNT_GM45 0x71040
  2577. #define _PIPEB_FLIPCOUNT_GM45 0x71044
  2578. /* Display B control */
  2579. #define _DSPBCNTR 0x71180
  2580. #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
  2581. #define DISPPLANE_ALPHA_TRANS_DISABLE 0
  2582. #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
  2583. #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
  2584. #define _DSPBADDR 0x71184
  2585. #define _DSPBSTRIDE 0x71188
  2586. #define _DSPBPOS 0x7118C
  2587. #define _DSPBSIZE 0x71190
  2588. #define _DSPBSURF 0x7119C
  2589. #define _DSPBTILEOFF 0x711A4
  2590. /* Sprite A control */
  2591. #define _DVSACNTR 0x72180
  2592. #define DVS_ENABLE (1<<31)
  2593. #define DVS_GAMMA_ENABLE (1<<30)
  2594. #define DVS_PIXFORMAT_MASK (3<<25)
  2595. #define DVS_FORMAT_YUV422 (0<<25)
  2596. #define DVS_FORMAT_RGBX101010 (1<<25)
  2597. #define DVS_FORMAT_RGBX888 (2<<25)
  2598. #define DVS_FORMAT_RGBX161616 (3<<25)
  2599. #define DVS_SOURCE_KEY (1<<22)
  2600. #define DVS_RGB_ORDER_XBGR (1<<20)
  2601. #define DVS_YUV_BYTE_ORDER_MASK (3<<16)
  2602. #define DVS_YUV_ORDER_YUYV (0<<16)
  2603. #define DVS_YUV_ORDER_UYVY (1<<16)
  2604. #define DVS_YUV_ORDER_YVYU (2<<16)
  2605. #define DVS_YUV_ORDER_VYUY (3<<16)
  2606. #define DVS_DEST_KEY (1<<2)
  2607. #define DVS_TRICKLE_FEED_DISABLE (1<<14)
  2608. #define DVS_TILED (1<<10)
  2609. #define _DVSALINOFF 0x72184
  2610. #define _DVSASTRIDE 0x72188
  2611. #define _DVSAPOS 0x7218c
  2612. #define _DVSASIZE 0x72190
  2613. #define _DVSAKEYVAL 0x72194
  2614. #define _DVSAKEYMSK 0x72198
  2615. #define _DVSASURF 0x7219c
  2616. #define _DVSAKEYMAXVAL 0x721a0
  2617. #define _DVSATILEOFF 0x721a4
  2618. #define _DVSASURFLIVE 0x721ac
  2619. #define _DVSASCALE 0x72204
  2620. #define DVS_SCALE_ENABLE (1<<31)
  2621. #define DVS_FILTER_MASK (3<<29)
  2622. #define DVS_FILTER_MEDIUM (0<<29)
  2623. #define DVS_FILTER_ENHANCING (1<<29)
  2624. #define DVS_FILTER_SOFTENING (2<<29)
  2625. #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
  2626. #define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
  2627. #define _DVSAGAMC 0x72300
  2628. #define _DVSBCNTR 0x73180
  2629. #define _DVSBLINOFF 0x73184
  2630. #define _DVSBSTRIDE 0x73188
  2631. #define _DVSBPOS 0x7318c
  2632. #define _DVSBSIZE 0x73190
  2633. #define _DVSBKEYVAL 0x73194
  2634. #define _DVSBKEYMSK 0x73198
  2635. #define _DVSBSURF 0x7319c
  2636. #define _DVSBKEYMAXVAL 0x731a0
  2637. #define _DVSBTILEOFF 0x731a4
  2638. #define _DVSBSURFLIVE 0x731ac
  2639. #define _DVSBSCALE 0x73204
  2640. #define _DVSBGAMC 0x73300
  2641. #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
  2642. #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
  2643. #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
  2644. #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
  2645. #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
  2646. #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
  2647. #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
  2648. #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
  2649. #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
  2650. #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
  2651. #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
  2652. #define _SPRA_CTL 0x70280
  2653. #define SPRITE_ENABLE (1<<31)
  2654. #define SPRITE_GAMMA_ENABLE (1<<30)
  2655. #define SPRITE_PIXFORMAT_MASK (7<<25)
  2656. #define SPRITE_FORMAT_YUV422 (0<<25)
  2657. #define SPRITE_FORMAT_RGBX101010 (1<<25)
  2658. #define SPRITE_FORMAT_RGBX888 (2<<25)
  2659. #define SPRITE_FORMAT_RGBX161616 (3<<25)
  2660. #define SPRITE_FORMAT_YUV444 (4<<25)
  2661. #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
  2662. #define SPRITE_CSC_ENABLE (1<<24)
  2663. #define SPRITE_SOURCE_KEY (1<<22)
  2664. #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
  2665. #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
  2666. #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
  2667. #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
  2668. #define SPRITE_YUV_ORDER_YUYV (0<<16)
  2669. #define SPRITE_YUV_ORDER_UYVY (1<<16)
  2670. #define SPRITE_YUV_ORDER_YVYU (2<<16)
  2671. #define SPRITE_YUV_ORDER_VYUY (3<<16)
  2672. #define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
  2673. #define SPRITE_INT_GAMMA_ENABLE (1<<13)
  2674. #define SPRITE_TILED (1<<10)
  2675. #define SPRITE_DEST_KEY (1<<2)
  2676. #define _SPRA_LINOFF 0x70284
  2677. #define _SPRA_STRIDE 0x70288
  2678. #define _SPRA_POS 0x7028c
  2679. #define _SPRA_SIZE 0x70290
  2680. #define _SPRA_KEYVAL 0x70294
  2681. #define _SPRA_KEYMSK 0x70298
  2682. #define _SPRA_SURF 0x7029c
  2683. #define _SPRA_KEYMAX 0x702a0
  2684. #define _SPRA_TILEOFF 0x702a4
  2685. #define _SPRA_SCALE 0x70304
  2686. #define SPRITE_SCALE_ENABLE (1<<31)
  2687. #define SPRITE_FILTER_MASK (3<<29)
  2688. #define SPRITE_FILTER_MEDIUM (0<<29)
  2689. #define SPRITE_FILTER_ENHANCING (1<<29)
  2690. #define SPRITE_FILTER_SOFTENING (2<<29)
  2691. #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
  2692. #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
  2693. #define _SPRA_GAMC 0x70400
  2694. #define _SPRB_CTL 0x71280
  2695. #define _SPRB_LINOFF 0x71284
  2696. #define _SPRB_STRIDE 0x71288
  2697. #define _SPRB_POS 0x7128c
  2698. #define _SPRB_SIZE 0x71290
  2699. #define _SPRB_KEYVAL 0x71294
  2700. #define _SPRB_KEYMSK 0x71298
  2701. #define _SPRB_SURF 0x7129c
  2702. #define _SPRB_KEYMAX 0x712a0
  2703. #define _SPRB_TILEOFF 0x712a4
  2704. #define _SPRB_SCALE 0x71304
  2705. #define _SPRB_GAMC 0x71400
  2706. #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
  2707. #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
  2708. #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
  2709. #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
  2710. #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
  2711. #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
  2712. #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
  2713. #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
  2714. #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
  2715. #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
  2716. #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
  2717. #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
  2718. /* VBIOS regs */
  2719. #define VGACNTRL 0x71400
  2720. # define VGA_DISP_DISABLE (1 << 31)
  2721. # define VGA_2X_MODE (1 << 30)
  2722. # define VGA_PIPE_B_SELECT (1 << 29)
  2723. /* Ironlake */
  2724. #define CPU_VGACNTRL 0x41000
  2725. #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
  2726. #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
  2727. #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
  2728. #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
  2729. #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
  2730. #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
  2731. #define DIGITAL_PORTA_NO_DETECT (0 << 0)
  2732. #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
  2733. #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
  2734. /* refresh rate hardware control */
  2735. #define RR_HW_CTL 0x45300
  2736. #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
  2737. #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
  2738. #define FDI_PLL_BIOS_0 0x46000
  2739. #define FDI_PLL_FB_CLOCK_MASK 0xff
  2740. #define FDI_PLL_BIOS_1 0x46004
  2741. #define FDI_PLL_BIOS_2 0x46008
  2742. #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
  2743. #define DISPLAY_PORT_PLL_BIOS_1 0x46010
  2744. #define DISPLAY_PORT_PLL_BIOS_2 0x46014
  2745. #define PCH_DSPCLK_GATE_D 0x42020
  2746. # define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
  2747. # define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
  2748. # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
  2749. # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
  2750. #define PCH_3DCGDIS0 0x46020
  2751. # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
  2752. # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
  2753. #define PCH_3DCGDIS1 0x46024
  2754. # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
  2755. #define FDI_PLL_FREQ_CTL 0x46030
  2756. #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
  2757. #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
  2758. #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
  2759. #define _PIPEA_DATA_M1 0x60030
  2760. #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
  2761. #define TU_SIZE_MASK 0x7e000000
  2762. #define PIPE_DATA_M1_OFFSET 0
  2763. #define _PIPEA_DATA_N1 0x60034
  2764. #define PIPE_DATA_N1_OFFSET 0
  2765. #define _PIPEA_DATA_M2 0x60038
  2766. #define PIPE_DATA_M2_OFFSET 0
  2767. #define _PIPEA_DATA_N2 0x6003c
  2768. #define PIPE_DATA_N2_OFFSET 0
  2769. #define _PIPEA_LINK_M1 0x60040
  2770. #define PIPE_LINK_M1_OFFSET 0
  2771. #define _PIPEA_LINK_N1 0x60044
  2772. #define PIPE_LINK_N1_OFFSET 0
  2773. #define _PIPEA_LINK_M2 0x60048
  2774. #define PIPE_LINK_M2_OFFSET 0
  2775. #define _PIPEA_LINK_N2 0x6004c
  2776. #define PIPE_LINK_N2_OFFSET 0
  2777. /* PIPEB timing regs are same start from 0x61000 */
  2778. #define _PIPEB_DATA_M1 0x61030
  2779. #define _PIPEB_DATA_N1 0x61034
  2780. #define _PIPEB_DATA_M2 0x61038
  2781. #define _PIPEB_DATA_N2 0x6103c
  2782. #define _PIPEB_LINK_M1 0x61040
  2783. #define _PIPEB_LINK_N1 0x61044
  2784. #define _PIPEB_LINK_M2 0x61048
  2785. #define _PIPEB_LINK_N2 0x6104c
  2786. #define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
  2787. #define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
  2788. #define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
  2789. #define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
  2790. #define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
  2791. #define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
  2792. #define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
  2793. #define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
  2794. /* CPU panel fitter */
  2795. /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
  2796. #define _PFA_CTL_1 0x68080
  2797. #define _PFB_CTL_1 0x68880
  2798. #define PF_ENABLE (1<<31)
  2799. #define PF_PIPE_SEL_MASK_IVB (3<<29)
  2800. #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
  2801. #define PF_FILTER_MASK (3<<23)
  2802. #define PF_FILTER_PROGRAMMED (0<<23)
  2803. #define PF_FILTER_MED_3x3 (1<<23)
  2804. #define PF_FILTER_EDGE_ENHANCE (2<<23)
  2805. #define PF_FILTER_EDGE_SOFTEN (3<<23)
  2806. #define _PFA_WIN_SZ 0x68074
  2807. #define _PFB_WIN_SZ 0x68874
  2808. #define _PFA_WIN_POS 0x68070
  2809. #define _PFB_WIN_POS 0x68870
  2810. #define _PFA_VSCALE 0x68084
  2811. #define _PFB_VSCALE 0x68884
  2812. #define _PFA_HSCALE 0x68090
  2813. #define _PFB_HSCALE 0x68890
  2814. #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
  2815. #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
  2816. #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
  2817. #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
  2818. #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
  2819. /* legacy palette */
  2820. #define _LGC_PALETTE_A 0x4a000
  2821. #define _LGC_PALETTE_B 0x4a800
  2822. #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
  2823. /* interrupts */
  2824. #define DE_MASTER_IRQ_CONTROL (1 << 31)
  2825. #define DE_SPRITEB_FLIP_DONE (1 << 29)
  2826. #define DE_SPRITEA_FLIP_DONE (1 << 28)
  2827. #define DE_PLANEB_FLIP_DONE (1 << 27)
  2828. #define DE_PLANEA_FLIP_DONE (1 << 26)
  2829. #define DE_PCU_EVENT (1 << 25)
  2830. #define DE_GTT_FAULT (1 << 24)
  2831. #define DE_POISON (1 << 23)
  2832. #define DE_PERFORM_COUNTER (1 << 22)
  2833. #define DE_PCH_EVENT (1 << 21)
  2834. #define DE_AUX_CHANNEL_A (1 << 20)
  2835. #define DE_DP_A_HOTPLUG (1 << 19)
  2836. #define DE_GSE (1 << 18)
  2837. #define DE_PIPEB_VBLANK (1 << 15)
  2838. #define DE_PIPEB_EVEN_FIELD (1 << 14)
  2839. #define DE_PIPEB_ODD_FIELD (1 << 13)
  2840. #define DE_PIPEB_LINE_COMPARE (1 << 12)
  2841. #define DE_PIPEB_VSYNC (1 << 11)
  2842. #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
  2843. #define DE_PIPEA_VBLANK (1 << 7)
  2844. #define DE_PIPEA_EVEN_FIELD (1 << 6)
  2845. #define DE_PIPEA_ODD_FIELD (1 << 5)
  2846. #define DE_PIPEA_LINE_COMPARE (1 << 4)
  2847. #define DE_PIPEA_VSYNC (1 << 3)
  2848. #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
  2849. /* More Ivybridge lolz */
  2850. #define DE_ERR_DEBUG_IVB (1<<30)
  2851. #define DE_GSE_IVB (1<<29)
  2852. #define DE_PCH_EVENT_IVB (1<<28)
  2853. #define DE_DP_A_HOTPLUG_IVB (1<<27)
  2854. #define DE_AUX_CHANNEL_A_IVB (1<<26)
  2855. #define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
  2856. #define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
  2857. #define DE_PLANEB_FLIP_DONE_IVB (1<<8)
  2858. #define DE_PLANEA_FLIP_DONE_IVB (1<<3)
  2859. #define DE_PIPEB_VBLANK_IVB (1<<5)
  2860. #define DE_PIPEA_VBLANK_IVB (1<<0)
  2861. #define DEISR 0x44000
  2862. #define DEIMR 0x44004
  2863. #define DEIIR 0x44008
  2864. #define DEIER 0x4400c
  2865. /* GT interrupt */
  2866. #define GT_PIPE_NOTIFY (1 << 4)
  2867. #define GT_SYNC_STATUS (1 << 2)
  2868. #define GT_USER_INTERRUPT (1 << 0)
  2869. #define GT_BSD_USER_INTERRUPT (1 << 5)
  2870. #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
  2871. #define GT_BLT_USER_INTERRUPT (1 << 22)
  2872. #define GTISR 0x44010
  2873. #define GTIMR 0x44014
  2874. #define GTIIR 0x44018
  2875. #define GTIER 0x4401c
  2876. #define ILK_DISPLAY_CHICKEN2 0x42004
  2877. /* Required on all Ironlake and Sandybridge according to the B-Spec. */
  2878. #define ILK_ELPIN_409_SELECT (1 << 25)
  2879. #define ILK_DPARB_GATE (1<<22)
  2880. #define ILK_VSDPFD_FULL (1<<21)
  2881. #define ILK_DISPLAY_CHICKEN_FUSES 0x42014
  2882. #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
  2883. #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
  2884. #define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
  2885. #define ILK_HDCP_DISABLE (1<<25)
  2886. #define ILK_eDP_A_DISABLE (1<<24)
  2887. #define ILK_DESKTOP (1<<23)
  2888. #define ILK_DSPCLK_GATE 0x42020
  2889. #define IVB_VRHUNIT_CLK_GATE (1<<28)
  2890. #define ILK_DPARB_CLK_GATE (1<<5)
  2891. #define ILK_DPFD_CLK_GATE (1<<7)
  2892. /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
  2893. #define ILK_CLK_FBC (1<<7)
  2894. #define ILK_DPFC_DIS1 (1<<8)
  2895. #define ILK_DPFC_DIS2 (1<<9)
  2896. #define IVB_CHICKEN3 0x4200c
  2897. # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
  2898. # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
  2899. #define DISP_ARB_CTL 0x45000
  2900. #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
  2901. #define DISP_FBC_WM_DIS (1<<15)
  2902. /* GEN7 chicken */
  2903. #define GEN7_COMMON_SLICE_CHICKEN1 0x7010
  2904. # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
  2905. #define GEN7_L3CNTLREG1 0xB01C
  2906. #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
  2907. #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
  2908. #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
  2909. /* WaCatErrorRejectionIssue */
  2910. #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
  2911. #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
  2912. /* PCH */
  2913. /* south display engine interrupt */
  2914. #define SDE_AUDIO_POWER_D (1 << 27)
  2915. #define SDE_AUDIO_POWER_C (1 << 26)
  2916. #define SDE_AUDIO_POWER_B (1 << 25)
  2917. #define SDE_AUDIO_POWER_SHIFT (25)
  2918. #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
  2919. #define SDE_GMBUS (1 << 24)
  2920. #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
  2921. #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
  2922. #define SDE_AUDIO_HDCP_MASK (3 << 22)
  2923. #define SDE_AUDIO_TRANSB (1 << 21)
  2924. #define SDE_AUDIO_TRANSA (1 << 20)
  2925. #define SDE_AUDIO_TRANS_MASK (3 << 20)
  2926. #define SDE_POISON (1 << 19)
  2927. /* 18 reserved */
  2928. #define SDE_FDI_RXB (1 << 17)
  2929. #define SDE_FDI_RXA (1 << 16)
  2930. #define SDE_FDI_MASK (3 << 16)
  2931. #define SDE_AUXD (1 << 15)
  2932. #define SDE_AUXC (1 << 14)
  2933. #define SDE_AUXB (1 << 13)
  2934. #define SDE_AUX_MASK (7 << 13)
  2935. /* 12 reserved */
  2936. #define SDE_CRT_HOTPLUG (1 << 11)
  2937. #define SDE_PORTD_HOTPLUG (1 << 10)
  2938. #define SDE_PORTC_HOTPLUG (1 << 9)
  2939. #define SDE_PORTB_HOTPLUG (1 << 8)
  2940. #define SDE_SDVOB_HOTPLUG (1 << 6)
  2941. #define SDE_HOTPLUG_MASK (0xf << 8)
  2942. #define SDE_TRANSB_CRC_DONE (1 << 5)
  2943. #define SDE_TRANSB_CRC_ERR (1 << 4)
  2944. #define SDE_TRANSB_FIFO_UNDER (1 << 3)
  2945. #define SDE_TRANSA_CRC_DONE (1 << 2)
  2946. #define SDE_TRANSA_CRC_ERR (1 << 1)
  2947. #define SDE_TRANSA_FIFO_UNDER (1 << 0)
  2948. #define SDE_TRANS_MASK (0x3f)
  2949. /* CPT */
  2950. #define SDE_CRT_HOTPLUG_CPT (1 << 19)
  2951. #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
  2952. #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
  2953. #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
  2954. #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
  2955. SDE_PORTD_HOTPLUG_CPT | \
  2956. SDE_PORTC_HOTPLUG_CPT | \
  2957. SDE_PORTB_HOTPLUG_CPT)
  2958. #define SDEISR 0xc4000
  2959. #define SDEIMR 0xc4004
  2960. #define SDEIIR 0xc4008
  2961. #define SDEIER 0xc400c
  2962. /* digital port hotplug */
  2963. #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
  2964. #define PORTD_HOTPLUG_ENABLE (1 << 20)
  2965. #define PORTD_PULSE_DURATION_2ms (0)
  2966. #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
  2967. #define PORTD_PULSE_DURATION_6ms (2 << 18)
  2968. #define PORTD_PULSE_DURATION_100ms (3 << 18)
  2969. #define PORTD_PULSE_DURATION_MASK (3 << 18)
  2970. #define PORTD_HOTPLUG_NO_DETECT (0)
  2971. #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
  2972. #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
  2973. #define PORTC_HOTPLUG_ENABLE (1 << 12)
  2974. #define PORTC_PULSE_DURATION_2ms (0)
  2975. #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
  2976. #define PORTC_PULSE_DURATION_6ms (2 << 10)
  2977. #define PORTC_PULSE_DURATION_100ms (3 << 10)
  2978. #define PORTC_PULSE_DURATION_MASK (3 << 10)
  2979. #define PORTC_HOTPLUG_NO_DETECT (0)
  2980. #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
  2981. #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
  2982. #define PORTB_HOTPLUG_ENABLE (1 << 4)
  2983. #define PORTB_PULSE_DURATION_2ms (0)
  2984. #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
  2985. #define PORTB_PULSE_DURATION_6ms (2 << 2)
  2986. #define PORTB_PULSE_DURATION_100ms (3 << 2)
  2987. #define PORTB_PULSE_DURATION_MASK (3 << 2)
  2988. #define PORTB_HOTPLUG_NO_DETECT (0)
  2989. #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
  2990. #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
  2991. #define PCH_GPIOA 0xc5010
  2992. #define PCH_GPIOB 0xc5014
  2993. #define PCH_GPIOC 0xc5018
  2994. #define PCH_GPIOD 0xc501c
  2995. #define PCH_GPIOE 0xc5020
  2996. #define PCH_GPIOF 0xc5024
  2997. #define PCH_GMBUS0 0xc5100
  2998. #define PCH_GMBUS1 0xc5104
  2999. #define PCH_GMBUS2 0xc5108
  3000. #define PCH_GMBUS3 0xc510c
  3001. #define PCH_GMBUS4 0xc5110
  3002. #define PCH_GMBUS5 0xc5120
  3003. #define _PCH_DPLL_A 0xc6014
  3004. #define _PCH_DPLL_B 0xc6018
  3005. #define PCH_DPLL(pipe) (pipe == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
  3006. #define _PCH_FPA0 0xc6040
  3007. #define FP_CB_TUNE (0x3<<22)
  3008. #define _PCH_FPA1 0xc6044
  3009. #define _PCH_FPB0 0xc6048
  3010. #define _PCH_FPB1 0xc604c
  3011. #define PCH_FP0(pipe) (pipe == 0 ? _PCH_FPA0 : _PCH_FPB0)
  3012. #define PCH_FP1(pipe) (pipe == 0 ? _PCH_FPA1 : _PCH_FPB1)
  3013. #define PCH_DPLL_TEST 0xc606c
  3014. #define PCH_DREF_CONTROL 0xC6200
  3015. #define DREF_CONTROL_MASK 0x7fc3
  3016. #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
  3017. #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
  3018. #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
  3019. #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
  3020. #define DREF_SSC_SOURCE_DISABLE (0<<11)
  3021. #define DREF_SSC_SOURCE_ENABLE (2<<11)
  3022. #define DREF_SSC_SOURCE_MASK (3<<11)
  3023. #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
  3024. #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
  3025. #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
  3026. #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
  3027. #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
  3028. #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
  3029. #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
  3030. #define DREF_SSC4_DOWNSPREAD (0<<6)
  3031. #define DREF_SSC4_CENTERSPREAD (1<<6)
  3032. #define DREF_SSC1_DISABLE (0<<1)
  3033. #define DREF_SSC1_ENABLE (1<<1)
  3034. #define DREF_SSC4_DISABLE (0)
  3035. #define DREF_SSC4_ENABLE (1)
  3036. #define PCH_RAWCLK_FREQ 0xc6204
  3037. #define FDL_TP1_TIMER_SHIFT 12
  3038. #define FDL_TP1_TIMER_MASK (3<<12)
  3039. #define FDL_TP2_TIMER_SHIFT 10
  3040. #define FDL_TP2_TIMER_MASK (3<<10)
  3041. #define RAWCLK_FREQ_MASK 0x3ff
  3042. #define PCH_DPLL_TMR_CFG 0xc6208
  3043. #define PCH_SSC4_PARMS 0xc6210
  3044. #define PCH_SSC4_AUX_PARMS 0xc6214
  3045. #define PCH_DPLL_SEL 0xc7000
  3046. #define TRANSA_DPLL_ENABLE (1<<3)
  3047. #define TRANSA_DPLLB_SEL (1<<0)
  3048. #define TRANSA_DPLLA_SEL 0
  3049. #define TRANSB_DPLL_ENABLE (1<<7)
  3050. #define TRANSB_DPLLB_SEL (1<<4)
  3051. #define TRANSB_DPLLA_SEL (0)
  3052. #define TRANSC_DPLL_ENABLE (1<<11)
  3053. #define TRANSC_DPLLB_SEL (1<<8)
  3054. #define TRANSC_DPLLA_SEL (0)
  3055. /* transcoder */
  3056. #define _TRANS_HTOTAL_A 0xe0000
  3057. #define TRANS_HTOTAL_SHIFT 16
  3058. #define TRANS_HACTIVE_SHIFT 0
  3059. #define _TRANS_HBLANK_A 0xe0004
  3060. #define TRANS_HBLANK_END_SHIFT 16
  3061. #define TRANS_HBLANK_START_SHIFT 0
  3062. #define _TRANS_HSYNC_A 0xe0008
  3063. #define TRANS_HSYNC_END_SHIFT 16
  3064. #define TRANS_HSYNC_START_SHIFT 0
  3065. #define _TRANS_VTOTAL_A 0xe000c
  3066. #define TRANS_VTOTAL_SHIFT 16
  3067. #define TRANS_VACTIVE_SHIFT 0
  3068. #define _TRANS_VBLANK_A 0xe0010
  3069. #define TRANS_VBLANK_END_SHIFT 16
  3070. #define TRANS_VBLANK_START_SHIFT 0
  3071. #define _TRANS_VSYNC_A 0xe0014
  3072. #define TRANS_VSYNC_END_SHIFT 16
  3073. #define TRANS_VSYNC_START_SHIFT 0
  3074. #define _TRANS_VSYNCSHIFT_A 0xe0028
  3075. #define _TRANSA_DATA_M1 0xe0030
  3076. #define _TRANSA_DATA_N1 0xe0034
  3077. #define _TRANSA_DATA_M2 0xe0038
  3078. #define _TRANSA_DATA_N2 0xe003c
  3079. #define _TRANSA_DP_LINK_M1 0xe0040
  3080. #define _TRANSA_DP_LINK_N1 0xe0044
  3081. #define _TRANSA_DP_LINK_M2 0xe0048
  3082. #define _TRANSA_DP_LINK_N2 0xe004c
  3083. /* Per-transcoder DIP controls */
  3084. #define _VIDEO_DIP_CTL_A 0xe0200
  3085. #define _VIDEO_DIP_DATA_A 0xe0208
  3086. #define _VIDEO_DIP_GCP_A 0xe0210
  3087. #define _VIDEO_DIP_CTL_B 0xe1200
  3088. #define _VIDEO_DIP_DATA_B 0xe1208
  3089. #define _VIDEO_DIP_GCP_B 0xe1210
  3090. #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
  3091. #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
  3092. #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
  3093. #define _TRANS_HTOTAL_B 0xe1000
  3094. #define _TRANS_HBLANK_B 0xe1004
  3095. #define _TRANS_HSYNC_B 0xe1008
  3096. #define _TRANS_VTOTAL_B 0xe100c
  3097. #define _TRANS_VBLANK_B 0xe1010
  3098. #define _TRANS_VSYNC_B 0xe1014
  3099. #define _TRANS_VSYNCSHIFT_B 0xe1028
  3100. #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
  3101. #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
  3102. #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
  3103. #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
  3104. #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
  3105. #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
  3106. #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \
  3107. _TRANS_VSYNCSHIFT_B)
  3108. #define _TRANSB_DATA_M1 0xe1030
  3109. #define _TRANSB_DATA_N1 0xe1034
  3110. #define _TRANSB_DATA_M2 0xe1038
  3111. #define _TRANSB_DATA_N2 0xe103c
  3112. #define _TRANSB_DP_LINK_M1 0xe1040
  3113. #define _TRANSB_DP_LINK_N1 0xe1044
  3114. #define _TRANSB_DP_LINK_M2 0xe1048
  3115. #define _TRANSB_DP_LINK_N2 0xe104c
  3116. #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
  3117. #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
  3118. #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
  3119. #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
  3120. #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
  3121. #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
  3122. #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
  3123. #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
  3124. #define _TRANSACONF 0xf0008
  3125. #define _TRANSBCONF 0xf1008
  3126. #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
  3127. #define TRANS_DISABLE (0<<31)
  3128. #define TRANS_ENABLE (1<<31)
  3129. #define TRANS_STATE_MASK (1<<30)
  3130. #define TRANS_STATE_DISABLE (0<<30)
  3131. #define TRANS_STATE_ENABLE (1<<30)
  3132. #define TRANS_FSYNC_DELAY_HB1 (0<<27)
  3133. #define TRANS_FSYNC_DELAY_HB2 (1<<27)
  3134. #define TRANS_FSYNC_DELAY_HB3 (2<<27)
  3135. #define TRANS_FSYNC_DELAY_HB4 (3<<27)
  3136. #define TRANS_DP_AUDIO_ONLY (1<<26)
  3137. #define TRANS_DP_VIDEO_AUDIO (0<<26)
  3138. #define TRANS_INTERLACE_MASK (7<<21)
  3139. #define TRANS_PROGRESSIVE (0<<21)
  3140. #define TRANS_INTERLACED (3<<21)
  3141. #define TRANS_LEGACY_INTERLACED_ILK (2<<21)
  3142. #define TRANS_8BPC (0<<5)
  3143. #define TRANS_10BPC (1<<5)
  3144. #define TRANS_6BPC (2<<5)
  3145. #define TRANS_12BPC (3<<5)
  3146. #define _TRANSA_CHICKEN2 0xf0064
  3147. #define _TRANSB_CHICKEN2 0xf1064
  3148. #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
  3149. #define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
  3150. #define SOUTH_CHICKEN1 0xc2000
  3151. #define FDIA_PHASE_SYNC_SHIFT_OVR 19
  3152. #define FDIA_PHASE_SYNC_SHIFT_EN 18
  3153. #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
  3154. #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
  3155. #define SOUTH_CHICKEN2 0xc2004
  3156. #define DPLS_EDP_PPS_FIX_DIS (1<<0)
  3157. #define _FDI_RXA_CHICKEN 0xc200c
  3158. #define _FDI_RXB_CHICKEN 0xc2010
  3159. #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
  3160. #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
  3161. #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
  3162. #define SOUTH_DSPCLK_GATE_D 0xc2020
  3163. #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
  3164. /* CPU: FDI_TX */
  3165. #define _FDI_TXA_CTL 0x60100
  3166. #define _FDI_TXB_CTL 0x61100
  3167. #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
  3168. #define FDI_TX_DISABLE (0<<31)
  3169. #define FDI_TX_ENABLE (1<<31)
  3170. #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
  3171. #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
  3172. #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
  3173. #define FDI_LINK_TRAIN_NONE (3<<28)
  3174. #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
  3175. #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
  3176. #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
  3177. #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
  3178. #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
  3179. #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
  3180. #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
  3181. #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
  3182. /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
  3183. SNB has different settings. */
  3184. /* SNB A-stepping */
  3185. #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
  3186. #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
  3187. #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
  3188. #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
  3189. /* SNB B-stepping */
  3190. #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
  3191. #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
  3192. #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
  3193. #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
  3194. #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
  3195. #define FDI_DP_PORT_WIDTH_X1 (0<<19)
  3196. #define FDI_DP_PORT_WIDTH_X2 (1<<19)
  3197. #define FDI_DP_PORT_WIDTH_X3 (2<<19)
  3198. #define FDI_DP_PORT_WIDTH_X4 (3<<19)
  3199. #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
  3200. /* Ironlake: hardwired to 1 */
  3201. #define FDI_TX_PLL_ENABLE (1<<14)
  3202. /* Ivybridge has different bits for lolz */
  3203. #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
  3204. #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
  3205. #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
  3206. #define FDI_LINK_TRAIN_NONE_IVB (3<<8)
  3207. /* both Tx and Rx */
  3208. #define FDI_COMPOSITE_SYNC (1<<11)
  3209. #define FDI_LINK_TRAIN_AUTO (1<<10)
  3210. #define FDI_SCRAMBLING_ENABLE (0<<7)
  3211. #define FDI_SCRAMBLING_DISABLE (1<<7)
  3212. /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
  3213. #define _FDI_RXA_CTL 0xf000c
  3214. #define _FDI_RXB_CTL 0xf100c
  3215. #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
  3216. #define FDI_RX_ENABLE (1<<31)
  3217. /* train, dp width same as FDI_TX */
  3218. #define FDI_FS_ERRC_ENABLE (1<<27)
  3219. #define FDI_FE_ERRC_ENABLE (1<<26)
  3220. #define FDI_DP_PORT_WIDTH_X8 (7<<19)
  3221. #define FDI_8BPC (0<<16)
  3222. #define FDI_10BPC (1<<16)
  3223. #define FDI_6BPC (2<<16)
  3224. #define FDI_12BPC (3<<16)
  3225. #define FDI_LINK_REVERSE_OVERWRITE (1<<15)
  3226. #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
  3227. #define FDI_RX_PLL_ENABLE (1<<13)
  3228. #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
  3229. #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
  3230. #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
  3231. #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
  3232. #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
  3233. #define FDI_PCDCLK (1<<4)
  3234. /* CPT */
  3235. #define FDI_AUTO_TRAINING (1<<10)
  3236. #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
  3237. #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
  3238. #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
  3239. #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
  3240. #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
  3241. #define _FDI_RXA_MISC 0xf0010
  3242. #define _FDI_RXB_MISC 0xf1010
  3243. #define _FDI_RXA_TUSIZE1 0xf0030
  3244. #define _FDI_RXA_TUSIZE2 0xf0038
  3245. #define _FDI_RXB_TUSIZE1 0xf1030
  3246. #define _FDI_RXB_TUSIZE2 0xf1038
  3247. #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
  3248. #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
  3249. #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
  3250. /* FDI_RX interrupt register format */
  3251. #define FDI_RX_INTER_LANE_ALIGN (1<<10)
  3252. #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
  3253. #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
  3254. #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
  3255. #define FDI_RX_FS_CODE_ERR (1<<6)
  3256. #define FDI_RX_FE_CODE_ERR (1<<5)
  3257. #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
  3258. #define FDI_RX_HDCP_LINK_FAIL (1<<3)
  3259. #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
  3260. #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
  3261. #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
  3262. #define _FDI_RXA_IIR 0xf0014
  3263. #define _FDI_RXA_IMR 0xf0018
  3264. #define _FDI_RXB_IIR 0xf1014
  3265. #define _FDI_RXB_IMR 0xf1018
  3266. #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
  3267. #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
  3268. #define FDI_PLL_CTL_1 0xfe000
  3269. #define FDI_PLL_CTL_2 0xfe004
  3270. /* CRT */
  3271. #define PCH_ADPA 0xe1100
  3272. #define ADPA_TRANS_SELECT_MASK (1<<30)
  3273. #define ADPA_TRANS_A_SELECT 0
  3274. #define ADPA_TRANS_B_SELECT (1<<30)
  3275. #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
  3276. #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
  3277. #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
  3278. #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
  3279. #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
  3280. #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
  3281. #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
  3282. #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
  3283. #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
  3284. #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
  3285. #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
  3286. #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
  3287. #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
  3288. #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
  3289. #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
  3290. #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
  3291. #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
  3292. #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
  3293. #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
  3294. /* or SDVOB */
  3295. #define HDMIB 0xe1140
  3296. #define PORT_ENABLE (1 << 31)
  3297. #define TRANSCODER(pipe) ((pipe) << 30)
  3298. #define TRANSCODER_CPT(pipe) ((pipe) << 29)
  3299. #define TRANSCODER_MASK (1 << 30)
  3300. #define TRANSCODER_MASK_CPT (3 << 29)
  3301. #define COLOR_FORMAT_8bpc (0)
  3302. #define COLOR_FORMAT_12bpc (3 << 26)
  3303. #define SDVOB_HOTPLUG_ENABLE (1 << 23)
  3304. #define SDVO_ENCODING (0)
  3305. #define TMDS_ENCODING (2 << 10)
  3306. #define NULL_PACKET_VSYNC_ENABLE (1 << 9)
  3307. /* CPT */
  3308. #define HDMI_MODE_SELECT (1 << 9)
  3309. #define DVI_MODE_SELECT (0)
  3310. #define SDVOB_BORDER_ENABLE (1 << 7)
  3311. #define AUDIO_ENABLE (1 << 6)
  3312. #define VSYNC_ACTIVE_HIGH (1 << 4)
  3313. #define HSYNC_ACTIVE_HIGH (1 << 3)
  3314. #define PORT_DETECTED (1 << 2)
  3315. /* PCH SDVOB multiplex with HDMIB */
  3316. #define PCH_SDVOB HDMIB
  3317. #define HDMIC 0xe1150
  3318. #define HDMID 0xe1160
  3319. #define PCH_LVDS 0xe1180
  3320. #define LVDS_DETECTED (1 << 1)
  3321. #define BLC_PWM_CPU_CTL2 0x48250
  3322. #define PWM_ENABLE (1 << 31)
  3323. #define PWM_PIPE_A (0 << 29)
  3324. #define PWM_PIPE_B (1 << 29)
  3325. #define BLC_PWM_CPU_CTL 0x48254
  3326. #define BLC_PWM_PCH_CTL1 0xc8250
  3327. #define PWM_PCH_ENABLE (1 << 31)
  3328. #define PWM_POLARITY_ACTIVE_LOW (1 << 29)
  3329. #define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
  3330. #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
  3331. #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
  3332. #define BLC_PWM_PCH_CTL2 0xc8254
  3333. #define PCH_PP_STATUS 0xc7200
  3334. #define PCH_PP_CONTROL 0xc7204
  3335. #define PANEL_UNLOCK_REGS (0xabcd << 16)
  3336. #define PANEL_UNLOCK_MASK (0xffff << 16)
  3337. #define EDP_FORCE_VDD (1 << 3)
  3338. #define EDP_BLC_ENABLE (1 << 2)
  3339. #define PANEL_POWER_RESET (1 << 1)
  3340. #define PANEL_POWER_OFF (0 << 0)
  3341. #define PANEL_POWER_ON (1 << 0)
  3342. #define PCH_PP_ON_DELAYS 0xc7208
  3343. #define PANEL_PORT_SELECT_MASK (3 << 30)
  3344. #define PANEL_PORT_SELECT_LVDS (0 << 30)
  3345. #define PANEL_PORT_SELECT_DPA (1 << 30)
  3346. #define EDP_PANEL (1 << 30)
  3347. #define PANEL_PORT_SELECT_DPC (2 << 30)
  3348. #define PANEL_PORT_SELECT_DPD (3 << 30)
  3349. #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
  3350. #define PANEL_POWER_UP_DELAY_SHIFT 16
  3351. #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
  3352. #define PANEL_LIGHT_ON_DELAY_SHIFT 0
  3353. #define PCH_PP_OFF_DELAYS 0xc720c
  3354. #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
  3355. #define PANEL_POWER_DOWN_DELAY_SHIFT 16
  3356. #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
  3357. #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
  3358. #define PCH_PP_DIVISOR 0xc7210
  3359. #define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
  3360. #define PP_REFERENCE_DIVIDER_SHIFT 8
  3361. #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
  3362. #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
  3363. #define PCH_DP_B 0xe4100
  3364. #define PCH_DPB_AUX_CH_CTL 0xe4110
  3365. #define PCH_DPB_AUX_CH_DATA1 0xe4114
  3366. #define PCH_DPB_AUX_CH_DATA2 0xe4118
  3367. #define PCH_DPB_AUX_CH_DATA3 0xe411c
  3368. #define PCH_DPB_AUX_CH_DATA4 0xe4120
  3369. #define PCH_DPB_AUX_CH_DATA5 0xe4124
  3370. #define PCH_DP_C 0xe4200
  3371. #define PCH_DPC_AUX_CH_CTL 0xe4210
  3372. #define PCH_DPC_AUX_CH_DATA1 0xe4214
  3373. #define PCH_DPC_AUX_CH_DATA2 0xe4218
  3374. #define PCH_DPC_AUX_CH_DATA3 0xe421c
  3375. #define PCH_DPC_AUX_CH_DATA4 0xe4220
  3376. #define PCH_DPC_AUX_CH_DATA5 0xe4224
  3377. #define PCH_DP_D 0xe4300
  3378. #define PCH_DPD_AUX_CH_CTL 0xe4310
  3379. #define PCH_DPD_AUX_CH_DATA1 0xe4314
  3380. #define PCH_DPD_AUX_CH_DATA2 0xe4318
  3381. #define PCH_DPD_AUX_CH_DATA3 0xe431c
  3382. #define PCH_DPD_AUX_CH_DATA4 0xe4320
  3383. #define PCH_DPD_AUX_CH_DATA5 0xe4324
  3384. /* CPT */
  3385. #define PORT_TRANS_A_SEL_CPT 0
  3386. #define PORT_TRANS_B_SEL_CPT (1<<29)
  3387. #define PORT_TRANS_C_SEL_CPT (2<<29)
  3388. #define PORT_TRANS_SEL_MASK (3<<29)
  3389. #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
  3390. #define TRANS_DP_CTL_A 0xe0300
  3391. #define TRANS_DP_CTL_B 0xe1300
  3392. #define TRANS_DP_CTL_C 0xe2300
  3393. #define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
  3394. #define TRANS_DP_OUTPUT_ENABLE (1<<31)
  3395. #define TRANS_DP_PORT_SEL_B (0<<29)
  3396. #define TRANS_DP_PORT_SEL_C (1<<29)
  3397. #define TRANS_DP_PORT_SEL_D (2<<29)
  3398. #define TRANS_DP_PORT_SEL_NONE (3<<29)
  3399. #define TRANS_DP_PORT_SEL_MASK (3<<29)
  3400. #define TRANS_DP_AUDIO_ONLY (1<<26)
  3401. #define TRANS_DP_ENH_FRAMING (1<<18)
  3402. #define TRANS_DP_8BPC (0<<9)
  3403. #define TRANS_DP_10BPC (1<<9)
  3404. #define TRANS_DP_6BPC (2<<9)
  3405. #define TRANS_DP_12BPC (3<<9)
  3406. #define TRANS_DP_BPC_MASK (3<<9)
  3407. #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
  3408. #define TRANS_DP_VSYNC_ACTIVE_LOW 0
  3409. #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
  3410. #define TRANS_DP_HSYNC_ACTIVE_LOW 0
  3411. #define TRANS_DP_SYNC_MASK (3<<3)
  3412. /* SNB eDP training params */
  3413. /* SNB A-stepping */
  3414. #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
  3415. #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
  3416. #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
  3417. #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
  3418. /* SNB B-stepping */
  3419. #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
  3420. #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
  3421. #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
  3422. #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
  3423. #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
  3424. #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
  3425. /* IVB */
  3426. #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
  3427. #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
  3428. #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
  3429. #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
  3430. #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
  3431. #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
  3432. #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
  3433. /* legacy values */
  3434. #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
  3435. #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
  3436. #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
  3437. #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
  3438. #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
  3439. #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
  3440. #define FORCEWAKE 0xA18C
  3441. #define FORCEWAKE_ACK 0x130090
  3442. #define FORCEWAKE_MT 0xa188 /* multi-threaded */
  3443. #define FORCEWAKE_MT_ACK 0x130040
  3444. #define ECOBUS 0xa180
  3445. #define FORCEWAKE_MT_ENABLE (1<<5)
  3446. #define GTFIFODBG 0x120000
  3447. #define GT_FIFO_CPU_ERROR_MASK 7
  3448. #define GT_FIFO_OVFERR (1<<2)
  3449. #define GT_FIFO_IAWRERR (1<<1)
  3450. #define GT_FIFO_IARDERR (1<<0)
  3451. #define GT_FIFO_FREE_ENTRIES 0x120008
  3452. #define GT_FIFO_NUM_RESERVED_ENTRIES 20
  3453. #define GEN6_UCGCTL1 0x9400
  3454. # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
  3455. #define GEN6_UCGCTL2 0x9404
  3456. # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
  3457. # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
  3458. # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
  3459. #define GEN6_RPNSWREQ 0xA008
  3460. #define GEN6_TURBO_DISABLE (1<<31)
  3461. #define GEN6_FREQUENCY(x) ((x)<<25)
  3462. #define GEN6_OFFSET(x) ((x)<<19)
  3463. #define GEN6_AGGRESSIVE_TURBO (0<<15)
  3464. #define GEN6_RC_VIDEO_FREQ 0xA00C
  3465. #define GEN6_RC_CONTROL 0xA090
  3466. #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
  3467. #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
  3468. #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
  3469. #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
  3470. #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
  3471. #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
  3472. #define GEN6_RC_CTL_HW_ENABLE (1<<31)
  3473. #define GEN6_RP_DOWN_TIMEOUT 0xA010
  3474. #define GEN6_RP_INTERRUPT_LIMITS 0xA014
  3475. #define GEN6_RPSTAT1 0xA01C
  3476. #define GEN6_CAGF_SHIFT 8
  3477. #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
  3478. #define GEN6_RP_CONTROL 0xA024
  3479. #define GEN6_RP_MEDIA_TURBO (1<<11)
  3480. #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
  3481. #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
  3482. #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
  3483. #define GEN6_RP_MEDIA_HW_MODE (1<<9)
  3484. #define GEN6_RP_MEDIA_SW_MODE (0<<9)
  3485. #define GEN6_RP_MEDIA_IS_GFX (1<<8)
  3486. #define GEN6_RP_ENABLE (1<<7)
  3487. #define GEN6_RP_UP_IDLE_MIN (0x1<<3)
  3488. #define GEN6_RP_UP_BUSY_AVG (0x2<<3)
  3489. #define GEN6_RP_UP_BUSY_CONT (0x4<<3)
  3490. #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
  3491. #define GEN6_RP_UP_THRESHOLD 0xA02C
  3492. #define GEN6_RP_DOWN_THRESHOLD 0xA030
  3493. #define GEN6_RP_CUR_UP_EI 0xA050
  3494. #define GEN6_CURICONT_MASK 0xffffff
  3495. #define GEN6_RP_CUR_UP 0xA054
  3496. #define GEN6_CURBSYTAVG_MASK 0xffffff
  3497. #define GEN6_RP_PREV_UP 0xA058
  3498. #define GEN6_RP_CUR_DOWN_EI 0xA05C
  3499. #define GEN6_CURIAVG_MASK 0xffffff
  3500. #define GEN6_RP_CUR_DOWN 0xA060
  3501. #define GEN6_RP_PREV_DOWN 0xA064
  3502. #define GEN6_RP_UP_EI 0xA068
  3503. #define GEN6_RP_DOWN_EI 0xA06C
  3504. #define GEN6_RP_IDLE_HYSTERSIS 0xA070
  3505. #define GEN6_RC_STATE 0xA094
  3506. #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
  3507. #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
  3508. #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
  3509. #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
  3510. #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
  3511. #define GEN6_RC_SLEEP 0xA0B0
  3512. #define GEN6_RC1e_THRESHOLD 0xA0B4
  3513. #define GEN6_RC6_THRESHOLD 0xA0B8
  3514. #define GEN6_RC6p_THRESHOLD 0xA0BC
  3515. #define GEN6_RC6pp_THRESHOLD 0xA0C0
  3516. #define GEN6_PMINTRMSK 0xA168
  3517. #define GEN6_PMISR 0x44020
  3518. #define GEN6_PMIMR 0x44024 /* rps_lock */
  3519. #define GEN6_PMIIR 0x44028
  3520. #define GEN6_PMIER 0x4402C
  3521. #define GEN6_PM_MBOX_EVENT (1<<25)
  3522. #define GEN6_PM_THERMAL_EVENT (1<<24)
  3523. #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
  3524. #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
  3525. #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
  3526. #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
  3527. #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
  3528. #define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
  3529. GEN6_PM_RP_DOWN_THRESHOLD | \
  3530. GEN6_PM_RP_DOWN_TIMEOUT)
  3531. #define GEN6_PCODE_MAILBOX 0x138124
  3532. #define GEN6_PCODE_READY (1<<31)
  3533. #define GEN6_READ_OC_PARAMS 0xc
  3534. #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
  3535. #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
  3536. #define GEN6_PCODE_DATA 0x138128
  3537. #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
  3538. #define GEN6_GT_CORE_STATUS 0x138060
  3539. #define GEN6_CORE_CPD_STATE_MASK (7<<4)
  3540. #define GEN6_RCn_MASK 7
  3541. #define GEN6_RC0 0
  3542. #define GEN6_RC3 2
  3543. #define GEN6_RC6 3
  3544. #define GEN6_RC7 4
  3545. #define G4X_AUD_VID_DID 0x62020
  3546. #define INTEL_AUDIO_DEVCL 0x808629FB
  3547. #define INTEL_AUDIO_DEVBLC 0x80862801
  3548. #define INTEL_AUDIO_DEVCTG 0x80862802
  3549. #define G4X_AUD_CNTL_ST 0x620B4
  3550. #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
  3551. #define G4X_ELDV_DEVCTG (1 << 14)
  3552. #define G4X_ELD_ADDR (0xf << 5)
  3553. #define G4X_ELD_ACK (1 << 4)
  3554. #define G4X_HDMIW_HDMIEDID 0x6210C
  3555. #define IBX_HDMIW_HDMIEDID_A 0xE2050
  3556. #define IBX_AUD_CNTL_ST_A 0xE20B4
  3557. #define IBX_ELD_BUFFER_SIZE (0x1f << 10)
  3558. #define IBX_ELD_ADDRESS (0x1f << 5)
  3559. #define IBX_ELD_ACK (1 << 4)
  3560. #define IBX_AUD_CNTL_ST2 0xE20C0
  3561. #define IBX_ELD_VALIDB (1 << 0)
  3562. #define IBX_CP_READYB (1 << 1)
  3563. #define CPT_HDMIW_HDMIEDID_A 0xE5050
  3564. #define CPT_AUD_CNTL_ST_A 0xE50B4
  3565. #define CPT_AUD_CNTRL_ST2 0xE50C0
  3566. /* These are the 4 32-bit write offset registers for each stream
  3567. * output buffer. It determines the offset from the
  3568. * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
  3569. */
  3570. #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
  3571. #define IBX_AUD_CONFIG_A 0xe2000
  3572. #define CPT_AUD_CONFIG_A 0xe5000
  3573. #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
  3574. #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
  3575. #define AUD_CONFIG_UPPER_N_SHIFT 20
  3576. #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
  3577. #define AUD_CONFIG_LOWER_N_SHIFT 4
  3578. #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
  3579. #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
  3580. #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
  3581. #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
  3582. #endif /* _I915_REG_H_ */