oaktrail_lvds.c 14 KB

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  1. /*
  2. * Copyright © 2006-2009 Intel Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License along with
  14. * this program; if not, write to the Free Software Foundation, Inc.,
  15. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16. *
  17. * Authors:
  18. * Eric Anholt <eric@anholt.net>
  19. * Dave Airlie <airlied@linux.ie>
  20. * Jesse Barnes <jesse.barnes@intel.com>
  21. */
  22. #include <linux/i2c.h>
  23. #include <drm/drmP.h>
  24. #include <asm/mrst.h>
  25. #include "intel_bios.h"
  26. #include "psb_drv.h"
  27. #include "psb_intel_drv.h"
  28. #include "psb_intel_reg.h"
  29. #include "power.h"
  30. #include <linux/pm_runtime.h>
  31. /* The max/min PWM frequency in BPCR[31:17] - */
  32. /* The smallest number is 1 (not 0) that can fit in the
  33. * 15-bit field of the and then*/
  34. /* shifts to the left by one bit to get the actual 16-bit
  35. * value that the 15-bits correspond to.*/
  36. #define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
  37. #define BRIGHTNESS_MAX_LEVEL 100
  38. /**
  39. * Sets the power state for the panel.
  40. */
  41. static void oaktrail_lvds_set_power(struct drm_device *dev,
  42. struct psb_intel_encoder *psb_intel_encoder,
  43. bool on)
  44. {
  45. u32 pp_status;
  46. struct drm_psb_private *dev_priv = dev->dev_private;
  47. if (!gma_power_begin(dev, true))
  48. return;
  49. if (on) {
  50. REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
  51. POWER_TARGET_ON);
  52. do {
  53. pp_status = REG_READ(PP_STATUS);
  54. } while ((pp_status & (PP_ON | PP_READY)) == PP_READY);
  55. dev_priv->is_lvds_on = true;
  56. if (dev_priv->ops->lvds_bl_power)
  57. dev_priv->ops->lvds_bl_power(dev, true);
  58. } else {
  59. if (dev_priv->ops->lvds_bl_power)
  60. dev_priv->ops->lvds_bl_power(dev, false);
  61. REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
  62. ~POWER_TARGET_ON);
  63. do {
  64. pp_status = REG_READ(PP_STATUS);
  65. } while (pp_status & PP_ON);
  66. dev_priv->is_lvds_on = false;
  67. pm_request_idle(&dev->pdev->dev);
  68. }
  69. gma_power_end(dev);
  70. }
  71. static void oaktrail_lvds_dpms(struct drm_encoder *encoder, int mode)
  72. {
  73. struct drm_device *dev = encoder->dev;
  74. struct psb_intel_encoder *psb_intel_encoder =
  75. to_psb_intel_encoder(encoder);
  76. if (mode == DRM_MODE_DPMS_ON)
  77. oaktrail_lvds_set_power(dev, psb_intel_encoder, true);
  78. else
  79. oaktrail_lvds_set_power(dev, psb_intel_encoder, false);
  80. /* XXX: We never power down the LVDS pairs. */
  81. }
  82. static void oaktrail_lvds_mode_set(struct drm_encoder *encoder,
  83. struct drm_display_mode *mode,
  84. struct drm_display_mode *adjusted_mode)
  85. {
  86. struct drm_device *dev = encoder->dev;
  87. struct drm_psb_private *dev_priv = dev->dev_private;
  88. struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
  89. struct drm_mode_config *mode_config = &dev->mode_config;
  90. struct drm_connector *connector = NULL;
  91. struct drm_crtc *crtc = encoder->crtc;
  92. u32 lvds_port;
  93. uint64_t v = DRM_MODE_SCALE_FULLSCREEN;
  94. if (!gma_power_begin(dev, true))
  95. return;
  96. /*
  97. * The LVDS pin pair will already have been turned on in the
  98. * psb_intel_crtc_mode_set since it has a large impact on the DPLL
  99. * settings.
  100. */
  101. lvds_port = (REG_READ(LVDS) &
  102. (~LVDS_PIPEB_SELECT)) |
  103. LVDS_PORT_EN |
  104. LVDS_BORDER_EN;
  105. /* If the firmware says dither on Moorestown, or the BIOS does
  106. on Oaktrail then enable dithering */
  107. if (mode_dev->panel_wants_dither || dev_priv->lvds_dither)
  108. lvds_port |= MRST_PANEL_8TO6_DITHER_ENABLE;
  109. REG_WRITE(LVDS, lvds_port);
  110. /* Find the connector we're trying to set up */
  111. list_for_each_entry(connector, &mode_config->connector_list, head) {
  112. if (!connector->encoder || connector->encoder->crtc != crtc)
  113. continue;
  114. }
  115. if (!connector) {
  116. DRM_ERROR("Couldn't find connector when setting mode");
  117. return;
  118. }
  119. drm_connector_property_get_value(
  120. connector,
  121. dev->mode_config.scaling_mode_property,
  122. &v);
  123. if (v == DRM_MODE_SCALE_NO_SCALE)
  124. REG_WRITE(PFIT_CONTROL, 0);
  125. else if (v == DRM_MODE_SCALE_ASPECT) {
  126. if ((mode->vdisplay != adjusted_mode->crtc_vdisplay) ||
  127. (mode->hdisplay != adjusted_mode->crtc_hdisplay)) {
  128. if ((adjusted_mode->crtc_hdisplay * mode->vdisplay) ==
  129. (mode->hdisplay * adjusted_mode->crtc_vdisplay))
  130. REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
  131. else if ((adjusted_mode->crtc_hdisplay *
  132. mode->vdisplay) > (mode->hdisplay *
  133. adjusted_mode->crtc_vdisplay))
  134. REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
  135. PFIT_SCALING_MODE_PILLARBOX);
  136. else
  137. REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
  138. PFIT_SCALING_MODE_LETTERBOX);
  139. } else
  140. REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
  141. } else /*(v == DRM_MODE_SCALE_FULLSCREEN)*/
  142. REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
  143. gma_power_end(dev);
  144. }
  145. static void oaktrail_lvds_prepare(struct drm_encoder *encoder)
  146. {
  147. struct drm_device *dev = encoder->dev;
  148. struct drm_psb_private *dev_priv = dev->dev_private;
  149. struct psb_intel_encoder *psb_intel_encoder =
  150. to_psb_intel_encoder(encoder);
  151. struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
  152. if (!gma_power_begin(dev, true))
  153. return;
  154. mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
  155. mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL &
  156. BACKLIGHT_DUTY_CYCLE_MASK);
  157. oaktrail_lvds_set_power(dev, psb_intel_encoder, false);
  158. gma_power_end(dev);
  159. }
  160. static u32 oaktrail_lvds_get_max_backlight(struct drm_device *dev)
  161. {
  162. struct drm_psb_private *dev_priv = dev->dev_private;
  163. u32 ret;
  164. if (gma_power_begin(dev, false)) {
  165. ret = ((REG_READ(BLC_PWM_CTL) &
  166. BACKLIGHT_MODULATION_FREQ_MASK) >>
  167. BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
  168. gma_power_end(dev);
  169. } else
  170. ret = ((dev_priv->regs.saveBLC_PWM_CTL &
  171. BACKLIGHT_MODULATION_FREQ_MASK) >>
  172. BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
  173. return ret;
  174. }
  175. static void oaktrail_lvds_commit(struct drm_encoder *encoder)
  176. {
  177. struct drm_device *dev = encoder->dev;
  178. struct drm_psb_private *dev_priv = dev->dev_private;
  179. struct psb_intel_encoder *psb_intel_encoder =
  180. to_psb_intel_encoder(encoder);
  181. struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
  182. if (mode_dev->backlight_duty_cycle == 0)
  183. mode_dev->backlight_duty_cycle =
  184. oaktrail_lvds_get_max_backlight(dev);
  185. oaktrail_lvds_set_power(dev, psb_intel_encoder, true);
  186. }
  187. static const struct drm_encoder_helper_funcs oaktrail_lvds_helper_funcs = {
  188. .dpms = oaktrail_lvds_dpms,
  189. .mode_fixup = psb_intel_lvds_mode_fixup,
  190. .prepare = oaktrail_lvds_prepare,
  191. .mode_set = oaktrail_lvds_mode_set,
  192. .commit = oaktrail_lvds_commit,
  193. };
  194. static struct drm_display_mode lvds_configuration_modes[] = {
  195. /* hard coded fixed mode for TPO LTPS LPJ040K001A */
  196. { DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 33264, 800, 836,
  197. 846, 1056, 0, 480, 489, 491, 525, 0, 0) },
  198. /* hard coded fixed mode for LVDS 800x480 */
  199. { DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 30994, 800, 801,
  200. 802, 1024, 0, 480, 481, 482, 525, 0, 0) },
  201. /* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */
  202. { DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 53990, 1024, 1072,
  203. 1104, 1184, 0, 600, 603, 604, 608, 0, 0) },
  204. /* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */
  205. { DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 53990, 1024, 1104,
  206. 1136, 1184, 0, 600, 603, 604, 608, 0, 0) },
  207. /* hard coded fixed mode for Sharp wsvga LVDS 1024x600 */
  208. { DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 48885, 1024, 1124,
  209. 1204, 1312, 0, 600, 607, 610, 621, 0, 0) },
  210. /* hard coded fixed mode for LVDS 1024x768 */
  211. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
  212. 1184, 1344, 0, 768, 771, 777, 806, 0, 0) },
  213. /* hard coded fixed mode for LVDS 1366x768 */
  214. { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 77500, 1366, 1430,
  215. 1558, 1664, 0, 768, 769, 770, 776, 0, 0) },
  216. };
  217. /* Returns the panel fixed mode from configuration. */
  218. static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev,
  219. struct psb_intel_mode_device *mode_dev)
  220. {
  221. struct drm_display_mode *mode = NULL;
  222. struct drm_psb_private *dev_priv = dev->dev_private;
  223. struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD;
  224. mode_dev->panel_fixed_mode = NULL;
  225. /* Use the firmware provided data on Moorestown */
  226. if (dev_priv->vbt_data.size != 0x00) { /*if non-zero, then use vbt*/
  227. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  228. if (!mode)
  229. return;
  230. mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo;
  231. mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo;
  232. mode->hsync_start = mode->hdisplay + \
  233. ((ti->hsync_offset_hi << 8) | \
  234. ti->hsync_offset_lo);
  235. mode->hsync_end = mode->hsync_start + \
  236. ((ti->hsync_pulse_width_hi << 8) | \
  237. ti->hsync_pulse_width_lo);
  238. mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \
  239. ti->hblank_lo);
  240. mode->vsync_start = \
  241. mode->vdisplay + ((ti->vsync_offset_hi << 4) | \
  242. ti->vsync_offset_lo);
  243. mode->vsync_end = \
  244. mode->vsync_start + ((ti->vsync_pulse_width_hi << 4) | \
  245. ti->vsync_pulse_width_lo);
  246. mode->vtotal = mode->vdisplay + \
  247. ((ti->vblank_hi << 8) | ti->vblank_lo);
  248. mode->clock = ti->pixel_clock * 10;
  249. #if 0
  250. printk(KERN_INFO "hdisplay is %d\n", mode->hdisplay);
  251. printk(KERN_INFO "vdisplay is %d\n", mode->vdisplay);
  252. printk(KERN_INFO "HSS is %d\n", mode->hsync_start);
  253. printk(KERN_INFO "HSE is %d\n", mode->hsync_end);
  254. printk(KERN_INFO "htotal is %d\n", mode->htotal);
  255. printk(KERN_INFO "VSS is %d\n", mode->vsync_start);
  256. printk(KERN_INFO "VSE is %d\n", mode->vsync_end);
  257. printk(KERN_INFO "vtotal is %d\n", mode->vtotal);
  258. printk(KERN_INFO "clock is %d\n", mode->clock);
  259. #endif
  260. mode_dev->panel_fixed_mode = mode;
  261. }
  262. /* Use the BIOS VBT mode if available */
  263. if (mode_dev->panel_fixed_mode == NULL && mode_dev->vbt_mode)
  264. mode_dev->panel_fixed_mode = drm_mode_duplicate(dev,
  265. mode_dev->vbt_mode);
  266. /* Then try the LVDS VBT mode */
  267. if (mode_dev->panel_fixed_mode == NULL)
  268. if (dev_priv->lfp_lvds_vbt_mode)
  269. mode_dev->panel_fixed_mode =
  270. drm_mode_duplicate(dev,
  271. dev_priv->lfp_lvds_vbt_mode);
  272. /* Then guess */
  273. if (mode_dev->panel_fixed_mode == NULL)
  274. mode_dev->panel_fixed_mode
  275. = drm_mode_duplicate(dev, &lvds_configuration_modes[2]);
  276. drm_mode_set_name(mode_dev->panel_fixed_mode);
  277. drm_mode_set_crtcinfo(mode_dev->panel_fixed_mode, 0);
  278. }
  279. /**
  280. * oaktrail_lvds_init - setup LVDS connectors on this device
  281. * @dev: drm device
  282. *
  283. * Create the connector, register the LVDS DDC bus, and try to figure out what
  284. * modes we can display on the LVDS panel (if present).
  285. */
  286. void oaktrail_lvds_init(struct drm_device *dev,
  287. struct psb_intel_mode_device *mode_dev)
  288. {
  289. struct psb_intel_encoder *psb_intel_encoder;
  290. struct psb_intel_connector *psb_intel_connector;
  291. struct drm_connector *connector;
  292. struct drm_encoder *encoder;
  293. struct drm_psb_private *dev_priv = dev->dev_private;
  294. struct edid *edid;
  295. struct i2c_adapter *i2c_adap;
  296. struct drm_display_mode *scan; /* *modes, *bios_mode; */
  297. psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL);
  298. if (!psb_intel_encoder)
  299. return;
  300. psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL);
  301. if (!psb_intel_connector)
  302. goto failed_connector;
  303. connector = &psb_intel_connector->base;
  304. encoder = &psb_intel_encoder->base;
  305. dev_priv->is_lvds_on = true;
  306. drm_connector_init(dev, connector,
  307. &psb_intel_lvds_connector_funcs,
  308. DRM_MODE_CONNECTOR_LVDS);
  309. drm_encoder_init(dev, encoder, &psb_intel_lvds_enc_funcs,
  310. DRM_MODE_ENCODER_LVDS);
  311. psb_intel_connector_attach_encoder(psb_intel_connector,
  312. psb_intel_encoder);
  313. psb_intel_encoder->type = INTEL_OUTPUT_LVDS;
  314. drm_encoder_helper_add(encoder, &oaktrail_lvds_helper_funcs);
  315. drm_connector_helper_add(connector,
  316. &psb_intel_lvds_connector_helper_funcs);
  317. connector->display_info.subpixel_order = SubPixelHorizontalRGB;
  318. connector->interlace_allowed = false;
  319. connector->doublescan_allowed = false;
  320. drm_connector_attach_property(connector,
  321. dev->mode_config.scaling_mode_property,
  322. DRM_MODE_SCALE_FULLSCREEN);
  323. drm_connector_attach_property(connector,
  324. dev_priv->backlight_property,
  325. BRIGHTNESS_MAX_LEVEL);
  326. mode_dev->panel_wants_dither = false;
  327. if (dev_priv->vbt_data.size != 0x00)
  328. mode_dev->panel_wants_dither = (dev_priv->gct_data.
  329. Panel_Port_Control & MRST_PANEL_8TO6_DITHER_ENABLE);
  330. if (dev_priv->lvds_dither)
  331. mode_dev->panel_wants_dither = 1;
  332. /*
  333. * LVDS discovery:
  334. * 1) check for EDID on DDC
  335. * 2) check for VBT data
  336. * 3) check to see if LVDS is already on
  337. * if none of the above, no panel
  338. * 4) make sure lid is open
  339. * if closed, act like it's not there for now
  340. */
  341. i2c_adap = i2c_get_adapter(dev_priv->ops->i2c_bus);
  342. if (i2c_adap == NULL)
  343. dev_err(dev->dev, "No ddc adapter available!\n");
  344. /*
  345. * Attempt to get the fixed panel mode from DDC. Assume that the
  346. * preferred mode is the right one.
  347. */
  348. if (i2c_adap) {
  349. edid = drm_get_edid(connector, i2c_adap);
  350. if (edid) {
  351. drm_mode_connector_update_edid_property(connector,
  352. edid);
  353. drm_add_edid_modes(connector, edid);
  354. kfree(edid);
  355. }
  356. list_for_each_entry(scan, &connector->probed_modes, head) {
  357. if (scan->type & DRM_MODE_TYPE_PREFERRED) {
  358. mode_dev->panel_fixed_mode =
  359. drm_mode_duplicate(dev, scan);
  360. goto out; /* FIXME: check for quirks */
  361. }
  362. }
  363. }
  364. /*
  365. * If we didn't get EDID, try geting panel timing
  366. * from configuration data
  367. */
  368. oaktrail_lvds_get_configuration_mode(dev, mode_dev);
  369. if (mode_dev->panel_fixed_mode) {
  370. mode_dev->panel_fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
  371. goto out; /* FIXME: check for quirks */
  372. }
  373. /* If we still don't have a mode after all that, give up. */
  374. if (!mode_dev->panel_fixed_mode) {
  375. dev_err(dev->dev, "Found no modes on the lvds, ignoring the LVDS\n");
  376. goto failed_find;
  377. }
  378. out:
  379. drm_sysfs_connector_add(connector);
  380. return;
  381. failed_find:
  382. dev_dbg(dev->dev, "No LVDS modes found, disabling.\n");
  383. if (psb_intel_encoder->ddc_bus)
  384. psb_intel_i2c_destroy(psb_intel_encoder->ddc_bus);
  385. /* failed_ddc: */
  386. drm_encoder_cleanup(encoder);
  387. drm_connector_cleanup(connector);
  388. kfree(psb_intel_connector);
  389. failed_connector:
  390. kfree(psb_intel_encoder);
  391. }