Accueil Explorer Aide
Connexion
ichrin
/
kernel_samsung_msm8974
Suivre 1
Voter 0
Fork 0
Fichiers Tickets 0 Pull Requests 0 Wiki
Aborescence: 6ab9bf52ed
Branches Tags
kernel_samsu...
/
drivers
/
crypto
/
tegra-aes.h

tegra-aes.h 4.2 KB
Historique Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104 
  1. /*
    2. 

  2.  * Copyright (c) 2010, NVIDIA Corporation.
    3. 

  3.  *
    4. 

  4.  * This program is free software; you can redistribute it and/or modify
    5. 

  5.  * it under the terms of the GNU General Public License as published by
    6. 

  6.  * the Free Software Foundation; either version 2 of the License, or
    7. 

  7.  * (at your option) any later version.
    8. 

  8.  *
    9. 

  9.  * This program is distributed in the hope that it will be useful, but WITHOUT
    10. 

  10.  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    11. 

  11.  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
    12. 

  12.  * more details.
    13. 

  13.  *
    14. 

  14.  * You should have received a copy of the GNU General Public License along
    15. 

  15.  * with this program; if not, write to the Free Software Foundation, Inc.,
    16. 

  16.  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
    17. 

  17.  */
    18. 

  18. 

  19. #ifndef __CRYPTODEV_TEGRA_AES_H
    20. 

  20. #define __CRYPTODEV_TEGRA_AES_H
    21. 

  21. 

  22. #define TEGRA_AES_ICMDQUE_WR			0x1000
    23. 

  23. #define TEGRA_AES_CMDQUE_CONTROL		0x1008
    24. 

  24. #define TEGRA_AES_INTR_STATUS			0x1018
    25. 

  25. #define TEGRA_AES_INT_ENB			0x1040
    26. 

  26. #define TEGRA_AES_CONFIG			0x1044
    27. 

  27. #define TEGRA_AES_IRAM_ACCESS_CFG		0x10A0
    28. 

  28. #define TEGRA_AES_SECURE_DEST_ADDR		0x1100
    29. 

  29. #define TEGRA_AES_SECURE_INPUT_SELECT		0x1104
    30. 

  30. #define TEGRA_AES_SECURE_CONFIG			0x1108
    31. 

  31. #define TEGRA_AES_SECURE_CONFIG_EXT		0x110C
    32. 

  32. #define TEGRA_AES_SECURE_SECURITY		0x1110
    33. 

  33. #define TEGRA_AES_SECURE_HASH_RESULT0		0x1120
    34. 

  34. #define TEGRA_AES_SECURE_HASH_RESULT1		0x1124
    35. 

  35. #define TEGRA_AES_SECURE_HASH_RESULT2		0x1128
    36. 

  36. #define TEGRA_AES_SECURE_HASH_RESULT3		0x112C
    37. 

  37. #define TEGRA_AES_SECURE_SEC_SEL0		0x1140
    38. 

  38. #define TEGRA_AES_SECURE_SEC_SEL1		0x1144
    39. 

  39. #define TEGRA_AES_SECURE_SEC_SEL2		0x1148
    40. 

  40. #define TEGRA_AES_SECURE_SEC_SEL3		0x114C
    41. 

  41. #define TEGRA_AES_SECURE_SEC_SEL4		0x1150
    42. 

  42. #define TEGRA_AES_SECURE_SEC_SEL5		0x1154
    43. 

  43. #define TEGRA_AES_SECURE_SEC_SEL6		0x1158
    44. 

  44. #define TEGRA_AES_SECURE_SEC_SEL7		0x115C
    45. 

  45. 

  46. /* interrupt status reg masks and shifts */
    47. 

  47. #define TEGRA_AES_ENGINE_BUSY_FIELD		BIT(0)
    48. 

  48. #define TEGRA_AES_ICQ_EMPTY_FIELD		BIT(3)
    49. 

  49. #define TEGRA_AES_DMA_BUSY_FIELD		BIT(23)
    50. 

  50. 

  51. /* secure select reg masks and shifts */
    52. 

  52. #define TEGRA_AES_SECURE_SEL0_KEYREAD_ENB0_FIELD	BIT(0)
    53. 

  53. 

  54. /* secure config ext masks and shifts */
    55. 

  55. #define TEGRA_AES_SECURE_KEY_SCH_DIS_FIELD	BIT(15)
    56. 

  56. 

  57. /* secure config masks and shifts */
    58. 

  58. #define TEGRA_AES_SECURE_KEY_INDEX_SHIFT	20
    59. 

  59. #define TEGRA_AES_SECURE_KEY_INDEX_FIELD	(0x1F << TEGRA_AES_SECURE_KEY_INDEX_SHIFT)
    60. 

  60. #define TEGRA_AES_SECURE_BLOCK_CNT_SHIFT	0
    61. 

  61. #define TEGRA_AES_SECURE_BLOCK_CNT_FIELD	(0xFFFFF << TEGRA_AES_SECURE_BLOCK_CNT_SHIFT)
    62. 

  62. 

  63. /* stream interface select masks and shifts */
    64. 

  64. #define TEGRA_AES_CMDQ_CTRL_UCMDQEN_FIELD	BIT(0)
    65. 

  65. #define TEGRA_AES_CMDQ_CTRL_ICMDQEN_FIELD	BIT(1)
    66. 

  66. #define TEGRA_AES_CMDQ_CTRL_SRC_STM_SEL_FIELD	BIT(4)
    67. 

  67. #define TEGRA_AES_CMDQ_CTRL_DST_STM_SEL_FIELD	BIT(5)
    68. 

  68. 

  69. /* config register masks and shifts */
    70. 

  70. #define TEGRA_AES_CONFIG_ENDIAN_ENB_FIELD	BIT(10)
    71. 

  71. #define TEGRA_AES_CONFIG_MODE_SEL_SHIFT		0
    72. 

  72. #define TEGRA_AES_CONFIG_MODE_SEL_FIELD		(0x1F << TEGRA_AES_CONFIG_MODE_SEL_SHIFT)
    73. 

  73. 

  74. /* extended config */
    75. 

  75. #define TEGRA_AES_SECURE_OFFSET_CNT_SHIFT	24
    76. 

  76. #define TEGRA_AES_SECURE_OFFSET_CNT_FIELD	(0xFF << TEGRA_AES_SECURE_OFFSET_CNT_SHIFT)
    77. 

  77. #define TEGRA_AES_SECURE_KEYSCHED_GEN_FIELD	BIT(15)
    78. 

  78. 

  79. /* init vector select */
    80. 

  80. #define TEGRA_AES_SECURE_IV_SELECT_SHIFT	10
    81. 

  81. #define TEGRA_AES_SECURE_IV_SELECT_FIELD	BIT(10)
    82. 

  82. 

  83. /* secure engine input */
    84. 

  84. #define TEGRA_AES_SECURE_INPUT_ALG_SEL_SHIFT	28
    85. 

  85. #define TEGRA_AES_SECURE_INPUT_ALG_SEL_FIELD	(0xF << TEGRA_AES_SECURE_INPUT_ALG_SEL_SHIFT)
    86. 

  86. #define TEGRA_AES_SECURE_INPUT_KEY_LEN_SHIFT	16
    87. 

  87. #define TEGRA_AES_SECURE_INPUT_KEY_LEN_FIELD	(0xFFF << TEGRA_AES_SECURE_INPUT_KEY_LEN_SHIFT)
    88. 

  88. #define TEGRA_AES_SECURE_RNG_ENB_FIELD		BIT(11)
    89. 

  89. #define TEGRA_AES_SECURE_CORE_SEL_SHIFT		9
    90. 

  90. #define TEGRA_AES_SECURE_CORE_SEL_FIELD		BIT(9)
    91. 

  91. #define TEGRA_AES_SECURE_VCTRAM_SEL_SHIFT	7
    92. 

  92. #define TEGRA_AES_SECURE_VCTRAM_SEL_FIELD	(0x3 << TEGRA_AES_SECURE_VCTRAM_SEL_SHIFT)
    93. 

  93. #define TEGRA_AES_SECURE_INPUT_SEL_SHIFT	5
    94. 

  94. #define TEGRA_AES_SECURE_INPUT_SEL_FIELD	(0x3 << TEGRA_AES_SECURE_INPUT_SEL_SHIFT)
    95. 

  95. #define TEGRA_AES_SECURE_XOR_POS_SHIFT		3
    96. 

  96. #define TEGRA_AES_SECURE_XOR_POS_FIELD		(0x3 << TEGRA_AES_SECURE_XOR_POS_SHIFT)
    97. 

  97. #define TEGRA_AES_SECURE_HASH_ENB_FIELD		BIT(2)
    98. 

  98. #define TEGRA_AES_SECURE_ON_THE_FLY_FIELD	BIT(0)
    99. 

  99. 

  100. /* interrupt error mask */
    101. 

  101. #define TEGRA_AES_INT_ERROR_MASK		0xFFF000
    102. 

  102. 

  103. #endif
    104. 

  104.