qcedev.c 58 KB

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  1. /* Qualcomm CE device driver.
  2. *
  3. * Copyright (c) 2010-2016, The Linux Foundation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 and
  7. * only version 2 as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <linux/mman.h>
  15. #include <linux/types.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/kernel.h>
  19. #include <linux/dmapool.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/init.h>
  23. #include <linux/module.h>
  24. #include <linux/fs.h>
  25. #include <linux/miscdevice.h>
  26. #include <linux/uaccess.h>
  27. #include <linux/debugfs.h>
  28. #include <linux/scatterlist.h>
  29. #include <linux/crypto.h>
  30. #include <crypto/hash.h>
  31. #include <linux/platform_data/qcom_crypto_device.h>
  32. #include <mach/scm.h>
  33. #include <mach/msm_bus.h>
  34. #include <linux/qcedev.h>
  35. #include "qcedevi.h"
  36. #include "qce.h"
  37. #define CACHE_LINE_SIZE 32
  38. #define CE_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE
  39. /* are FIPS integrity tests done ?? */
  40. bool is_fips_qcedev_integritytest_done;
  41. static uint8_t _std_init_vector_sha1_uint8[] = {
  42. 0x67, 0x45, 0x23, 0x01, 0xEF, 0xCD, 0xAB, 0x89,
  43. 0x98, 0xBA, 0xDC, 0xFE, 0x10, 0x32, 0x54, 0x76,
  44. 0xC3, 0xD2, 0xE1, 0xF0
  45. };
  46. /* standard initialization vector for SHA-256, source: FIPS 180-2 */
  47. static uint8_t _std_init_vector_sha256_uint8[] = {
  48. 0x6A, 0x09, 0xE6, 0x67, 0xBB, 0x67, 0xAE, 0x85,
  49. 0x3C, 0x6E, 0xF3, 0x72, 0xA5, 0x4F, 0xF5, 0x3A,
  50. 0x51, 0x0E, 0x52, 0x7F, 0x9B, 0x05, 0x68, 0x8C,
  51. 0x1F, 0x83, 0xD9, 0xAB, 0x5B, 0xE0, 0xCD, 0x19
  52. };
  53. static DEFINE_MUTEX(send_cmd_lock);
  54. static DEFINE_MUTEX(qcedev_sent_bw_req);
  55. static DEFINE_MUTEX(hash_access_lock);
  56. /*-------------------------------------------------------------------------
  57. * Resource Locking Service
  58. * ------------------------------------------------------------------------*/
  59. #define QCEDEV_CMD_ID 1
  60. #define QCEDEV_CE_LOCK_CMD 1
  61. #define QCEDEV_CE_UNLOCK_CMD 0
  62. #define NUM_RETRY 1000
  63. #define CE_BUSY 55
  64. static int qcedev_scm_cmd(int resource, int cmd, int *response)
  65. {
  66. #ifdef CONFIG_MSM_SCM
  67. struct {
  68. int resource;
  69. int cmd;
  70. } cmd_buf;
  71. cmd_buf.resource = resource;
  72. cmd_buf.cmd = cmd;
  73. return scm_call(SCM_SVC_TZ, QCEDEV_CMD_ID, &cmd_buf,
  74. sizeof(cmd_buf), response, sizeof(*response));
  75. #else
  76. return 0;
  77. #endif
  78. }
  79. static void qcedev_ce_high_bw_req(struct qcedev_control *podev,
  80. bool high_bw_req)
  81. {
  82. int ret = 0;
  83. mutex_lock(&qcedev_sent_bw_req);
  84. if (high_bw_req) {
  85. if (podev->high_bw_req_count == 0) {
  86. ret = qce_enable_clk(podev->qce);
  87. if (ret) {
  88. pr_err("%s Unable enable clk\n", __func__);
  89. mutex_unlock(&qcedev_sent_bw_req);
  90. return;
  91. }
  92. ret = msm_bus_scale_client_update_request(
  93. podev->bus_scale_handle, 1);
  94. if (ret) {
  95. pr_err("%s Unable to set to high bandwidth\n",
  96. __func__);
  97. ret = qce_disable_clk(podev->qce);
  98. mutex_unlock(&qcedev_sent_bw_req);
  99. return;
  100. }
  101. }
  102. podev->high_bw_req_count++;
  103. } else {
  104. if (podev->high_bw_req_count == 1) {
  105. ret = msm_bus_scale_client_update_request(
  106. podev->bus_scale_handle, 0);
  107. if (ret) {
  108. pr_err("%s Unable to set to low bandwidth\n",
  109. __func__);
  110. mutex_unlock(&qcedev_sent_bw_req);
  111. return;
  112. }
  113. ret = qce_disable_clk(podev->qce);
  114. if (ret) {
  115. pr_err("%s Unable disable clk\n", __func__);
  116. ret = msm_bus_scale_client_update_request(
  117. podev->bus_scale_handle, 1);
  118. if (ret)
  119. pr_err("%s Unable to set to high bandwidth\n",
  120. __func__);
  121. mutex_unlock(&qcedev_sent_bw_req);
  122. return;
  123. }
  124. }
  125. podev->high_bw_req_count--;
  126. }
  127. mutex_unlock(&qcedev_sent_bw_req);
  128. }
  129. static int qcedev_unlock_ce(struct qcedev_control *podev)
  130. {
  131. int ret = 0;
  132. mutex_lock(&send_cmd_lock);
  133. if (podev->ce_lock_count == 1) {
  134. int response = 0;
  135. if (qcedev_scm_cmd(podev->platform_support.shared_ce_resource,
  136. QCEDEV_CE_UNLOCK_CMD, &response)) {
  137. pr_err("Failed to release CE lock\n");
  138. ret = -EIO;
  139. }
  140. }
  141. if (ret == 0) {
  142. if (podev->ce_lock_count)
  143. podev->ce_lock_count--;
  144. else {
  145. /* We should never be here */
  146. ret = -EIO;
  147. pr_err("CE hardware is already unlocked\n");
  148. }
  149. }
  150. mutex_unlock(&send_cmd_lock);
  151. return ret;
  152. }
  153. static int qcedev_lock_ce(struct qcedev_control *podev)
  154. {
  155. int ret = 0;
  156. mutex_lock(&send_cmd_lock);
  157. if (podev->ce_lock_count == 0) {
  158. int response = -CE_BUSY;
  159. int i = 0;
  160. do {
  161. if (qcedev_scm_cmd(
  162. podev->platform_support.shared_ce_resource,
  163. QCEDEV_CE_LOCK_CMD, &response)) {
  164. response = -EINVAL;
  165. break;
  166. }
  167. } while ((response == -CE_BUSY) && (i++ < NUM_RETRY));
  168. if ((response == -CE_BUSY) && (i >= NUM_RETRY)) {
  169. ret = -EUSERS;
  170. } else {
  171. if (response < 0)
  172. ret = -EINVAL;
  173. }
  174. }
  175. if (ret == 0)
  176. podev->ce_lock_count++;
  177. mutex_unlock(&send_cmd_lock);
  178. return ret;
  179. }
  180. #define QCEDEV_MAGIC 0x56434544 /* "qced" */
  181. static long qcedev_ioctl(struct file *file, unsigned cmd, unsigned long arg);
  182. static int qcedev_open(struct inode *inode, struct file *file);
  183. static int qcedev_release(struct inode *inode, struct file *file);
  184. static int start_cipher_req(struct qcedev_control *podev);
  185. static int start_sha_req(struct qcedev_control *podev);
  186. static const struct file_operations qcedev_fops = {
  187. .owner = THIS_MODULE,
  188. .unlocked_ioctl = qcedev_ioctl,
  189. .open = qcedev_open,
  190. .release = qcedev_release,
  191. };
  192. static struct qcedev_control qce_dev[] = {
  193. {
  194. .miscdevice = {
  195. .minor = MISC_DYNAMIC_MINOR,
  196. .name = "qce",
  197. .fops = &qcedev_fops,
  198. },
  199. .magic = QCEDEV_MAGIC,
  200. },
  201. };
  202. #define MAX_QCE_DEVICE ARRAY_SIZE(qce_dev)
  203. #define DEBUG_MAX_FNAME 16
  204. #define DEBUG_MAX_RW_BUF 1024
  205. struct qcedev_stat {
  206. u32 qcedev_dec_success;
  207. u32 qcedev_dec_fail;
  208. u32 qcedev_enc_success;
  209. u32 qcedev_enc_fail;
  210. u32 qcedev_sha_success;
  211. u32 qcedev_sha_fail;
  212. };
  213. static struct qcedev_stat _qcedev_stat;
  214. static struct dentry *_debug_dent;
  215. static char _debug_read_buf[DEBUG_MAX_RW_BUF];
  216. static int _debug_qcedev;
  217. static struct qcedev_control *qcedev_minor_to_control(unsigned n)
  218. {
  219. int i;
  220. for (i = 0; i < MAX_QCE_DEVICE; i++) {
  221. if (qce_dev[i].miscdevice.minor == n)
  222. return &qce_dev[i];
  223. }
  224. return NULL;
  225. }
  226. static int qcedev_open(struct inode *inode, struct file *file)
  227. {
  228. struct qcedev_handle *handle;
  229. struct qcedev_control *podev;
  230. /* IF FIPS tests not passed, return error */
  231. if (((g_fips140_status == FIPS140_STATUS_FAIL) ||
  232. (g_fips140_status == FIPS140_STATUS_PASS_CRYPTO)) &&
  233. is_fips_qcedev_integritytest_done)
  234. return -ENXIO;
  235. podev = qcedev_minor_to_control(MINOR(inode->i_rdev));
  236. if (podev == NULL) {
  237. pr_err("%s: no such device %d\n", __func__,
  238. MINOR(inode->i_rdev));
  239. return -ENOENT;
  240. }
  241. handle = kzalloc(sizeof(struct qcedev_handle), GFP_KERNEL);
  242. if (handle == NULL) {
  243. pr_err("Failed to allocate memory %ld\n",
  244. PTR_ERR(handle));
  245. return -ENOMEM;
  246. }
  247. handle->cntl = podev;
  248. file->private_data = handle;
  249. if (podev->platform_support.bus_scale_table != NULL)
  250. qcedev_ce_high_bw_req(podev, true);
  251. return 0;
  252. }
  253. static int qcedev_release(struct inode *inode, struct file *file)
  254. {
  255. struct qcedev_control *podev;
  256. struct qcedev_handle *handle;
  257. handle = file->private_data;
  258. podev = handle->cntl;
  259. if (podev != NULL && podev->magic != QCEDEV_MAGIC) {
  260. pr_err("%s: invalid handle %p\n",
  261. __func__, podev);
  262. }
  263. kzfree(handle);
  264. file->private_data = NULL;
  265. if (podev != NULL && podev->platform_support.bus_scale_table != NULL)
  266. qcedev_ce_high_bw_req(podev, false);
  267. return 0;
  268. }
  269. static void req_done(unsigned long data)
  270. {
  271. struct qcedev_control *podev = (struct qcedev_control *)data;
  272. struct qcedev_async_req *areq;
  273. unsigned long flags = 0;
  274. struct qcedev_async_req *new_req = NULL;
  275. int ret = 0;
  276. spin_lock_irqsave(&podev->lock, flags);
  277. areq = podev->active_command;
  278. podev->active_command = NULL;
  279. again:
  280. if (!list_empty(&podev->ready_commands)) {
  281. new_req = container_of(podev->ready_commands.next,
  282. struct qcedev_async_req, list);
  283. list_del(&new_req->list);
  284. podev->active_command = new_req;
  285. new_req->err = 0;
  286. if (new_req->op_type == QCEDEV_CRYPTO_OPER_CIPHER)
  287. ret = start_cipher_req(podev);
  288. else
  289. ret = start_sha_req(podev);
  290. }
  291. spin_unlock_irqrestore(&podev->lock, flags);
  292. if (areq)
  293. complete(&areq->complete);
  294. if (new_req && ret) {
  295. complete(&new_req->complete);
  296. spin_lock_irqsave(&podev->lock, flags);
  297. podev->active_command = NULL;
  298. areq = NULL;
  299. ret = 0;
  300. new_req = NULL;
  301. goto again;
  302. }
  303. return;
  304. }
  305. void qcedev_sha_req_cb(void *cookie, unsigned char *digest,
  306. unsigned char *authdata, int ret)
  307. {
  308. struct qcedev_sha_req *areq;
  309. struct qcedev_control *pdev;
  310. struct qcedev_handle *handle;
  311. uint32_t *auth32 = (uint32_t *)authdata;
  312. areq = (struct qcedev_sha_req *) cookie;
  313. handle = (struct qcedev_handle *) areq->cookie;
  314. pdev = handle->cntl;
  315. if (digest)
  316. memcpy(&handle->sha_ctxt.digest[0], digest, 32);
  317. if (authdata) {
  318. handle->sha_ctxt.auth_data[0] = auth32[0];
  319. handle->sha_ctxt.auth_data[1] = auth32[1];
  320. handle->sha_ctxt.auth_data[2] = auth32[2];
  321. handle->sha_ctxt.auth_data[3] = auth32[3];
  322. }
  323. tasklet_schedule(&pdev->done_tasklet);
  324. };
  325. void qcedev_cipher_req_cb(void *cookie, unsigned char *icv,
  326. unsigned char *iv, int ret)
  327. {
  328. struct qcedev_cipher_req *areq;
  329. struct qcedev_handle *handle;
  330. struct qcedev_control *podev;
  331. struct qcedev_async_req *qcedev_areq;
  332. areq = (struct qcedev_cipher_req *) cookie;
  333. handle = (struct qcedev_handle *) areq->cookie;
  334. podev = handle->cntl;
  335. qcedev_areq = podev->active_command;
  336. if (iv)
  337. memcpy(&qcedev_areq->cipher_op_req.iv[0], iv,
  338. qcedev_areq->cipher_op_req.ivlen);
  339. tasklet_schedule(&podev->done_tasklet);
  340. };
  341. static int start_cipher_req(struct qcedev_control *podev)
  342. {
  343. struct qcedev_async_req *qcedev_areq;
  344. struct qce_req creq;
  345. int ret = 0;
  346. /* start the command on the podev->active_command */
  347. qcedev_areq = podev->active_command;
  348. qcedev_areq->cipher_req.cookie = qcedev_areq->handle;
  349. if (qcedev_areq->cipher_op_req.use_pmem == QCEDEV_USE_PMEM) {
  350. pr_err("%s: Use of PMEM is not supported\n", __func__);
  351. goto unsupported;
  352. }
  353. creq.pmem = NULL;
  354. switch (qcedev_areq->cipher_op_req.alg) {
  355. case QCEDEV_ALG_DES:
  356. creq.alg = CIPHER_ALG_DES;
  357. break;
  358. case QCEDEV_ALG_3DES:
  359. creq.alg = CIPHER_ALG_3DES;
  360. break;
  361. case QCEDEV_ALG_AES:
  362. creq.alg = CIPHER_ALG_AES;
  363. break;
  364. default:
  365. return -EINVAL;
  366. };
  367. switch (qcedev_areq->cipher_op_req.mode) {
  368. case QCEDEV_AES_MODE_CBC:
  369. case QCEDEV_DES_MODE_CBC:
  370. creq.mode = QCE_MODE_CBC;
  371. break;
  372. case QCEDEV_AES_MODE_ECB:
  373. case QCEDEV_DES_MODE_ECB:
  374. creq.mode = QCE_MODE_ECB;
  375. break;
  376. case QCEDEV_AES_MODE_CTR:
  377. creq.mode = QCE_MODE_CTR;
  378. break;
  379. case QCEDEV_AES_MODE_XTS:
  380. creq.mode = QCE_MODE_XTS;
  381. break;
  382. default:
  383. return -EINVAL;
  384. };
  385. if ((creq.alg == CIPHER_ALG_AES) &&
  386. (creq.mode == QCE_MODE_CTR)) {
  387. creq.dir = QCE_ENCRYPT;
  388. } else {
  389. if (QCEDEV_OPER_ENC == qcedev_areq->cipher_op_req.op)
  390. creq.dir = QCE_ENCRYPT;
  391. else
  392. creq.dir = QCE_DECRYPT;
  393. }
  394. creq.iv = &qcedev_areq->cipher_op_req.iv[0];
  395. creq.ivsize = qcedev_areq->cipher_op_req.ivlen;
  396. creq.enckey = &qcedev_areq->cipher_op_req.enckey[0];
  397. creq.encklen = qcedev_areq->cipher_op_req.encklen;
  398. creq.cryptlen = qcedev_areq->cipher_op_req.data_len;
  399. if (qcedev_areq->cipher_op_req.encklen == 0) {
  400. if ((qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC_NO_KEY)
  401. || (qcedev_areq->cipher_op_req.op ==
  402. QCEDEV_OPER_DEC_NO_KEY))
  403. creq.op = QCE_REQ_ABLK_CIPHER_NO_KEY;
  404. else {
  405. int i;
  406. for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
  407. if (qcedev_areq->cipher_op_req.enckey[i] != 0)
  408. break;
  409. }
  410. if ((podev->platform_support.hw_key_support == 1) &&
  411. (i == QCEDEV_MAX_KEY_SIZE))
  412. creq.op = QCE_REQ_ABLK_CIPHER;
  413. else {
  414. ret = -EINVAL;
  415. goto unsupported;
  416. }
  417. }
  418. } else {
  419. creq.op = QCE_REQ_ABLK_CIPHER;
  420. }
  421. creq.qce_cb = qcedev_cipher_req_cb;
  422. creq.areq = (void *)&qcedev_areq->cipher_req;
  423. creq.flags = 0;
  424. ret = qce_ablk_cipher_req(podev->qce, &creq);
  425. unsupported:
  426. if (ret)
  427. qcedev_areq->err = -ENXIO;
  428. else
  429. qcedev_areq->err = 0;
  430. return ret;
  431. };
  432. static int start_sha_req(struct qcedev_control *podev)
  433. {
  434. struct qcedev_async_req *qcedev_areq;
  435. struct qce_sha_req sreq;
  436. int ret = 0;
  437. struct qcedev_handle *handle;
  438. /* start the command on the podev->active_command */
  439. qcedev_areq = podev->active_command;
  440. handle = qcedev_areq->handle;
  441. switch (qcedev_areq->sha_op_req.alg) {
  442. case QCEDEV_ALG_SHA1:
  443. sreq.alg = QCE_HASH_SHA1;
  444. break;
  445. case QCEDEV_ALG_SHA256:
  446. sreq.alg = QCE_HASH_SHA256;
  447. break;
  448. case QCEDEV_ALG_SHA1_HMAC:
  449. if (podev->ce_support.sha_hmac) {
  450. sreq.alg = QCE_HASH_SHA1_HMAC;
  451. sreq.authkey = &handle->sha_ctxt.authkey[0];
  452. sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
  453. } else {
  454. sreq.alg = QCE_HASH_SHA1;
  455. sreq.authkey = NULL;
  456. }
  457. break;
  458. case QCEDEV_ALG_SHA256_HMAC:
  459. if (podev->ce_support.sha_hmac) {
  460. sreq.alg = QCE_HASH_SHA256_HMAC;
  461. sreq.authkey = &handle->sha_ctxt.authkey[0];
  462. sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
  463. } else {
  464. sreq.alg = QCE_HASH_SHA256;
  465. sreq.authkey = NULL;
  466. }
  467. break;
  468. case QCEDEV_ALG_AES_CMAC:
  469. sreq.alg = QCE_HASH_AES_CMAC;
  470. sreq.authkey = &handle->sha_ctxt.authkey[0];
  471. sreq.authklen = qcedev_areq->sha_op_req.authklen;
  472. break;
  473. default:
  474. pr_err("Algorithm %d not supported, exiting\n",
  475. qcedev_areq->sha_op_req.alg);
  476. return -EINVAL;
  477. break;
  478. };
  479. qcedev_areq->sha_req.cookie = handle;
  480. sreq.qce_cb = qcedev_sha_req_cb;
  481. if (qcedev_areq->sha_op_req.alg != QCEDEV_ALG_AES_CMAC) {
  482. sreq.auth_data[0] = handle->sha_ctxt.auth_data[0];
  483. sreq.auth_data[1] = handle->sha_ctxt.auth_data[1];
  484. sreq.auth_data[2] = handle->sha_ctxt.auth_data[2];
  485. sreq.auth_data[3] = handle->sha_ctxt.auth_data[3];
  486. sreq.digest = &handle->sha_ctxt.digest[0];
  487. sreq.first_blk = handle->sha_ctxt.first_blk;
  488. sreq.last_blk = handle->sha_ctxt.last_blk;
  489. }
  490. sreq.size = qcedev_areq->sha_req.sreq.nbytes;
  491. sreq.src = qcedev_areq->sha_req.sreq.src;
  492. sreq.areq = (void *)&qcedev_areq->sha_req;
  493. sreq.flags = 0;
  494. ret = qce_process_sha_req(podev->qce, &sreq);
  495. if (ret)
  496. qcedev_areq->err = -ENXIO;
  497. else
  498. qcedev_areq->err = 0;
  499. return ret;
  500. };
  501. static int submit_req(struct qcedev_async_req *qcedev_areq,
  502. struct qcedev_handle *handle)
  503. {
  504. struct qcedev_control *podev;
  505. unsigned long flags = 0;
  506. int ret = 0;
  507. struct qcedev_stat *pstat;
  508. qcedev_areq->err = 0;
  509. podev = handle->cntl;
  510. if (podev->platform_support.ce_shared) {
  511. ret = qcedev_lock_ce(podev);
  512. if (ret)
  513. return ret;
  514. }
  515. spin_lock_irqsave(&podev->lock, flags);
  516. if (podev->active_command == NULL) {
  517. podev->active_command = qcedev_areq;
  518. if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_CIPHER)
  519. ret = start_cipher_req(podev);
  520. else
  521. ret = start_sha_req(podev);
  522. } else {
  523. list_add_tail(&qcedev_areq->list, &podev->ready_commands);
  524. }
  525. if (ret != 0)
  526. podev->active_command = NULL;
  527. spin_unlock_irqrestore(&podev->lock, flags);
  528. if (ret == 0)
  529. wait_for_completion(&qcedev_areq->complete);
  530. if (podev->platform_support.ce_shared)
  531. ret = qcedev_unlock_ce(podev);
  532. if (ret)
  533. qcedev_areq->err = -EIO;
  534. pstat = &_qcedev_stat;
  535. if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_CIPHER) {
  536. switch (qcedev_areq->cipher_op_req.op) {
  537. case QCEDEV_OPER_DEC:
  538. if (qcedev_areq->err)
  539. pstat->qcedev_dec_fail++;
  540. else
  541. pstat->qcedev_dec_success++;
  542. break;
  543. case QCEDEV_OPER_ENC:
  544. if (qcedev_areq->err)
  545. pstat->qcedev_enc_fail++;
  546. else
  547. pstat->qcedev_enc_success++;
  548. break;
  549. default:
  550. break;
  551. };
  552. } else {
  553. if (qcedev_areq->err)
  554. pstat->qcedev_sha_fail++;
  555. else
  556. pstat->qcedev_sha_success++;
  557. }
  558. return qcedev_areq->err;
  559. }
  560. static int qcedev_sha_init(struct qcedev_async_req *areq,
  561. struct qcedev_handle *handle)
  562. {
  563. struct qcedev_sha_ctxt *sha_ctxt = &handle->sha_ctxt;
  564. memset(sha_ctxt, 0, sizeof(struct qcedev_sha_ctxt));
  565. sha_ctxt->first_blk = 1;
  566. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  567. (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)) {
  568. memcpy(&sha_ctxt->digest[0],
  569. &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
  570. sha_ctxt->diglen = SHA1_DIGEST_SIZE;
  571. } else {
  572. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA256) ||
  573. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)) {
  574. memcpy(&sha_ctxt->digest[0],
  575. &_std_init_vector_sha256_uint8[0],
  576. SHA256_DIGEST_SIZE);
  577. sha_ctxt->diglen = SHA256_DIGEST_SIZE;
  578. }
  579. }
  580. sha_ctxt->init_done = true;
  581. return 0;
  582. }
  583. static int qcedev_sha_update_max_xfer(struct qcedev_async_req *qcedev_areq,
  584. struct qcedev_handle *handle,
  585. struct scatterlist *sg_src)
  586. {
  587. int err = 0;
  588. int i = 0;
  589. uint32_t total;
  590. uint8_t *user_src = NULL;
  591. uint8_t *k_src = NULL;
  592. uint8_t *k_buf_src = NULL;
  593. uint8_t *k_align_src = NULL;
  594. uint32_t sha_pad_len = 0;
  595. uint32_t trailing_buf_len = 0;
  596. uint32_t t_buf = handle->sha_ctxt.trailing_buf_len;
  597. uint32_t sha_block_size;
  598. total = qcedev_areq->sha_op_req.data_len + t_buf;
  599. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1)
  600. sha_block_size = SHA1_BLOCK_SIZE;
  601. else
  602. sha_block_size = SHA256_BLOCK_SIZE;
  603. if (total <= sha_block_size) {
  604. uint32_t len = qcedev_areq->sha_op_req.data_len;
  605. i = 0;
  606. k_src = &handle->sha_ctxt.trailing_buf[t_buf];
  607. /* Copy data from user src(s) */
  608. while (len > 0) {
  609. user_src =
  610. (void __user *)qcedev_areq->sha_op_req.data[i].vaddr;
  611. if (user_src && copy_from_user(k_src,
  612. (void __user *)user_src,
  613. qcedev_areq->sha_op_req.data[i].len))
  614. return -EFAULT;
  615. len -= qcedev_areq->sha_op_req.data[i].len;
  616. k_src += qcedev_areq->sha_op_req.data[i].len;
  617. i++;
  618. }
  619. handle->sha_ctxt.trailing_buf_len = total;
  620. return 0;
  621. }
  622. k_buf_src = kmalloc(total + CACHE_LINE_SIZE * 2,
  623. GFP_KERNEL);
  624. if (k_buf_src == NULL) {
  625. pr_err("%s: Can't Allocate memory: k_buf_src 0x%x\n",
  626. __func__, (uint32_t)k_buf_src);
  627. return -ENOMEM;
  628. }
  629. k_align_src = (uint8_t *) ALIGN(((unsigned int)k_buf_src),
  630. CACHE_LINE_SIZE);
  631. k_src = k_align_src;
  632. /* check for trailing buffer from previous updates and append it */
  633. if (t_buf > 0) {
  634. memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
  635. t_buf);
  636. k_src += t_buf;
  637. }
  638. /* Copy data from user src(s) */
  639. user_src = (void __user *)qcedev_areq->sha_op_req.data[0].vaddr;
  640. if (user_src && copy_from_user(k_src,
  641. (void __user *)user_src,
  642. qcedev_areq->sha_op_req.data[0].len)) {
  643. kzfree(k_buf_src);
  644. return -EFAULT;
  645. }
  646. k_src += qcedev_areq->sha_op_req.data[0].len;
  647. for (i = 1; i < qcedev_areq->sha_op_req.entries; i++) {
  648. user_src = (void __user *)qcedev_areq->sha_op_req.data[i].vaddr;
  649. if (user_src && copy_from_user(k_src,
  650. (void __user *)user_src,
  651. qcedev_areq->sha_op_req.data[i].len)) {
  652. kzfree(k_buf_src);
  653. return -EFAULT;
  654. }
  655. k_src += qcedev_areq->sha_op_req.data[i].len;
  656. }
  657. /* get new trailing buffer */
  658. sha_pad_len = ALIGN(total, CE_SHA_BLOCK_SIZE) - total;
  659. trailing_buf_len = CE_SHA_BLOCK_SIZE - sha_pad_len;
  660. qcedev_areq->sha_req.sreq.src = sg_src;
  661. sg_set_buf(qcedev_areq->sha_req.sreq.src, k_align_src,
  662. total-trailing_buf_len);
  663. sg_mark_end(qcedev_areq->sha_req.sreq.src);
  664. qcedev_areq->sha_req.sreq.nbytes = total - trailing_buf_len;
  665. /* update sha_ctxt trailing buf content to new trailing buf */
  666. if (trailing_buf_len > 0) {
  667. memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
  668. memcpy(&handle->sha_ctxt.trailing_buf[0],
  669. (k_src - trailing_buf_len),
  670. trailing_buf_len);
  671. }
  672. handle->sha_ctxt.trailing_buf_len = trailing_buf_len;
  673. err = submit_req(qcedev_areq, handle);
  674. handle->sha_ctxt.last_blk = 0;
  675. handle->sha_ctxt.first_blk = 0;
  676. kzfree(k_buf_src);
  677. return err;
  678. }
  679. static int qcedev_sha_update(struct qcedev_async_req *qcedev_areq,
  680. struct qcedev_handle *handle,
  681. struct scatterlist *sg_src)
  682. {
  683. int err = 0;
  684. int i = 0;
  685. int j = 0;
  686. int k = 0;
  687. int num_entries = 0;
  688. uint32_t total = 0;
  689. if (handle->sha_ctxt.init_done == false) {
  690. pr_err("%s Init was not called\n", __func__);
  691. return -EINVAL;
  692. }
  693. if (qcedev_areq->sha_op_req.data_len > QCE_MAX_OPER_DATA) {
  694. struct qcedev_sha_op_req *saved_req;
  695. struct qcedev_sha_op_req req;
  696. struct qcedev_sha_op_req *sreq = &qcedev_areq->sha_op_req;
  697. /* save the original req structure */
  698. saved_req =
  699. kmalloc(sizeof(struct qcedev_sha_op_req), GFP_KERNEL);
  700. if (saved_req == NULL) {
  701. pr_err("%s:Can't Allocate mem:saved_req 0x%x\n",
  702. __func__, (uint32_t)saved_req);
  703. return -ENOMEM;
  704. }
  705. memcpy(&req, sreq, sizeof(struct qcedev_sha_op_req));
  706. memcpy(saved_req, sreq, sizeof(struct qcedev_sha_op_req));
  707. i = 0;
  708. /* Address 32 KB at a time */
  709. while ((i < req.entries) && (err == 0)) {
  710. if (sreq->data[i].len > QCE_MAX_OPER_DATA) {
  711. sreq->data[0].len = QCE_MAX_OPER_DATA;
  712. if (i > 0) {
  713. sreq->data[0].vaddr =
  714. sreq->data[i].vaddr;
  715. }
  716. sreq->data_len = QCE_MAX_OPER_DATA;
  717. sreq->entries = 1;
  718. err = qcedev_sha_update_max_xfer(qcedev_areq,
  719. handle, sg_src);
  720. sreq->data[i].len = req.data[i].len -
  721. QCE_MAX_OPER_DATA;
  722. sreq->data[i].vaddr = req.data[i].vaddr +
  723. QCE_MAX_OPER_DATA;
  724. req.data[i].vaddr = sreq->data[i].vaddr;
  725. req.data[i].len = sreq->data[i].len;
  726. } else {
  727. total = 0;
  728. for (j = i; j < req.entries; j++) {
  729. num_entries++;
  730. if ((total + sreq->data[j].len) >=
  731. QCE_MAX_OPER_DATA) {
  732. sreq->data[j].len =
  733. (QCE_MAX_OPER_DATA - total);
  734. total = QCE_MAX_OPER_DATA;
  735. break;
  736. }
  737. total += sreq->data[j].len;
  738. }
  739. sreq->data_len = total;
  740. if (i > 0)
  741. for (k = 0; k < num_entries; k++) {
  742. sreq->data[k].len =
  743. sreq->data[i+k].len;
  744. sreq->data[k].vaddr =
  745. sreq->data[i+k].vaddr;
  746. }
  747. sreq->entries = num_entries;
  748. i = j;
  749. err = qcedev_sha_update_max_xfer(qcedev_areq,
  750. handle, sg_src);
  751. num_entries = 0;
  752. sreq->data[i].vaddr = req.data[i].vaddr +
  753. sreq->data[i].len;
  754. sreq->data[i].len = req.data[i].len -
  755. sreq->data[i].len;
  756. req.data[i].vaddr = sreq->data[i].vaddr;
  757. req.data[i].len = sreq->data[i].len;
  758. if (sreq->data[i].len == 0)
  759. i++;
  760. }
  761. } /* end of while ((i < req.entries) && (err == 0)) */
  762. /* Restore the original req structure */
  763. for (i = 0; i < saved_req->entries; i++) {
  764. sreq->data[i].len = saved_req->data[i].len;
  765. sreq->data[i].vaddr = saved_req->data[i].vaddr;
  766. }
  767. sreq->entries = saved_req->entries;
  768. sreq->data_len = saved_req->data_len;
  769. kzfree(saved_req);
  770. } else
  771. err = qcedev_sha_update_max_xfer(qcedev_areq, handle, sg_src);
  772. return err;
  773. }
  774. static int qcedev_sha_final(struct qcedev_async_req *qcedev_areq,
  775. struct qcedev_handle *handle)
  776. {
  777. int err = 0;
  778. struct scatterlist sg_src;
  779. uint32_t total;
  780. uint8_t *k_buf_src = NULL;
  781. uint8_t *k_align_src = NULL;
  782. if (handle->sha_ctxt.init_done == false) {
  783. pr_err("%s Init was not called\n", __func__);
  784. return -EINVAL;
  785. }
  786. handle->sha_ctxt.last_blk = 1;
  787. total = handle->sha_ctxt.trailing_buf_len;
  788. if (total) {
  789. k_buf_src = kmalloc(total + CACHE_LINE_SIZE * 2,
  790. GFP_KERNEL);
  791. if (k_buf_src == NULL) {
  792. pr_err("%s: Can't Allocate memory: k_buf_src 0x%x\n",
  793. __func__, (uint32_t)k_buf_src);
  794. return -ENOMEM;
  795. }
  796. k_align_src = (uint8_t *) ALIGN(((unsigned int)k_buf_src),
  797. CACHE_LINE_SIZE);
  798. memcpy(k_align_src, &handle->sha_ctxt.trailing_buf[0], total);
  799. }
  800. qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
  801. sg_set_buf(qcedev_areq->sha_req.sreq.src, k_align_src, total);
  802. sg_mark_end(qcedev_areq->sha_req.sreq.src);
  803. qcedev_areq->sha_req.sreq.nbytes = total;
  804. err = submit_req(qcedev_areq, handle);
  805. handle->sha_ctxt.first_blk = 0;
  806. handle->sha_ctxt.last_blk = 0;
  807. handle->sha_ctxt.auth_data[0] = 0;
  808. handle->sha_ctxt.auth_data[1] = 0;
  809. handle->sha_ctxt.trailing_buf_len = 0;
  810. handle->sha_ctxt.init_done = false;
  811. memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
  812. kzfree(k_buf_src);
  813. return err;
  814. }
  815. static int qcedev_hash_cmac(struct qcedev_async_req *qcedev_areq,
  816. struct qcedev_handle *handle,
  817. struct scatterlist *sg_src)
  818. {
  819. int err = 0;
  820. int i = 0;
  821. uint32_t total;
  822. uint8_t *user_src = NULL;
  823. uint8_t *k_src = NULL;
  824. uint8_t *k_buf_src = NULL;
  825. total = qcedev_areq->sha_op_req.data_len;
  826. if (copy_from_user(&handle->sha_ctxt.authkey[0],
  827. (void __user *)qcedev_areq->sha_op_req.authkey,
  828. qcedev_areq->sha_op_req.authklen))
  829. return -EFAULT;
  830. k_buf_src = kmalloc(total, GFP_KERNEL);
  831. if (k_buf_src == NULL) {
  832. pr_err("%s: Can't Allocate memory: k_buf_src 0x%x\n",
  833. __func__, (uint32_t)k_buf_src);
  834. return -ENOMEM;
  835. }
  836. k_src = k_buf_src;
  837. /* Copy data from user src(s) */
  838. user_src = (void __user *)qcedev_areq->sha_op_req.data[0].vaddr;
  839. for (i = 0; i < qcedev_areq->sha_op_req.entries; i++) {
  840. user_src =
  841. (void __user *)qcedev_areq->sha_op_req.data[i].vaddr;
  842. if (user_src && copy_from_user(k_src, (void __user *)user_src,
  843. qcedev_areq->sha_op_req.data[i].len)) {
  844. kzfree(k_buf_src);
  845. return -EFAULT;
  846. }
  847. k_src += qcedev_areq->sha_op_req.data[i].len;
  848. }
  849. qcedev_areq->sha_req.sreq.src = sg_src;
  850. sg_set_buf(qcedev_areq->sha_req.sreq.src, k_buf_src, total);
  851. sg_mark_end(qcedev_areq->sha_req.sreq.src);
  852. qcedev_areq->sha_req.sreq.nbytes = total;
  853. handle->sha_ctxt.diglen = qcedev_areq->sha_op_req.diglen;
  854. err = submit_req(qcedev_areq, handle);
  855. kzfree(k_buf_src);
  856. return err;
  857. }
  858. static int qcedev_set_hmac_auth_key(struct qcedev_async_req *areq,
  859. struct qcedev_handle *handle,
  860. struct scatterlist *sg_src)
  861. {
  862. int err = 0;
  863. if (areq->sha_op_req.authklen <= QCEDEV_MAX_KEY_SIZE) {
  864. qcedev_sha_init(areq, handle);
  865. if (copy_from_user(&handle->sha_ctxt.authkey[0],
  866. (void __user *)areq->sha_op_req.authkey,
  867. areq->sha_op_req.authklen))
  868. return -EFAULT;
  869. } else {
  870. struct qcedev_async_req authkey_areq;
  871. uint8_t authkey[QCEDEV_MAX_SHA_BLOCK_SIZE];
  872. init_completion(&authkey_areq.complete);
  873. authkey_areq.sha_op_req.entries = 1;
  874. authkey_areq.sha_op_req.data[0].vaddr =
  875. areq->sha_op_req.authkey;
  876. authkey_areq.sha_op_req.data[0].len = areq->sha_op_req.authklen;
  877. authkey_areq.sha_op_req.data_len = areq->sha_op_req.authklen;
  878. authkey_areq.sha_op_req.diglen = 0;
  879. authkey_areq.handle = handle;
  880. memset(&authkey_areq.sha_op_req.digest[0], 0,
  881. QCEDEV_MAX_SHA_DIGEST);
  882. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
  883. authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA1;
  884. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)
  885. authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA256;
  886. authkey_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
  887. qcedev_sha_init(&authkey_areq, handle);
  888. err = qcedev_sha_update(&authkey_areq, handle, sg_src);
  889. if (!err)
  890. err = qcedev_sha_final(&authkey_areq, handle);
  891. else
  892. return err;
  893. memcpy(&authkey[0], &handle->sha_ctxt.digest[0],
  894. handle->sha_ctxt.diglen);
  895. qcedev_sha_init(areq, handle);
  896. memcpy(&handle->sha_ctxt.authkey[0], &authkey[0],
  897. handle->sha_ctxt.diglen);
  898. }
  899. return err;
  900. }
  901. static int qcedev_hmac_get_ohash(struct qcedev_async_req *qcedev_areq,
  902. struct qcedev_handle *handle)
  903. {
  904. int err = 0;
  905. struct scatterlist sg_src;
  906. uint8_t *k_src = NULL;
  907. uint32_t sha_block_size = 0;
  908. uint32_t sha_digest_size = 0;
  909. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
  910. sha_digest_size = SHA1_DIGEST_SIZE;
  911. sha_block_size = SHA1_BLOCK_SIZE;
  912. } else {
  913. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
  914. sha_digest_size = SHA256_DIGEST_SIZE;
  915. sha_block_size = SHA256_BLOCK_SIZE;
  916. }
  917. }
  918. k_src = kmalloc(sha_block_size, GFP_KERNEL);
  919. if (k_src == NULL) {
  920. pr_err("%s: Can't Allocate memory: k_src 0x%x\n",
  921. __func__, (uint32_t)k_src);
  922. return -ENOMEM;
  923. }
  924. /* check for trailing buffer from previous updates and append it */
  925. memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
  926. handle->sha_ctxt.trailing_buf_len);
  927. qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
  928. sg_set_buf(qcedev_areq->sha_req.sreq.src, k_src, sha_block_size);
  929. sg_mark_end(qcedev_areq->sha_req.sreq.src);
  930. qcedev_areq->sha_req.sreq.nbytes = sha_block_size;
  931. memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
  932. memcpy(&handle->sha_ctxt.trailing_buf[0], &handle->sha_ctxt.digest[0],
  933. sha_digest_size);
  934. handle->sha_ctxt.trailing_buf_len = sha_digest_size;
  935. handle->sha_ctxt.first_blk = 1;
  936. handle->sha_ctxt.last_blk = 0;
  937. handle->sha_ctxt.auth_data[0] = 0;
  938. handle->sha_ctxt.auth_data[1] = 0;
  939. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
  940. memcpy(&handle->sha_ctxt.digest[0],
  941. &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
  942. handle->sha_ctxt.diglen = SHA1_DIGEST_SIZE;
  943. }
  944. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
  945. memcpy(&handle->sha_ctxt.digest[0],
  946. &_std_init_vector_sha256_uint8[0], SHA256_DIGEST_SIZE);
  947. handle->sha_ctxt.diglen = SHA256_DIGEST_SIZE;
  948. }
  949. err = submit_req(qcedev_areq, handle);
  950. handle->sha_ctxt.last_blk = 0;
  951. handle->sha_ctxt.first_blk = 0;
  952. kzfree(k_src);
  953. return err;
  954. }
  955. static int qcedev_hmac_update_iokey(struct qcedev_async_req *areq,
  956. struct qcedev_handle *handle, bool ikey)
  957. {
  958. int i;
  959. uint32_t constant;
  960. uint32_t sha_block_size;
  961. if (ikey)
  962. constant = 0x36;
  963. else
  964. constant = 0x5c;
  965. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
  966. sha_block_size = SHA1_BLOCK_SIZE;
  967. else
  968. sha_block_size = SHA256_BLOCK_SIZE;
  969. memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
  970. for (i = 0; i < sha_block_size; i++)
  971. handle->sha_ctxt.trailing_buf[i] =
  972. (handle->sha_ctxt.authkey[i] ^ constant);
  973. handle->sha_ctxt.trailing_buf_len = sha_block_size;
  974. return 0;
  975. }
  976. static int qcedev_hmac_init(struct qcedev_async_req *areq,
  977. struct qcedev_handle *handle,
  978. struct scatterlist *sg_src)
  979. {
  980. int err;
  981. struct qcedev_control *podev = handle->cntl;
  982. err = qcedev_set_hmac_auth_key(areq, handle, sg_src);
  983. if (err)
  984. return err;
  985. if (!podev->ce_support.sha_hmac)
  986. qcedev_hmac_update_iokey(areq, handle, true);
  987. return 0;
  988. }
  989. static int qcedev_hmac_final(struct qcedev_async_req *areq,
  990. struct qcedev_handle *handle)
  991. {
  992. int err;
  993. struct qcedev_control *podev = handle->cntl;
  994. err = qcedev_sha_final(areq, handle);
  995. if (podev->ce_support.sha_hmac)
  996. return err;
  997. qcedev_hmac_update_iokey(areq, handle, false);
  998. err = qcedev_hmac_get_ohash(areq, handle);
  999. if (err)
  1000. return err;
  1001. err = qcedev_sha_final(areq, handle);
  1002. return err;
  1003. }
  1004. static int qcedev_hash_init(struct qcedev_async_req *areq,
  1005. struct qcedev_handle *handle,
  1006. struct scatterlist *sg_src)
  1007. {
  1008. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  1009. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
  1010. return qcedev_sha_init(areq, handle);
  1011. else
  1012. return qcedev_hmac_init(areq, handle, sg_src);
  1013. }
  1014. static int qcedev_hash_update(struct qcedev_async_req *qcedev_areq,
  1015. struct qcedev_handle *handle,
  1016. struct scatterlist *sg_src)
  1017. {
  1018. return qcedev_sha_update(qcedev_areq, handle, sg_src);
  1019. }
  1020. static int qcedev_hash_final(struct qcedev_async_req *areq,
  1021. struct qcedev_handle *handle)
  1022. {
  1023. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  1024. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
  1025. return qcedev_sha_final(areq, handle);
  1026. else
  1027. return qcedev_hmac_final(areq, handle);
  1028. }
  1029. static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
  1030. int *di, struct qcedev_handle *handle,
  1031. uint8_t *k_align_src)
  1032. {
  1033. int err = 0;
  1034. int i = 0;
  1035. int dst_i = *di;
  1036. struct scatterlist sg_src;
  1037. uint32_t byteoffset = 0;
  1038. uint8_t *user_src = NULL;
  1039. uint8_t *k_align_dst = k_align_src;
  1040. struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
  1041. if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1042. byteoffset = areq->cipher_op_req.byteoffset;
  1043. user_src = (void __user *)areq->cipher_op_req.vbuf.src[0].vaddr;
  1044. if (user_src && copy_from_user((k_align_src + byteoffset),
  1045. (void __user *)user_src,
  1046. areq->cipher_op_req.vbuf.src[0].len))
  1047. return -EFAULT;
  1048. k_align_src += byteoffset + areq->cipher_op_req.vbuf.src[0].len;
  1049. for (i = 1; i < areq->cipher_op_req.entries; i++) {
  1050. user_src =
  1051. (void __user *)areq->cipher_op_req.vbuf.src[i].vaddr;
  1052. if (user_src && copy_from_user(k_align_src,
  1053. (void __user *)user_src,
  1054. areq->cipher_op_req.vbuf.src[i].len)) {
  1055. return -EFAULT;
  1056. }
  1057. k_align_src += areq->cipher_op_req.vbuf.src[i].len;
  1058. }
  1059. /* restore src beginning */
  1060. k_align_src = k_align_dst;
  1061. areq->cipher_op_req.data_len += byteoffset;
  1062. areq->cipher_req.creq.src = (struct scatterlist *) &sg_src;
  1063. areq->cipher_req.creq.dst = (struct scatterlist *) &sg_src;
  1064. /* In place encryption/decryption */
  1065. sg_set_buf(areq->cipher_req.creq.src,
  1066. k_align_dst,
  1067. areq->cipher_op_req.data_len);
  1068. sg_mark_end(areq->cipher_req.creq.src);
  1069. areq->cipher_req.creq.nbytes = areq->cipher_op_req.data_len;
  1070. areq->cipher_req.creq.info = areq->cipher_op_req.iv;
  1071. areq->cipher_op_req.entries = 1;
  1072. err = submit_req(areq, handle);
  1073. /* copy data to destination buffer*/
  1074. creq->data_len -= byteoffset;
  1075. while (creq->data_len > 0) {
  1076. if (creq->vbuf.dst[dst_i].len <= creq->data_len) {
  1077. if (err == 0 && copy_to_user(
  1078. (void __user *)creq->vbuf.dst[dst_i].vaddr,
  1079. (k_align_dst + byteoffset),
  1080. creq->vbuf.dst[dst_i].len))
  1081. return -EFAULT;
  1082. k_align_dst += creq->vbuf.dst[dst_i].len +
  1083. byteoffset;
  1084. creq->data_len -= creq->vbuf.dst[dst_i].len;
  1085. dst_i++;
  1086. } else {
  1087. if (err == 0 && copy_to_user(
  1088. (void __user *)creq->vbuf.dst[dst_i].vaddr,
  1089. (k_align_dst + byteoffset),
  1090. creq->data_len))
  1091. return -EFAULT;
  1092. k_align_dst += creq->data_len;
  1093. creq->vbuf.dst[dst_i].len -= creq->data_len;
  1094. creq->vbuf.dst[dst_i].vaddr += creq->data_len;
  1095. creq->data_len = 0;
  1096. }
  1097. }
  1098. *di = dst_i;
  1099. return err;
  1100. };
  1101. static int qcedev_vbuf_ablk_cipher(struct qcedev_async_req *areq,
  1102. struct qcedev_handle *handle)
  1103. {
  1104. int err = 0;
  1105. int di = 0;
  1106. int i = 0;
  1107. int j = 0;
  1108. int k = 0;
  1109. uint32_t byteoffset = 0;
  1110. int num_entries = 0;
  1111. uint32_t total = 0;
  1112. uint32_t len;
  1113. uint8_t *k_buf_src = NULL;
  1114. uint8_t *k_align_src = NULL;
  1115. uint32_t max_data_xfer;
  1116. struct qcedev_cipher_op_req *saved_req;
  1117. struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
  1118. total = 0;
  1119. if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1120. byteoffset = areq->cipher_op_req.byteoffset;
  1121. k_buf_src = kmalloc(QCE_MAX_OPER_DATA + CACHE_LINE_SIZE * 2,
  1122. GFP_KERNEL);
  1123. if (k_buf_src == NULL) {
  1124. pr_err("%s: Can't Allocate memory: k_buf_src 0x%x\n",
  1125. __func__, (uint32_t)k_buf_src);
  1126. return -ENOMEM;
  1127. }
  1128. k_align_src = (uint8_t *) ALIGN(((unsigned int)k_buf_src),
  1129. CACHE_LINE_SIZE);
  1130. max_data_xfer = QCE_MAX_OPER_DATA - byteoffset;
  1131. saved_req = kmalloc(sizeof(struct qcedev_cipher_op_req), GFP_KERNEL);
  1132. if (saved_req == NULL) {
  1133. pr_err("%s: Can't Allocate memory:saved_req 0x%x\n",
  1134. __func__, (uint32_t)saved_req);
  1135. kfree(k_buf_src);
  1136. return -ENOMEM;
  1137. }
  1138. memcpy(saved_req, creq, sizeof(struct qcedev_cipher_op_req));
  1139. if (areq->cipher_op_req.data_len > max_data_xfer) {
  1140. struct qcedev_cipher_op_req req;
  1141. /* save the original req structure */
  1142. memcpy(&req, creq, sizeof(struct qcedev_cipher_op_req));
  1143. i = 0;
  1144. /* Address 32 KB at a time */
  1145. while ((i < req.entries) && (err == 0)) {
  1146. if (creq->vbuf.src[i].len > max_data_xfer) {
  1147. creq->vbuf.src[0].len = max_data_xfer;
  1148. if (i > 0) {
  1149. creq->vbuf.src[0].vaddr =
  1150. creq->vbuf.src[i].vaddr;
  1151. }
  1152. creq->data_len = max_data_xfer;
  1153. creq->entries = 1;
  1154. err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
  1155. &di, handle, k_align_src);
  1156. if (err < 0) {
  1157. kzfree(k_buf_src);
  1158. kzfree(saved_req);
  1159. return err;
  1160. }
  1161. creq->vbuf.src[i].len = req.vbuf.src[i].len -
  1162. max_data_xfer;
  1163. creq->vbuf.src[i].vaddr =
  1164. req.vbuf.src[i].vaddr +
  1165. max_data_xfer;
  1166. req.vbuf.src[i].vaddr =
  1167. creq->vbuf.src[i].vaddr;
  1168. req.vbuf.src[i].len = creq->vbuf.src[i].len;
  1169. } else {
  1170. total = areq->cipher_op_req.byteoffset;
  1171. for (j = i; j < req.entries; j++) {
  1172. num_entries++;
  1173. if ((total + creq->vbuf.src[j].len)
  1174. >= max_data_xfer) {
  1175. creq->vbuf.src[j].len =
  1176. max_data_xfer - total;
  1177. total = max_data_xfer;
  1178. break;
  1179. }
  1180. total += creq->vbuf.src[j].len;
  1181. }
  1182. creq->data_len = total;
  1183. if (i > 0)
  1184. for (k = 0; k < num_entries; k++) {
  1185. creq->vbuf.src[k].len =
  1186. creq->vbuf.src[i+k].len;
  1187. creq->vbuf.src[k].vaddr =
  1188. creq->vbuf.src[i+k].vaddr;
  1189. }
  1190. creq->entries = num_entries;
  1191. i = j;
  1192. err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
  1193. &di, handle, k_align_src);
  1194. if (err < 0) {
  1195. kzfree(k_buf_src);
  1196. kzfree(saved_req);
  1197. return err;
  1198. }
  1199. num_entries = 0;
  1200. areq->cipher_op_req.byteoffset = 0;
  1201. creq->vbuf.src[i].vaddr = req.vbuf.src[i].vaddr
  1202. + creq->vbuf.src[i].len;
  1203. creq->vbuf.src[i].len = req.vbuf.src[i].len -
  1204. creq->vbuf.src[i].len;
  1205. req.vbuf.src[i].vaddr =
  1206. creq->vbuf.src[i].vaddr;
  1207. req.vbuf.src[i].len = creq->vbuf.src[i].len;
  1208. if (creq->vbuf.src[i].len == 0)
  1209. i++;
  1210. }
  1211. areq->cipher_op_req.byteoffset = 0;
  1212. max_data_xfer = QCE_MAX_OPER_DATA;
  1213. byteoffset = 0;
  1214. } /* end of while ((i < req.entries) && (err == 0)) */
  1215. } else
  1216. err = qcedev_vbuf_ablk_cipher_max_xfer(areq, &di, handle,
  1217. k_align_src);
  1218. /* Restore the original req structure */
  1219. for (i = 0; i < saved_req->entries; i++) {
  1220. creq->vbuf.src[i].len = saved_req->vbuf.src[i].len;
  1221. creq->vbuf.src[i].vaddr = saved_req->vbuf.src[i].vaddr;
  1222. }
  1223. for (len = 0, i = 0; len < saved_req->data_len; i++) {
  1224. creq->vbuf.dst[i].len = saved_req->vbuf.dst[i].len;
  1225. creq->vbuf.dst[i].vaddr = saved_req->vbuf.dst[i].vaddr;
  1226. len += saved_req->vbuf.dst[i].len;
  1227. }
  1228. creq->entries = saved_req->entries;
  1229. creq->data_len = saved_req->data_len;
  1230. creq->byteoffset = saved_req->byteoffset;
  1231. kzfree(saved_req);
  1232. kzfree(k_buf_src);
  1233. return err;
  1234. }
  1235. static int qcedev_check_cipher_key(struct qcedev_cipher_op_req *req,
  1236. struct qcedev_control *podev)
  1237. {
  1238. /* if intending to use HW key make sure key fields are set
  1239. * correctly and HW key is indeed supported in target
  1240. */
  1241. if (req->encklen == 0) {
  1242. int i;
  1243. for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
  1244. if (req->enckey[i]) {
  1245. pr_err("%s: Invalid key: non-zero key input\n",
  1246. __func__);
  1247. goto error;
  1248. }
  1249. }
  1250. if ((req->op != QCEDEV_OPER_ENC_NO_KEY) &&
  1251. (req->op != QCEDEV_OPER_DEC_NO_KEY))
  1252. if (!podev->platform_support.hw_key_support) {
  1253. pr_err("%s: Invalid op %d\n", __func__,
  1254. (uint32_t)req->op);
  1255. goto error;
  1256. }
  1257. } else {
  1258. if (req->encklen == QCEDEV_AES_KEY_192) {
  1259. if (!podev->ce_support.aes_key_192) {
  1260. pr_err("%s: AES-192 not supported\n", __func__);
  1261. goto error;
  1262. }
  1263. } else {
  1264. /* if not using HW key make sure key
  1265. * length is valid
  1266. */
  1267. if ((req->mode == QCEDEV_AES_MODE_XTS)) {
  1268. if ((req->encklen != QCEDEV_AES_KEY_128*2) &&
  1269. (req->encklen != QCEDEV_AES_KEY_256*2)) {
  1270. pr_err("%s: unsupported key size: %d\n",
  1271. __func__, req->encklen);
  1272. goto error;
  1273. }
  1274. } else {
  1275. if ((req->encklen != QCEDEV_AES_KEY_128) &&
  1276. (req->encklen != QCEDEV_AES_KEY_256)) {
  1277. pr_err("%s: unsupported key size %d\n",
  1278. __func__, req->encklen);
  1279. goto error;
  1280. }
  1281. }
  1282. }
  1283. }
  1284. return 0;
  1285. error:
  1286. return -EINVAL;
  1287. }
  1288. static int qcedev_check_cipher_params(struct qcedev_cipher_op_req *req,
  1289. struct qcedev_control *podev)
  1290. {
  1291. uint32_t total = 0;
  1292. uint32_t i;
  1293. if (req->use_pmem) {
  1294. pr_err("%s: Use of PMEM is not supported\n", __func__);
  1295. goto error;
  1296. }
  1297. if ((req->entries == 0) || (req->data_len == 0) ||
  1298. (req->entries > QCEDEV_MAX_BUFFERS)) {
  1299. pr_err("%s: Invalid cipher length/entries\n", __func__);
  1300. goto error;
  1301. }
  1302. if ((req->alg >= QCEDEV_ALG_LAST) ||
  1303. (req->mode >= QCEDEV_AES_DES_MODE_LAST)) {
  1304. pr_err("%s: Invalid algorithm %d\n", __func__,
  1305. (uint32_t)req->alg);
  1306. goto error;
  1307. }
  1308. if ((req->mode == QCEDEV_AES_MODE_XTS) &&
  1309. (!podev->ce_support.aes_xts)) {
  1310. pr_err("%s: XTS algorithm is not supported\n", __func__);
  1311. goto error;
  1312. }
  1313. if (req->alg == QCEDEV_ALG_AES) {
  1314. if (qcedev_check_cipher_key(req, podev))
  1315. goto error;
  1316. }
  1317. /* if using a byteoffset, make sure it is CTR mode using vbuf */
  1318. if (req->byteoffset) {
  1319. if (req->mode != QCEDEV_AES_MODE_CTR) {
  1320. pr_err("%s: Operation on byte offset not supported\n",
  1321. __func__);
  1322. goto error;
  1323. }
  1324. if (req->byteoffset >= AES_CE_BLOCK_SIZE) {
  1325. pr_err("%s: Invalid byte offset\n", __func__);
  1326. goto error;
  1327. }
  1328. total = req->byteoffset;
  1329. for (i = 0; i < req->entries; i++) {
  1330. if (total > U32_MAX - req->vbuf.src[i].len) {
  1331. pr_err("%s:Integer overflow on total src len\n",
  1332. __func__);
  1333. goto error;
  1334. }
  1335. total += req->vbuf.src[i].len;
  1336. }
  1337. }
  1338. if (req->data_len < req->byteoffset) {
  1339. pr_err("%s: req data length %u is less than byteoffset %u\n",
  1340. __func__, req->data_len, req->byteoffset);
  1341. goto error;
  1342. }
  1343. /* Ensure IV size */
  1344. if (req->ivlen > QCEDEV_MAX_IV_SIZE) {
  1345. pr_err("%s: ivlen is not correct: %u\n", __func__, req->ivlen);
  1346. goto error;
  1347. }
  1348. /* Ensure Key size */
  1349. if (req->encklen > QCEDEV_MAX_KEY_SIZE) {
  1350. pr_err("%s: Klen is not correct: %u\n", __func__, req->encklen);
  1351. goto error;
  1352. }
  1353. /* Ensure zer ivlen for ECB mode */
  1354. if (req->ivlen > 0) {
  1355. if ((req->mode == QCEDEV_AES_MODE_ECB) ||
  1356. (req->mode == QCEDEV_DES_MODE_ECB)) {
  1357. pr_err("%s: Expecting a zero length IV\n", __func__);
  1358. goto error;
  1359. }
  1360. } else {
  1361. if ((req->mode != QCEDEV_AES_MODE_ECB) &&
  1362. (req->mode != QCEDEV_DES_MODE_ECB)) {
  1363. pr_err("%s: Expecting a non-zero ength IV\n", __func__);
  1364. goto error;
  1365. }
  1366. }
  1367. /* Check for sum of all dst length is equal to data_len */
  1368. for (i = 0, total = 0; i < req->entries; i++) {
  1369. if (req->vbuf.dst[i].len >= U32_MAX - total) {
  1370. pr_err("%s: Integer overflow on total req dst vbuf length\n",
  1371. __func__);
  1372. goto error;
  1373. }
  1374. total += req->vbuf.dst[i].len;
  1375. }
  1376. if (total != req->data_len) {
  1377. pr_err("%s: Total (i=%d) dst(%d) buf size != data_len (%d)\n",
  1378. __func__, i, total, req->data_len);
  1379. goto error;
  1380. }
  1381. /* Check for sum of all src length is equal to data_len */
  1382. for (i = 0, total = 0; i < req->entries; i++) {
  1383. if (req->vbuf.src[i].len > U32_MAX - total) {
  1384. pr_err("%s: Integer overflow on total req src vbuf length\n",
  1385. __func__);
  1386. goto error;
  1387. }
  1388. total += req->vbuf.src[i].len;
  1389. }
  1390. if (total != req->data_len) {
  1391. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1392. __func__, total, req->data_len);
  1393. goto error;
  1394. }
  1395. return 0;
  1396. error:
  1397. return -EINVAL;
  1398. }
  1399. static int qcedev_check_sha_params(struct qcedev_sha_op_req *req,
  1400. struct qcedev_control *podev)
  1401. {
  1402. uint32_t total = 0;
  1403. uint32_t i;
  1404. if ((req->alg == QCEDEV_ALG_AES_CMAC) &&
  1405. (!podev->ce_support.cmac)) {
  1406. pr_err("%s: CMAC not supported\n", __func__);
  1407. goto sha_error;
  1408. }
  1409. if ((!req->entries) || (req->entries > QCEDEV_MAX_BUFFERS)) {
  1410. pr_err("%s: Invalid num entries (%d)\n",
  1411. __func__, req->entries);
  1412. goto sha_error;
  1413. }
  1414. if (req->alg >= QCEDEV_ALG_SHA_ALG_LAST) {
  1415. pr_err("%s: Invalid algorithm (%d)\n", __func__, req->alg);
  1416. goto sha_error;
  1417. }
  1418. if ((req->alg == QCEDEV_ALG_SHA1_HMAC) ||
  1419. (req->alg == QCEDEV_ALG_SHA1_HMAC)) {
  1420. if (req->authkey == NULL) {
  1421. pr_err("%s: Invalid authkey pointer\n", __func__);
  1422. goto sha_error;
  1423. }
  1424. if (req->authklen <= 0) {
  1425. pr_err("%s: Invalid authkey length (%d)\n",
  1426. __func__, req->authklen);
  1427. goto sha_error;
  1428. }
  1429. }
  1430. if (req->alg == QCEDEV_ALG_AES_CMAC) {
  1431. if ((req->authklen != QCEDEV_AES_KEY_128) &&
  1432. (req->authklen != QCEDEV_AES_KEY_256)) {
  1433. pr_err("%s: unsupported key length\n", __func__);
  1434. goto sha_error;
  1435. }
  1436. }
  1437. /* Check for sum of all src length is equal to data_len */
  1438. for (i = 0, total = 0; i < req->entries; i++) {
  1439. if (req->data[i].len > U32_MAX - total) {
  1440. pr_err("%s: Integer overflow on total req buf length\n",
  1441. __func__);
  1442. goto sha_error;
  1443. }
  1444. total += req->data[i].len;
  1445. }
  1446. if (total != req->data_len) {
  1447. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1448. __func__, total, req->data_len);
  1449. goto sha_error;
  1450. }
  1451. return 0;
  1452. sha_error:
  1453. return -EINVAL;
  1454. }
  1455. static long qcedev_ioctl(struct file *file, unsigned cmd, unsigned long arg)
  1456. {
  1457. int err = 0;
  1458. struct qcedev_handle *handle;
  1459. struct qcedev_control *podev;
  1460. struct qcedev_async_req qcedev_areq;
  1461. struct qcedev_stat *pstat;
  1462. handle = file->private_data;
  1463. podev = handle->cntl;
  1464. qcedev_areq.handle = handle;
  1465. if (podev == NULL || podev->magic != QCEDEV_MAGIC) {
  1466. pr_err("%s: invalid handle %p\n",
  1467. __func__, podev);
  1468. return -ENOENT;
  1469. }
  1470. /* Verify user arguments. */
  1471. if (_IOC_TYPE(cmd) != QCEDEV_IOC_MAGIC)
  1472. return -ENOTTY;
  1473. init_completion(&qcedev_areq.complete);
  1474. pstat = &_qcedev_stat;
  1475. switch (cmd) {
  1476. case QCEDEV_IOCTL_LOCK_CE:
  1477. if (podev->platform_support.ce_shared)
  1478. err = qcedev_lock_ce(podev);
  1479. else
  1480. err = -ENOTTY;
  1481. break;
  1482. case QCEDEV_IOCTL_UNLOCK_CE:
  1483. if (podev->platform_support.ce_shared)
  1484. err = qcedev_unlock_ce(podev);
  1485. else
  1486. err = -ENOTTY;
  1487. break;
  1488. case QCEDEV_IOCTL_ENC_REQ:
  1489. case QCEDEV_IOCTL_DEC_REQ:
  1490. if (copy_from_user(&qcedev_areq.cipher_op_req,
  1491. (void __user *)arg,
  1492. sizeof(struct qcedev_cipher_op_req)))
  1493. return -EFAULT;
  1494. qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_CIPHER;
  1495. if (qcedev_check_cipher_params(&qcedev_areq.cipher_op_req,
  1496. podev))
  1497. return -EINVAL;
  1498. err = qcedev_vbuf_ablk_cipher(&qcedev_areq, handle);
  1499. if (err)
  1500. return err;
  1501. if (copy_to_user((void __user *)arg,
  1502. &qcedev_areq.cipher_op_req,
  1503. sizeof(struct qcedev_cipher_op_req)))
  1504. return -EFAULT;
  1505. break;
  1506. case QCEDEV_IOCTL_SHA_INIT_REQ:
  1507. {
  1508. struct scatterlist sg_src;
  1509. if (copy_from_user(&qcedev_areq.sha_op_req,
  1510. (void __user *)arg,
  1511. sizeof(struct qcedev_sha_op_req)))
  1512. return -EFAULT;
  1513. mutex_lock(&hash_access_lock);
  1514. if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) {
  1515. mutex_unlock(&hash_access_lock);
  1516. return -EINVAL;
  1517. }
  1518. qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
  1519. err = qcedev_hash_init(&qcedev_areq, handle, &sg_src);
  1520. if (err) {
  1521. mutex_unlock(&hash_access_lock);
  1522. return err;
  1523. }
  1524. mutex_unlock(&hash_access_lock);
  1525. if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,
  1526. sizeof(struct qcedev_sha_op_req)))
  1527. return -EFAULT;
  1528. }
  1529. handle->sha_ctxt.init_done = true;
  1530. break;
  1531. case QCEDEV_IOCTL_GET_CMAC_REQ:
  1532. if (!podev->ce_support.cmac)
  1533. return -ENOTTY;
  1534. case QCEDEV_IOCTL_SHA_UPDATE_REQ:
  1535. {
  1536. struct scatterlist sg_src;
  1537. if (copy_from_user(&qcedev_areq.sha_op_req,
  1538. (void __user *)arg,
  1539. sizeof(struct qcedev_sha_op_req)))
  1540. return -EFAULT;
  1541. mutex_lock(&hash_access_lock);
  1542. if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) {
  1543. mutex_unlock(&hash_access_lock);
  1544. return -EINVAL;
  1545. }
  1546. qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
  1547. if (qcedev_areq.sha_op_req.alg == QCEDEV_ALG_AES_CMAC) {
  1548. err = qcedev_hash_cmac(&qcedev_areq, handle, &sg_src);
  1549. if (err) {
  1550. mutex_unlock(&hash_access_lock);
  1551. return err;
  1552. }
  1553. } else {
  1554. if (handle->sha_ctxt.init_done == false) {
  1555. pr_err("%s Init was not called\n", __func__);
  1556. mutex_unlock(&hash_access_lock);
  1557. return -EINVAL;
  1558. }
  1559. err = qcedev_hash_update(&qcedev_areq, handle, &sg_src);
  1560. if (err) {
  1561. mutex_unlock(&hash_access_lock);
  1562. return err;
  1563. }
  1564. }
  1565. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  1566. pr_err("Invalid sha_ctxt.diglen %d\n",
  1567. handle->sha_ctxt.diglen);
  1568. mutex_unlock(&hash_access_lock);
  1569. return -EINVAL;
  1570. }
  1571. memcpy(&qcedev_areq.sha_op_req.digest[0],
  1572. &handle->sha_ctxt.digest[0],
  1573. handle->sha_ctxt.diglen);
  1574. mutex_unlock(&hash_access_lock);
  1575. if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,
  1576. sizeof(struct qcedev_sha_op_req)))
  1577. return -EFAULT;
  1578. }
  1579. break;
  1580. case QCEDEV_IOCTL_SHA_FINAL_REQ:
  1581. if (handle->sha_ctxt.init_done == false) {
  1582. pr_err("%s Init was not called\n", __func__);
  1583. return -EINVAL;
  1584. }
  1585. if (copy_from_user(&qcedev_areq.sha_op_req,
  1586. (void __user *)arg,
  1587. sizeof(struct qcedev_sha_op_req)))
  1588. return -EFAULT;
  1589. mutex_lock(&hash_access_lock);
  1590. if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) {
  1591. mutex_unlock(&hash_access_lock);
  1592. return -EINVAL;
  1593. }
  1594. qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
  1595. err = qcedev_hash_final(&qcedev_areq, handle);
  1596. if (err) {
  1597. mutex_unlock(&hash_access_lock);
  1598. return err;
  1599. }
  1600. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  1601. pr_err("Invalid sha_ctxt.diglen %d\n",
  1602. handle->sha_ctxt.diglen);
  1603. mutex_unlock(&hash_access_lock);
  1604. return -EINVAL;
  1605. }
  1606. qcedev_areq.sha_op_req.diglen = handle->sha_ctxt.diglen;
  1607. memcpy(&qcedev_areq.sha_op_req.digest[0],
  1608. &handle->sha_ctxt.digest[0],
  1609. handle->sha_ctxt.diglen);
  1610. mutex_unlock(&hash_access_lock);
  1611. if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,
  1612. sizeof(struct qcedev_sha_op_req)))
  1613. return -EFAULT;
  1614. handle->sha_ctxt.init_done = false;
  1615. break;
  1616. case QCEDEV_IOCTL_GET_SHA_REQ:
  1617. {
  1618. struct scatterlist sg_src;
  1619. if (copy_from_user(&qcedev_areq.sha_op_req,
  1620. (void __user *)arg,
  1621. sizeof(struct qcedev_sha_op_req)))
  1622. return -EFAULT;
  1623. mutex_lock(&hash_access_lock);
  1624. if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) {
  1625. mutex_unlock(&hash_access_lock);
  1626. return -EINVAL;
  1627. }
  1628. qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
  1629. qcedev_hash_init(&qcedev_areq, handle, &sg_src);
  1630. err = qcedev_hash_update(&qcedev_areq, handle, &sg_src);
  1631. if (err) {
  1632. mutex_unlock(&hash_access_lock);
  1633. return err;
  1634. }
  1635. err = qcedev_hash_final(&qcedev_areq, handle);
  1636. if (err) {
  1637. mutex_unlock(&hash_access_lock);
  1638. return err;
  1639. }
  1640. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  1641. pr_err("Invalid sha_ctxt.diglen %d\n",
  1642. handle->sha_ctxt.diglen);
  1643. mutex_unlock(&hash_access_lock);
  1644. return -EINVAL;
  1645. }
  1646. qcedev_areq.sha_op_req.diglen = handle->sha_ctxt.diglen;
  1647. memcpy(&qcedev_areq.sha_op_req.digest[0],
  1648. &handle->sha_ctxt.digest[0],
  1649. handle->sha_ctxt.diglen);
  1650. mutex_unlock(&hash_access_lock);
  1651. if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,
  1652. sizeof(struct qcedev_sha_op_req)))
  1653. return -EFAULT;
  1654. }
  1655. break;
  1656. /* This IOCTL call can be called only once
  1657. by FIPS Integrity test */
  1658. case QCEDEV_IOCTL_UPDATE_FIPS_STATUS:
  1659. {
  1660. enum fips_status status;
  1661. if (is_fips_qcedev_integritytest_done)
  1662. return -EPERM;
  1663. if (!access_ok(VERIFY_WRITE, (void __user *)arg,
  1664. sizeof(enum fips_status)))
  1665. return -EFAULT;
  1666. if (__copy_from_user(&status, (void __user *)arg,
  1667. sizeof(enum fips_status)))
  1668. return -EFAULT;
  1669. g_fips140_status = _fips_update_status(status);
  1670. pr_info("qcedev: FIPS140-2 Global status flag: %d\n",
  1671. g_fips140_status);
  1672. is_fips_qcedev_integritytest_done = true;
  1673. if (g_fips140_status == FIPS140_STATUS_FAIL) {
  1674. pr_info("qcedev: FIPS140-2 Integrity test failed\n");
  1675. break;
  1676. }
  1677. if (!(_do_msm_fips_drbg_init(drbg_call_back)) &&
  1678. (g_fips140_status != FIPS140_STATUS_NA))
  1679. g_fips140_status = FIPS140_STATUS_PASS;
  1680. }
  1681. pr_info("qcedev: FIPS140-2 Global status flag: %d\n",
  1682. g_fips140_status);
  1683. break;
  1684. /* Read only IOCTL call to read the
  1685. current FIPS140-2 Status */
  1686. case QCEDEV_IOCTL_QUERY_FIPS_STATUS:
  1687. {
  1688. enum fips_status status;
  1689. if (!access_ok(VERIFY_WRITE, (void __user *)arg,
  1690. sizeof(enum fips_status)))
  1691. return -EFAULT;
  1692. status = g_fips140_status;
  1693. if (__copy_to_user((void __user *)arg, &status,
  1694. sizeof(enum fips_status)))
  1695. return -EFAULT;
  1696. }
  1697. break;
  1698. default:
  1699. return -ENOTTY;
  1700. }
  1701. return err;
  1702. }
  1703. static int qcedev_probe(struct platform_device *pdev)
  1704. {
  1705. void *handle = NULL;
  1706. int rc = 0;
  1707. struct qcedev_control *podev;
  1708. struct msm_ce_hw_support *platform_support;
  1709. podev = &qce_dev[0];
  1710. podev->ce_lock_count = 0;
  1711. podev->high_bw_req_count = 0;
  1712. INIT_LIST_HEAD(&podev->ready_commands);
  1713. podev->active_command = NULL;
  1714. spin_lock_init(&podev->lock);
  1715. tasklet_init(&podev->done_tasklet, req_done, (unsigned long)podev);
  1716. /* open qce */
  1717. handle = qce_open(pdev, &rc);
  1718. if (handle == NULL) {
  1719. platform_set_drvdata(pdev, NULL);
  1720. return rc;
  1721. }
  1722. podev->qce = handle;
  1723. podev->pdev = pdev;
  1724. platform_set_drvdata(pdev, podev);
  1725. rc = misc_register(&podev->miscdevice);
  1726. if(rc < 0)
  1727. return rc;
  1728. rc = qce_hw_support(podev->qce, &podev->ce_support);
  1729. if(rc < 0)
  1730. return rc;
  1731. if (podev->ce_support.bam) {
  1732. podev->platform_support.ce_shared = 0;
  1733. podev->platform_support.shared_ce_resource = 0;
  1734. podev->platform_support.hw_key_support =
  1735. podev->ce_support.hw_key;
  1736. podev->platform_support.bus_scale_table = NULL;
  1737. podev->platform_support.sha_hmac = 1;
  1738. podev->platform_support.bus_scale_table =
  1739. (struct msm_bus_scale_pdata *)
  1740. msm_bus_cl_get_pdata(pdev);
  1741. if (!podev->platform_support.bus_scale_table)
  1742. pr_err("bus_scale_table is NULL\n");
  1743. } else {
  1744. platform_support =
  1745. (struct msm_ce_hw_support *)pdev->dev.platform_data;
  1746. podev->platform_support.ce_shared = platform_support->ce_shared;
  1747. podev->platform_support.shared_ce_resource =
  1748. platform_support->shared_ce_resource;
  1749. podev->platform_support.hw_key_support =
  1750. platform_support->hw_key_support;
  1751. podev->platform_support.bus_scale_table =
  1752. platform_support->bus_scale_table;
  1753. podev->platform_support.sha_hmac = platform_support->sha_hmac;
  1754. }
  1755. if (podev->platform_support.bus_scale_table != NULL) {
  1756. podev->bus_scale_handle =
  1757. msm_bus_scale_register_client(
  1758. (struct msm_bus_scale_pdata *)
  1759. podev->platform_support.bus_scale_table);
  1760. if (!podev->bus_scale_handle) {
  1761. pr_err("%s not able to get bus scale\n",
  1762. __func__);
  1763. rc = -ENOMEM;
  1764. goto err;
  1765. }
  1766. }
  1767. /*
  1768. * FIPS140-2 Known Answer Tests:
  1769. * IN case of any failure, do not Init the module
  1770. */
  1771. is_fips_qcedev_integritytest_done = false;
  1772. if (g_fips140_status != FIPS140_STATUS_NA) {
  1773. if (_fips_qcedev_cipher_selftest(&qce_dev[0]) ||
  1774. _fips_qcedev_sha_selftest(&qce_dev[0])) {
  1775. pr_err("qcedev: FIPS140-2 Known Answer Tests : Failed\n");
  1776. panic("SYSTEM CAN NOT BOOT !!!");
  1777. rc = -1;
  1778. } else {
  1779. pr_info("qcedev: FIPS140-2 Known Answer Tests : Successful\n");
  1780. rc = 0;
  1781. }
  1782. } else
  1783. pr_info("qcedev: FIPS140-2 Known Answer Tests : Skipped\n");
  1784. if (rc >= 0)
  1785. return 0;
  1786. else
  1787. if (podev->platform_support.bus_scale_table != NULL)
  1788. msm_bus_scale_unregister_client(
  1789. podev->bus_scale_handle);
  1790. err:
  1791. if (handle)
  1792. qce_close(handle);
  1793. platform_set_drvdata(pdev, NULL);
  1794. podev->qce = NULL;
  1795. podev->pdev = NULL;
  1796. return rc;
  1797. };
  1798. static int qcedev_remove(struct platform_device *pdev)
  1799. {
  1800. struct qcedev_control *podev;
  1801. podev = platform_get_drvdata(pdev);
  1802. if (!podev)
  1803. return 0;
  1804. if (podev->qce)
  1805. qce_close(podev->qce);
  1806. if (podev->platform_support.bus_scale_table != NULL)
  1807. msm_bus_scale_unregister_client(podev->bus_scale_handle);
  1808. if (podev->miscdevice.minor != MISC_DYNAMIC_MINOR)
  1809. misc_deregister(&podev->miscdevice);
  1810. tasklet_kill(&podev->done_tasklet);
  1811. return 0;
  1812. };
  1813. static int qcedev_suspend(struct platform_device *pdev, pm_message_t state)
  1814. {
  1815. struct qcedev_control *podev;
  1816. int ret;
  1817. podev = platform_get_drvdata(pdev);
  1818. if (!podev || !podev->platform_support.bus_scale_table)
  1819. return 0;
  1820. mutex_lock(&qcedev_sent_bw_req);
  1821. if (podev->high_bw_req_count) {
  1822. ret = msm_bus_scale_client_update_request(
  1823. podev->bus_scale_handle, 0);
  1824. if (ret) {
  1825. pr_err("%s Unable to set to low bandwidth\n",
  1826. __func__);
  1827. goto suspend_exit;
  1828. }
  1829. ret = qce_disable_clk(podev->qce);
  1830. if (ret) {
  1831. pr_err("%s Unable disable clk\n", __func__);
  1832. ret = msm_bus_scale_client_update_request(
  1833. podev->bus_scale_handle, 1);
  1834. if (ret)
  1835. pr_err("%s Unable to set to high bandwidth\n",
  1836. __func__);
  1837. goto suspend_exit;
  1838. }
  1839. }
  1840. suspend_exit:
  1841. mutex_unlock(&qcedev_sent_bw_req);
  1842. return 0;
  1843. }
  1844. static int qcedev_resume(struct platform_device *pdev)
  1845. {
  1846. struct qcedev_control *podev;
  1847. int ret;
  1848. podev = platform_get_drvdata(pdev);
  1849. if (!podev || !podev->platform_support.bus_scale_table)
  1850. return 0;
  1851. mutex_lock(&qcedev_sent_bw_req);
  1852. if (podev->high_bw_req_count) {
  1853. ret = qce_enable_clk(podev->qce);
  1854. if (ret) {
  1855. pr_err("%s Unable enable clk\n", __func__);
  1856. goto resume_exit;
  1857. }
  1858. ret = msm_bus_scale_client_update_request(
  1859. podev->bus_scale_handle, 1);
  1860. if (ret) {
  1861. pr_err("%s Unable to set to high bandwidth\n",
  1862. __func__);
  1863. ret = qce_disable_clk(podev->qce);
  1864. if (ret)
  1865. pr_err("%s Unable enable clk\n",
  1866. __func__);
  1867. goto resume_exit;
  1868. }
  1869. }
  1870. resume_exit:
  1871. mutex_unlock(&qcedev_sent_bw_req);
  1872. return 0;
  1873. }
  1874. static struct of_device_id qcedev_match[] = {
  1875. { .compatible = "qcom,qcedev",
  1876. },
  1877. {}
  1878. };
  1879. static struct platform_driver qcedev_plat_driver = {
  1880. .probe = qcedev_probe,
  1881. .remove = qcedev_remove,
  1882. .suspend = qcedev_suspend,
  1883. .resume = qcedev_resume,
  1884. .driver = {
  1885. .name = "qce",
  1886. .owner = THIS_MODULE,
  1887. .of_match_table = qcedev_match,
  1888. },
  1889. };
  1890. static int _disp_stats(int id)
  1891. {
  1892. struct qcedev_stat *pstat;
  1893. int len = 0;
  1894. pstat = &_qcedev_stat;
  1895. len = scnprintf(_debug_read_buf, DEBUG_MAX_RW_BUF - 1,
  1896. "\nQualcomm QCE dev driver %d Statistics:\n",
  1897. id + 1);
  1898. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  1899. " Encryption operation success : %d\n",
  1900. pstat->qcedev_enc_success);
  1901. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  1902. " Encryption operation fail : %d\n",
  1903. pstat->qcedev_enc_fail);
  1904. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  1905. " Decryption operation success : %d\n",
  1906. pstat->qcedev_dec_success);
  1907. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  1908. " Encryption operation fail : %d\n",
  1909. pstat->qcedev_dec_fail);
  1910. return len;
  1911. }
  1912. static int _debug_stats_open(struct inode *inode, struct file *file)
  1913. {
  1914. file->private_data = inode->i_private;
  1915. return 0;
  1916. }
  1917. static ssize_t _debug_stats_read(struct file *file, char __user *buf,
  1918. size_t count, loff_t *ppos)
  1919. {
  1920. int rc = -EINVAL;
  1921. int qcedev = *((int *) file->private_data);
  1922. int len;
  1923. len = _disp_stats(qcedev);
  1924. if (len <= count)
  1925. rc = simple_read_from_buffer((void __user *) buf, len,
  1926. ppos, (void *) _debug_read_buf, len);
  1927. return rc;
  1928. }
  1929. static ssize_t _debug_stats_write(struct file *file, const char __user *buf,
  1930. size_t count, loff_t *ppos)
  1931. {
  1932. memset((char *)&_qcedev_stat, 0, sizeof(struct qcedev_stat));
  1933. return count;
  1934. };
  1935. static const struct file_operations _debug_stats_ops = {
  1936. .open = _debug_stats_open,
  1937. .read = _debug_stats_read,
  1938. .write = _debug_stats_write,
  1939. };
  1940. static int _qcedev_debug_init(void)
  1941. {
  1942. int rc;
  1943. char name[DEBUG_MAX_FNAME];
  1944. struct dentry *dent;
  1945. _debug_dent = debugfs_create_dir("qcedev", NULL);
  1946. if (IS_ERR(_debug_dent)) {
  1947. pr_err("qcedev debugfs_create_dir fail, error %ld\n",
  1948. PTR_ERR(_debug_dent));
  1949. return PTR_ERR(_debug_dent);
  1950. }
  1951. snprintf(name, DEBUG_MAX_FNAME-1, "stats-%d", 1);
  1952. _debug_qcedev = 0;
  1953. dent = debugfs_create_file(name, 0644, _debug_dent,
  1954. &_debug_qcedev, &_debug_stats_ops);
  1955. if (dent == NULL) {
  1956. pr_err("qcedev debugfs_create_file fail, error %ld\n",
  1957. PTR_ERR(dent));
  1958. rc = PTR_ERR(dent);
  1959. goto err;
  1960. }
  1961. return 0;
  1962. err:
  1963. debugfs_remove_recursive(_debug_dent);
  1964. return rc;
  1965. }
  1966. static int qcedev_init(void)
  1967. {
  1968. int rc;
  1969. rc = _qcedev_debug_init();
  1970. if (rc)
  1971. return rc;
  1972. return platform_driver_register(&qcedev_plat_driver);
  1973. }
  1974. static void qcedev_exit(void)
  1975. {
  1976. debugfs_remove_recursive(_debug_dent);
  1977. platform_driver_unregister(&qcedev_plat_driver);
  1978. }
  1979. MODULE_LICENSE("GPL v2");
  1980. MODULE_DESCRIPTION("Qualcomm DEV Crypto driver");
  1981. module_init(qcedev_init);
  1982. module_exit(qcedev_exit);