Kconfig 10 KB

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  1. menuconfig CRYPTO_HW
  2. bool "Hardware crypto devices"
  3. default y
  4. ---help---
  5. Say Y here to get to see options for hardware crypto devices and
  6. processors. This option alone does not add any kernel code.
  7. If you say N, all options in this submenu will be skipped and disabled.
  8. if CRYPTO_HW
  9. config CRYPTO_DEV_PADLOCK
  10. tristate "Support for VIA PadLock ACE"
  11. depends on X86 && !UML
  12. help
  13. Some VIA processors come with an integrated crypto engine
  14. (so called VIA PadLock ACE, Advanced Cryptography Engine)
  15. that provides instructions for very fast cryptographic
  16. operations with supported algorithms.
  17. The instructions are used only when the CPU supports them.
  18. Otherwise software encryption is used.
  19. config CRYPTO_DEV_PADLOCK_AES
  20. tristate "PadLock driver for AES algorithm"
  21. depends on CRYPTO_DEV_PADLOCK
  22. select CRYPTO_BLKCIPHER
  23. select CRYPTO_AES
  24. help
  25. Use VIA PadLock for AES algorithm.
  26. Available in VIA C3 and newer CPUs.
  27. If unsure say M. The compiled module will be
  28. called padlock-aes.
  29. config CRYPTO_DEV_PADLOCK_SHA
  30. tristate "PadLock driver for SHA1 and SHA256 algorithms"
  31. depends on CRYPTO_DEV_PADLOCK
  32. select CRYPTO_HASH
  33. select CRYPTO_SHA1
  34. select CRYPTO_SHA256
  35. help
  36. Use VIA PadLock for SHA1/SHA256 algorithms.
  37. Available in VIA C7 and newer processors.
  38. If unsure say M. The compiled module will be
  39. called padlock-sha.
  40. config CRYPTO_DEV_GEODE
  41. tristate "Support for the Geode LX AES engine"
  42. depends on X86_32 && PCI
  43. select CRYPTO_ALGAPI
  44. select CRYPTO_BLKCIPHER
  45. help
  46. Say 'Y' here to use the AMD Geode LX processor on-board AES
  47. engine for the CryptoAPI AES algorithm.
  48. To compile this driver as a module, choose M here: the module
  49. will be called geode-aes.
  50. config ZCRYPT
  51. tristate "Support for PCI-attached cryptographic adapters"
  52. depends on S390
  53. select HW_RANDOM
  54. help
  55. Select this option if you want to use a PCI-attached cryptographic
  56. adapter like:
  57. + PCI Cryptographic Accelerator (PCICA)
  58. + PCI Cryptographic Coprocessor (PCICC)
  59. + PCI-X Cryptographic Coprocessor (PCIXCC)
  60. + Crypto Express2 Coprocessor (CEX2C)
  61. + Crypto Express2 Accelerator (CEX2A)
  62. + Crypto Express3 Coprocessor (CEX3C)
  63. + Crypto Express3 Accelerator (CEX3A)
  64. config CRYPTO_SHA1_S390
  65. tristate "SHA1 digest algorithm"
  66. depends on S390
  67. select CRYPTO_HASH
  68. help
  69. This is the s390 hardware accelerated implementation of the
  70. SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
  71. It is available as of z990.
  72. config CRYPTO_SHA256_S390
  73. tristate "SHA256 digest algorithm"
  74. depends on S390
  75. select CRYPTO_HASH
  76. help
  77. This is the s390 hardware accelerated implementation of the
  78. SHA256 secure hash standard (DFIPS 180-2).
  79. It is available as of z9.
  80. config CRYPTO_SHA512_S390
  81. tristate "SHA384 and SHA512 digest algorithm"
  82. depends on S390
  83. select CRYPTO_HASH
  84. help
  85. This is the s390 hardware accelerated implementation of the
  86. SHA512 secure hash standard.
  87. It is available as of z10.
  88. config CRYPTO_DES_S390
  89. tristate "DES and Triple DES cipher algorithms"
  90. depends on S390
  91. select CRYPTO_ALGAPI
  92. select CRYPTO_BLKCIPHER
  93. help
  94. This is the s390 hardware accelerated implementation of the
  95. DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
  96. As of z990 the ECB and CBC mode are hardware accelerated.
  97. As of z196 the CTR mode is hardware accelerated.
  98. config CRYPTO_AES_S390
  99. tristate "AES cipher algorithms"
  100. depends on S390
  101. select CRYPTO_ALGAPI
  102. select CRYPTO_BLKCIPHER
  103. help
  104. This is the s390 hardware accelerated implementation of the
  105. AES cipher algorithms (FIPS-197).
  106. As of z9 the ECB and CBC modes are hardware accelerated
  107. for 128 bit keys.
  108. As of z10 the ECB and CBC modes are hardware accelerated
  109. for all AES key sizes.
  110. As of z196 the CTR mode is hardware accelerated for all AES
  111. key sizes and XTS mode is hardware accelerated for 256 and
  112. 512 bit keys.
  113. config S390_PRNG
  114. tristate "Pseudo random number generator device driver"
  115. depends on S390
  116. default "m"
  117. help
  118. Select this option if you want to use the s390 pseudo random number
  119. generator. The PRNG is part of the cryptographic processor functions
  120. and uses triple-DES to generate secure random numbers like the
  121. ANSI X9.17 standard. User-space programs access the
  122. pseudo-random-number device through the char device /dev/prandom.
  123. It is available as of z9.
  124. config CRYPTO_GHASH_S390
  125. tristate "GHASH digest algorithm"
  126. depends on S390
  127. select CRYPTO_HASH
  128. help
  129. This is the s390 hardware accelerated implementation of the
  130. GHASH message digest algorithm for GCM (Galois/Counter Mode).
  131. It is available as of z196.
  132. config CRYPTO_DEV_MV_CESA
  133. tristate "Marvell's Cryptographic Engine"
  134. depends on PLAT_ORION
  135. select CRYPTO_ALGAPI
  136. select CRYPTO_AES
  137. select CRYPTO_BLKCIPHER2
  138. select CRYPTO_HASH
  139. help
  140. This driver allows you to utilize the Cryptographic Engines and
  141. Security Accelerator (CESA) which can be found on the Marvell Orion
  142. and Kirkwood SoCs, such as QNAP's TS-209.
  143. Currently the driver supports AES in ECB and CBC mode without DMA.
  144. config CRYPTO_DEV_NIAGARA2
  145. tristate "Niagara2 Stream Processing Unit driver"
  146. select CRYPTO_DES
  147. select CRYPTO_ALGAPI
  148. depends on SPARC64
  149. help
  150. Each core of a Niagara2 processor contains a Stream
  151. Processing Unit, which itself contains several cryptographic
  152. sub-units. One set provides the Modular Arithmetic Unit,
  153. used for SSL offload. The other set provides the Cipher
  154. Group, which can perform encryption, decryption, hashing,
  155. checksumming, and raw copies.
  156. config CRYPTO_DEV_HIFN_795X
  157. tristate "Driver HIFN 795x crypto accelerator chips"
  158. select CRYPTO_DES
  159. select CRYPTO_ALGAPI
  160. select CRYPTO_BLKCIPHER
  161. select HW_RANDOM if CRYPTO_DEV_HIFN_795X_RNG
  162. depends on PCI
  163. depends on !ARCH_DMA_ADDR_T_64BIT
  164. help
  165. This option allows you to have support for HIFN 795x crypto adapters.
  166. config CRYPTO_DEV_HIFN_795X_RNG
  167. bool "HIFN 795x random number generator"
  168. depends on CRYPTO_DEV_HIFN_795X
  169. help
  170. Select this option if you want to enable the random number generator
  171. on the HIFN 795x crypto adapters.
  172. source drivers/crypto/caam/Kconfig
  173. config CRYPTO_DEV_TALITOS
  174. tristate "Talitos Freescale Security Engine (SEC)"
  175. select CRYPTO_ALGAPI
  176. select CRYPTO_AUTHENC
  177. select HW_RANDOM
  178. depends on FSL_SOC
  179. help
  180. Say 'Y' here to use the Freescale Security Engine (SEC)
  181. to offload cryptographic algorithm computation.
  182. The Freescale SEC is present on PowerQUICC 'E' processors, such
  183. as the MPC8349E and MPC8548E.
  184. To compile this driver as a module, choose M here: the module
  185. will be called talitos.
  186. config CRYPTO_DEV_IXP4XX
  187. tristate "Driver for IXP4xx crypto hardware acceleration"
  188. depends on ARCH_IXP4XX
  189. select CRYPTO_DES
  190. select CRYPTO_ALGAPI
  191. select CRYPTO_AUTHENC
  192. select CRYPTO_BLKCIPHER
  193. help
  194. Driver for the IXP4xx NPE crypto engine.
  195. config CRYPTO_DEV_PPC4XX
  196. tristate "Driver AMCC PPC4xx crypto accelerator"
  197. depends on PPC && 4xx
  198. select CRYPTO_HASH
  199. select CRYPTO_ALGAPI
  200. select CRYPTO_BLKCIPHER
  201. help
  202. This option allows you to have support for AMCC crypto acceleration.
  203. config CRYPTO_DEV_OMAP_SHAM
  204. tristate "Support for OMAP SHA1/MD5 hw accelerator"
  205. depends on ARCH_OMAP2 || ARCH_OMAP3
  206. select CRYPTO_SHA1
  207. select CRYPTO_MD5
  208. help
  209. OMAP processors have SHA1/MD5 hw accelerator. Select this if you
  210. want to use the OMAP module for SHA1/MD5 algorithms.
  211. config CRYPTO_DEV_OMAP_AES
  212. tristate "Support for OMAP AES hw engine"
  213. depends on ARCH_OMAP2 || ARCH_OMAP3
  214. select CRYPTO_AES
  215. help
  216. OMAP processors have AES module accelerator. Select this if you
  217. want to use the OMAP module for AES algorithms.
  218. config CRYPTO_DEV_PICOXCELL
  219. tristate "Support for picoXcell IPSEC and Layer2 crypto engines"
  220. depends on ARCH_PICOXCELL && HAVE_CLK
  221. select CRYPTO_AES
  222. select CRYPTO_AUTHENC
  223. select CRYPTO_ALGAPI
  224. select CRYPTO_DES
  225. select CRYPTO_CBC
  226. select CRYPTO_ECB
  227. select CRYPTO_SEQIV
  228. help
  229. This option enables support for the hardware offload engines in the
  230. Picochip picoXcell SoC devices. Select this for IPSEC ESP offload
  231. and for 3gpp Layer 2 ciphering support.
  232. Saying m here will build a module named pipcoxcell_crypto.
  233. config CRYPTO_DEV_S5P
  234. tristate "Support for Samsung S5PV210 crypto accelerator"
  235. depends on ARCH_S5PV210
  236. select CRYPTO_AES
  237. select CRYPTO_ALGAPI
  238. select CRYPTO_BLKCIPHER
  239. help
  240. This option allows you to have support for S5P crypto acceleration.
  241. Select this to offload Samsung S5PV210 or S5PC110 from AES
  242. algorithms execution.
  243. config CRYPTO_DEV_QCE40
  244. bool
  245. config CRYPTO_DEV_QCE50
  246. bool
  247. config FIPS_ENABLE
  248. bool "FIPS140-2 compliant build"
  249. default n
  250. help
  251. This flag is used to make current build FIPS140-2
  252. compliant. This flag will enable the patch of code
  253. which will perform this task. Please select Y here
  254. to enable.
  255. config CRYPTO_DEV_QCRYPTO
  256. tristate "Qualcomm Crypto accelerator"
  257. select CRYPTO_DES
  258. select CRYPTO_ALGAPI
  259. select CRYPTO_AUTHENC
  260. select CRYPTO_BLKCIPHER
  261. default n
  262. help
  263. This driver supports Qualcomm crypto acceleration.
  264. To compile this driver as a module, choose M here: the
  265. module will be called qcrypto.
  266. config CRYPTO_DEV_QCE
  267. tristate "Qualcomm Crypto Engine (QCE) module"
  268. select CRYPTO_DEV_QCE40 if ARCH_MSM8960 || ARCH_MSM9615
  269. select CRYPTO_DEV_QCE50 if ARCH_MSM8974 || ARCH_MSM9625 || ARCH_MSM8226 || ARCH_MSM8610
  270. default n
  271. help
  272. This driver supports Qualcomm Crypto Engine in MSM7x30, MSM8660
  273. MSM8x55, MSM8960 and MSM9615
  274. To compile this driver as a module, choose M here: the
  275. For MSM7x30 MSM8660 and MSM8x55 the module is called qce
  276. For MSM8960, APQ8064 and MSM9615 the module is called qce40
  277. For MSM8974 the module is called qce50
  278. config CRYPTO_DEV_QCEDEV
  279. tristate "QCEDEV Interface to CE module"
  280. default n
  281. help
  282. This driver supports Qualcomm QCEDEV Crypto in MSM7x30, MSM8660,
  283. MSM8960, MSM9615, APQ8064 and MSM8974.
  284. This exposes the interface to the QCE hardware accelerator via IOCTLs
  285. To compile this driver as a module, choose M here: the
  286. module will be called qcedev.
  287. config CRYPTO_DEV_OTA_CRYPTO
  288. tristate "OTA Crypto module"
  289. help
  290. This driver supports Qualcomm OTA Crypto in the FSM9xxx.
  291. To compile this driver as a module, choose M here: the
  292. module will be called ota_crypto.
  293. config CRYPTO_DEV_TEGRA_AES
  294. tristate "Support for TEGRA AES hw engine"
  295. depends on ARCH_TEGRA
  296. select CRYPTO_AES
  297. help
  298. TEGRA processors have AES module accelerator. Select this if you
  299. want to use the TEGRA module for AES algorithms.
  300. To compile this driver as a module, choose M here: the module
  301. will be called tegra-aes.
  302. endif # CRYPTO_HW