Home Explore Help
Sign In
ichrin
/
kernel_samsung_msm8974
Watch 1
Star 0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Tree: 6ab9bf52ed
Branches Tags
kernel_samsu...
/
arch
/
unicore32
/
include
/
mach
/
regs-nand.h

regs-nand.h 1.7 KB
History Raw

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980 
  1. /*
    2. 

  2.  * PKUnity NAND Controller Registers
    3. 

  3.  */
    4. 

  4. /*
    5. 

  5.  * ID Reg. 0 NAND_IDR0
    6. 

  6.  */
    7. 

  7. #define NAND_IDR0	(PKUNITY_NAND_BASE + 0x0000)
    8. 

  8. /*
    9. 

  9.  * ID Reg. 1 NAND_IDR1
    10. 

  10.  */
    11. 

  11. #define NAND_IDR1	(PKUNITY_NAND_BASE + 0x0004)
    12. 

  12. /*
    13. 

  13.  * ID Reg. 2 NAND_IDR2
    14. 

  14.  */
    15. 

  15. #define NAND_IDR2	(PKUNITY_NAND_BASE + 0x0008)
    16. 

  16. /*
    17. 

  17.  * ID Reg. 3 NAND_IDR3
    18. 

  18.  */
    19. 

  19. #define NAND_IDR3	(PKUNITY_NAND_BASE + 0x000C)
    20. 

  20. /*
    21. 

  21.  * Page Address Reg 0 NAND_PAR0
    22. 

  22.  */
    23. 

  23. #define NAND_PAR0	(PKUNITY_NAND_BASE + 0x0010)
    24. 

  24. /*
    25. 

  25.  * Page Address Reg 1 NAND_PAR1
    26. 

  26.  */
    27. 

  27. #define NAND_PAR1	(PKUNITY_NAND_BASE + 0x0014)
    28. 

  28. /*
    29. 

  29.  * Page Address Reg 2 NAND_PAR2
    30. 

  30.  */
    31. 

  31. #define NAND_PAR2	(PKUNITY_NAND_BASE + 0x0018)
    32. 

  32. /*
    33. 

  33.  * ECC Enable Reg NAND_ECCEN
    34. 

  34.  */
    35. 

  35. #define NAND_ECCEN	(PKUNITY_NAND_BASE + 0x001C)
    36. 

  36. /*
    37. 

  37.  * Buffer Reg NAND_BUF
    38. 

  38.  */
    39. 

  39. #define NAND_BUF	(PKUNITY_NAND_BASE + 0x0020)
    40. 

  40. /*
    41. 

  41.  * ECC Status Reg NAND_ECCSR
    42. 

  42.  */
    43. 

  43. #define NAND_ECCSR	(PKUNITY_NAND_BASE + 0x0024)
    44. 

  44. /*
    45. 

  45.  * Command Reg NAND_CMD
    46. 

  46.  */
    47. 

  47. #define NAND_CMD	(PKUNITY_NAND_BASE + 0x0028)
    48. 

  48. /*
    49. 

  49.  * DMA Configure Reg NAND_DMACR
    50. 

  50.  */
    51. 

  51. #define NAND_DMACR	(PKUNITY_NAND_BASE + 0x002C)
    52. 

  52. /*
    53. 

  53.  * Interrupt Reg NAND_IR
    54. 

  54.  */
    55. 

  55. #define NAND_IR		(PKUNITY_NAND_BASE + 0x0030)
    56. 

  56. /*
    57. 

  57.  * Interrupt Mask Reg NAND_IMR
    58. 

  58.  */
    59. 

  59. #define NAND_IMR	(PKUNITY_NAND_BASE + 0x0034)
    60. 

  60. /*
    61. 

  61.  * Chip Enable Reg NAND_CHIPEN
    62. 

  62.  */
    63. 

  63. #define NAND_CHIPEN	(PKUNITY_NAND_BASE + 0x0038)
    64. 

  64. /*
    65. 

  65.  * Address Reg NAND_ADDR
    66. 

  66.  */
    67. 

  67. #define NAND_ADDR	(PKUNITY_NAND_BASE + 0x003C)
    68. 

  68. 

  69. /*
    70. 

  70.  * Command bits NAND_CMD_CMD_MASK
    71. 

  71.  */
    72. 

  72. #define NAND_CMD_CMD_MASK		FMASK(4, 4)
    73. 

  73. #define NAND_CMD_CMD_READPAGE		FIELD(0x0, 4, 4)
    74. 

  74. #define NAND_CMD_CMD_ERASEBLOCK		FIELD(0x6, 4, 4)
    75. 

  75. #define NAND_CMD_CMD_READSTATUS		FIELD(0x7, 4, 4)
    76. 

  76. #define NAND_CMD_CMD_WRITEPAGE		FIELD(0x8, 4, 4)
    77. 

  77. #define NAND_CMD_CMD_READID		FIELD(0x9, 4, 4)
    78. 

  78. #define NAND_CMD_CMD_RESET		FIELD(0xf, 4, 4)
    79. 

  79. 

  80.