irq.h 2.8 KB

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  1. /*
  2. * Copyright 2010 Tilera Corporation. All Rights Reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation, version 2.
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11. * NON INFRINGEMENT. See the GNU General Public License for
  12. * more details.
  13. */
  14. #ifndef _ASM_TILE_IRQ_H
  15. #define _ASM_TILE_IRQ_H
  16. #include <linux/hardirq.h>
  17. /* The hypervisor interface provides 32 IRQs. */
  18. #define NR_IRQS 32
  19. /* IRQ numbers used for linux IPIs. */
  20. #define IRQ_RESCHEDULE 0
  21. #define irq_canonicalize(irq) (irq)
  22. void ack_bad_irq(unsigned int irq);
  23. /*
  24. * Different ways of handling interrupts. Tile interrupts are always
  25. * per-cpu; there is no global interrupt controller to implement
  26. * enable/disable. Most onboard devices can send their interrupts to
  27. * many tiles at the same time, and Tile-specific drivers know how to
  28. * deal with this.
  29. *
  30. * However, generic devices (usually PCIE based, sometimes GPIO)
  31. * expect that interrupts will fire on a single core at a time and
  32. * that the irq can be enabled or disabled from any core at any time.
  33. * We implement this by directing such interrupts to a single core.
  34. *
  35. * One added wrinkle is that PCI interrupts can be either
  36. * hardware-cleared (legacy interrupts) or software cleared (MSI).
  37. * Other generic device systems (GPIO) are always software-cleared.
  38. *
  39. * The enums below are used by drivers for onboard devices, including
  40. * the internals of PCI root complex and GPIO. They allow the driver
  41. * to tell the generic irq code what kind of interrupt is mapped to a
  42. * particular IRQ number.
  43. */
  44. enum {
  45. /* per-cpu interrupt; use enable/disable_percpu_irq() to mask */
  46. TILE_IRQ_PERCPU,
  47. /* global interrupt, hardware responsible for clearing. */
  48. TILE_IRQ_HW_CLEAR,
  49. /* global interrupt, software responsible for clearing. */
  50. TILE_IRQ_SW_CLEAR,
  51. };
  52. /*
  53. * Paravirtualized drivers should call this when they dynamically
  54. * allocate a new IRQ or discover an IRQ that was pre-allocated by the
  55. * hypervisor for use with their particular device. This gives the
  56. * IRQ subsystem an opportunity to do interrupt-type-specific
  57. * initialization.
  58. *
  59. * ISSUE: We should modify this API so that registering anything
  60. * except percpu interrupts also requires providing callback methods
  61. * for enabling and disabling the interrupt. This would allow the
  62. * generic IRQ code to proxy enable/disable_irq() calls back into the
  63. * PCI subsystem, which in turn could enable or disable the interrupt
  64. * at the PCI shim.
  65. */
  66. void tile_irq_activate(unsigned int irq, int tile_irq_type);
  67. void setup_irq_regs(void);
  68. #endif /* _ASM_TILE_IRQ_H */