pci-rc32434.c 7.3 KB

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  1. /*
  2. * BRIEF MODULE DESCRIPTION
  3. * PCI initialization for IDT EB434 board
  4. *
  5. * Copyright 2004 IDT Inc. (rischelp@idt.com)
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. *
  12. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  13. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  14. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  15. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  16. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  18. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  20. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22. *
  23. * You should have received a copy of the GNU General Public License along
  24. * with this program; if not, write to the Free Software Foundation, Inc.,
  25. * 675 Mass Ave, Cambridge, MA 02139, USA.
  26. */
  27. #include <linux/types.h>
  28. #include <linux/pci.h>
  29. #include <linux/kernel.h>
  30. #include <linux/init.h>
  31. #include <asm/mach-rc32434/rc32434.h>
  32. #include <asm/mach-rc32434/pci.h>
  33. #define PCI_ACCESS_READ 0
  34. #define PCI_ACCESS_WRITE 1
  35. /* define an unsigned array for the PCI registers */
  36. static unsigned int korina_cnfg_regs[25] = {
  37. KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
  38. KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
  39. KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
  40. KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
  41. KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
  42. KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
  43. };
  44. static struct resource rc32434_res_pci_mem1;
  45. static struct resource rc32434_res_pci_mem2;
  46. static struct resource rc32434_res_pci_mem1 = {
  47. .name = "PCI MEM1",
  48. .start = 0x50000000,
  49. .end = 0x5FFFFFFF,
  50. .flags = IORESOURCE_MEM,
  51. .parent = &rc32434_res_pci_mem1,
  52. .sibling = NULL,
  53. .child = &rc32434_res_pci_mem2
  54. };
  55. static struct resource rc32434_res_pci_mem2 = {
  56. .name = "PCI Mem2",
  57. .start = 0x60000000,
  58. .end = 0x6FFFFFFF,
  59. .flags = IORESOURCE_MEM,
  60. .parent = &rc32434_res_pci_mem1,
  61. .sibling = NULL,
  62. .child = NULL
  63. };
  64. static struct resource rc32434_res_pci_io1 = {
  65. .name = "PCI I/O1",
  66. .start = 0x18800000,
  67. .end = 0x188FFFFF,
  68. .flags = IORESOURCE_IO,
  69. };
  70. extern struct pci_ops rc32434_pci_ops;
  71. #define PCI_MEM1_START PCI_ADDR_START
  72. #define PCI_MEM1_END (PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1)
  73. #define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN)
  74. #define PCI_MEM2_END (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) - 1)
  75. #define PCI_IO1_START (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN))
  76. #define PCI_IO1_END \
  77. (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1)
  78. #define PCI_IO2_START \
  79. (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN)
  80. #define PCI_IO2_END \
  81. (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1)
  82. struct pci_controller rc32434_controller2;
  83. struct pci_controller rc32434_controller = {
  84. .pci_ops = &rc32434_pci_ops,
  85. .mem_resource = &rc32434_res_pci_mem1,
  86. .io_resource = &rc32434_res_pci_io1,
  87. .mem_offset = 0,
  88. .io_offset = 0,
  89. };
  90. #ifdef __MIPSEB__
  91. #define PCI_ENDIAN_FLAG PCILBAC_sb_m
  92. #else
  93. #define PCI_ENDIAN_FLAG 0
  94. #endif
  95. static int __init rc32434_pcibridge_init(void)
  96. {
  97. unsigned int pcicvalue, pcicdata = 0;
  98. unsigned int dummyread, pcicntlval;
  99. int loopCount;
  100. unsigned int pci_config_addr;
  101. pcicvalue = rc32434_pci->pcic;
  102. pcicvalue = (pcicvalue >> PCIM_SHFT) & PCIM_BIT_LEN;
  103. if (!((pcicvalue == PCIM_H_EA) ||
  104. (pcicvalue == PCIM_H_IA_FIX) ||
  105. (pcicvalue == PCIM_H_IA_RR))) {
  106. pr_err("PCI init error!!!\n");
  107. /* Not in Host Mode, return ERROR */
  108. return -1;
  109. }
  110. /* Enables the Idle Grant mode, Arbiter Parking */
  111. pcicdata |= (PCI_CTL_IGM | PCI_CTL_EAP | PCI_CTL_EN);
  112. rc32434_pci->pcic = pcicdata; /* Enable the PCI bus Interface */
  113. /* Zero out the PCI status & PCI Status Mask */
  114. for (;;) {
  115. pcicdata = rc32434_pci->pcis;
  116. if (!(pcicdata & PCI_STAT_RIP))
  117. break;
  118. }
  119. rc32434_pci->pcis = 0;
  120. rc32434_pci->pcism = 0xFFFFFFFF;
  121. /* Zero out the PCI decoupled registers */
  122. rc32434_pci->pcidac = 0; /*
  123. * disable PCI decoupled accesses at
  124. * initialization
  125. */
  126. rc32434_pci->pcidas = 0; /* clear the status */
  127. rc32434_pci->pcidasm = 0x0000007F; /* Mask all the interrupts */
  128. /* Mask PCI Messaging Interrupts */
  129. rc32434_pci_msg->pciiic = 0;
  130. rc32434_pci_msg->pciiim = 0xFFFFFFFF;
  131. rc32434_pci_msg->pciioic = 0;
  132. rc32434_pci_msg->pciioim = 0;
  133. /* Setup PCILB0 as Memory Window */
  134. rc32434_pci->pcilba[0].address = (unsigned int) (PCI_ADDR_START);
  135. /* setup the PCI map address as same as the local address */
  136. rc32434_pci->pcilba[0].mapping = (unsigned int) (PCI_ADDR_START);
  137. /* Setup PCILBA1 as MEM */
  138. rc32434_pci->pcilba[0].control =
  139. (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
  140. dummyread = rc32434_pci->pcilba[0].control; /* flush the CPU write Buffers */
  141. rc32434_pci->pcilba[1].address = 0x60000000;
  142. rc32434_pci->pcilba[1].mapping = 0x60000000;
  143. /* setup PCILBA2 as IO Window */
  144. rc32434_pci->pcilba[1].control =
  145. (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
  146. dummyread = rc32434_pci->pcilba[1].control; /* flush the CPU write Buffers */
  147. rc32434_pci->pcilba[2].address = 0x18C00000;
  148. rc32434_pci->pcilba[2].mapping = 0x18FFFFFF;
  149. /* setup PCILBA2 as IO Window */
  150. rc32434_pci->pcilba[2].control =
  151. (((SIZE_4MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
  152. dummyread = rc32434_pci->pcilba[2].control; /* flush the CPU write Buffers */
  153. /* Setup PCILBA3 as IO Window */
  154. rc32434_pci->pcilba[3].address = 0x18800000;
  155. rc32434_pci->pcilba[3].mapping = 0x18800000;
  156. rc32434_pci->pcilba[3].control =
  157. ((((SIZE_1MB & 0x1ff) << PCI_LBAC_SIZE_BIT) | PCI_LBAC_MSI) |
  158. PCI_ENDIAN_FLAG);
  159. dummyread = rc32434_pci->pcilba[3].control; /* flush the CPU write Buffers */
  160. pci_config_addr = (unsigned int) (0x80000004);
  161. for (loopCount = 0; loopCount < 24; loopCount++) {
  162. rc32434_pci->pcicfga = pci_config_addr;
  163. dummyread = rc32434_pci->pcicfga;
  164. rc32434_pci->pcicfgd = korina_cnfg_regs[loopCount];
  165. dummyread = rc32434_pci->pcicfgd;
  166. pci_config_addr += 4;
  167. }
  168. rc32434_pci->pcitc =
  169. (unsigned int) ((PCITC_RTIMER_VAL & 0xff) << PCI_TC_RTIMER_BIT) |
  170. ((PCITC_DTIMER_VAL & 0xff) << PCI_TC_DTIMER_BIT);
  171. pcicntlval = rc32434_pci->pcic;
  172. pcicntlval &= ~PCI_CTL_TNR;
  173. rc32434_pci->pcic = pcicntlval;
  174. pcicntlval = rc32434_pci->pcic;
  175. return 0;
  176. }
  177. static int __init rc32434_pci_init(void)
  178. {
  179. void __iomem *io_map_base;
  180. pr_info("PCI: Initializing PCI\n");
  181. ioport_resource.start = rc32434_res_pci_io1.start;
  182. ioport_resource.end = rc32434_res_pci_io1.end;
  183. rc32434_pcibridge_init();
  184. io_map_base = ioremap(rc32434_res_pci_io1.start,
  185. resource_size(&rc32434_res_pci_io1));
  186. if (!io_map_base)
  187. return -ENOMEM;
  188. rc32434_controller.io_map_base =
  189. (unsigned long)io_map_base - rc32434_res_pci_io1.start;
  190. register_pci_controller(&rc32434_controller);
  191. rc32434_sync();
  192. return 0;
  193. }
  194. arch_initcall(rc32434_pci_init);