ops-msc.c 4.0 KB

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  1. /*
  2. * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
  3. * All rights reserved.
  4. * Authors: Carsten Langgaard <carstenl@mips.com>
  5. * Maciej W. Rozycki <macro@mips.com>
  6. * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
  7. *
  8. * This program is free software; you can distribute it and/or modify it
  9. * under the terms of the GNU General Public License (Version 2) as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15. * for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along
  18. * with this program; if not, write to the Free Software Foundation, Inc.,
  19. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  20. *
  21. * MIPS boards specific PCI support.
  22. *
  23. */
  24. #include <linux/types.h>
  25. #include <linux/pci.h>
  26. #include <linux/kernel.h>
  27. #include <linux/init.h>
  28. #include <asm/mips-boards/msc01_pci.h>
  29. #define PCI_ACCESS_READ 0
  30. #define PCI_ACCESS_WRITE 1
  31. /*
  32. * PCI configuration cycle AD bus definition
  33. */
  34. /* Type 0 */
  35. #define PCI_CFG_TYPE0_REG_SHF 0
  36. #define PCI_CFG_TYPE0_FUNC_SHF 8
  37. /* Type 1 */
  38. #define PCI_CFG_TYPE1_REG_SHF 0
  39. #define PCI_CFG_TYPE1_FUNC_SHF 8
  40. #define PCI_CFG_TYPE1_DEV_SHF 11
  41. #define PCI_CFG_TYPE1_BUS_SHF 16
  42. static int msc_pcibios_config_access(unsigned char access_type,
  43. struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
  44. {
  45. unsigned char busnum = bus->number;
  46. u32 intr;
  47. /* Clear status register bits. */
  48. MSC_WRITE(MSC01_PCI_INTSTAT,
  49. (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
  50. MSC_WRITE(MSC01_PCI_CFGADDR,
  51. ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) |
  52. (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) |
  53. (PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) |
  54. ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF)));
  55. /* Perform access */
  56. if (access_type == PCI_ACCESS_WRITE)
  57. MSC_WRITE(MSC01_PCI_CFGDATA, *data);
  58. else
  59. MSC_READ(MSC01_PCI_CFGDATA, *data);
  60. /* Detect Master/Target abort */
  61. MSC_READ(MSC01_PCI_INTSTAT, intr);
  62. if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) {
  63. /* Error occurred */
  64. /* Clear bits */
  65. MSC_WRITE(MSC01_PCI_INTSTAT,
  66. (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
  67. return -1;
  68. }
  69. return 0;
  70. }
  71. /*
  72. * We can't address 8 and 16 bit words directly. Instead we have to
  73. * read/write a 32bit word and mask/modify the data we actually want.
  74. */
  75. static int msc_pcibios_read(struct pci_bus *bus, unsigned int devfn,
  76. int where, int size, u32 * val)
  77. {
  78. u32 data = 0;
  79. if ((size == 2) && (where & 1))
  80. return PCIBIOS_BAD_REGISTER_NUMBER;
  81. else if ((size == 4) && (where & 3))
  82. return PCIBIOS_BAD_REGISTER_NUMBER;
  83. if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
  84. &data))
  85. return -1;
  86. if (size == 1)
  87. *val = (data >> ((where & 3) << 3)) & 0xff;
  88. else if (size == 2)
  89. *val = (data >> ((where & 3) << 3)) & 0xffff;
  90. else
  91. *val = data;
  92. return PCIBIOS_SUCCESSFUL;
  93. }
  94. static int msc_pcibios_write(struct pci_bus *bus, unsigned int devfn,
  95. int where, int size, u32 val)
  96. {
  97. u32 data = 0;
  98. if ((size == 2) && (where & 1))
  99. return PCIBIOS_BAD_REGISTER_NUMBER;
  100. else if ((size == 4) && (where & 3))
  101. return PCIBIOS_BAD_REGISTER_NUMBER;
  102. if (size == 4)
  103. data = val;
  104. else {
  105. if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
  106. where, &data))
  107. return -1;
  108. if (size == 1)
  109. data = (data & ~(0xff << ((where & 3) << 3))) |
  110. (val << ((where & 3) << 3));
  111. else if (size == 2)
  112. data = (data & ~(0xffff << ((where & 3) << 3))) |
  113. (val << ((where & 3) << 3));
  114. }
  115. if (msc_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
  116. &data))
  117. return -1;
  118. return PCIBIOS_SUCCESSFUL;
  119. }
  120. struct pci_ops msc_pci_ops = {
  121. .read = msc_pcibios_read,
  122. .write = msc_pcibios_write
  123. };