fixup-malta.c 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104
  1. #include <linux/init.h>
  2. #include <linux/pci.h>
  3. /* PCI interrupt pins */
  4. #define PCIA 1
  5. #define PCIB 2
  6. #define PCIC 3
  7. #define PCID 4
  8. /* This table is filled in by interrogating the PIIX4 chip */
  9. static char pci_irq[5] __initdata;
  10. static char irq_tab[][5] __initdata = {
  11. /* INTA INTB INTC INTD */
  12. {0, 0, 0, 0, 0 }, /* 0: GT64120 PCI bridge */
  13. {0, 0, 0, 0, 0 }, /* 1: Unused */
  14. {0, 0, 0, 0, 0 }, /* 2: Unused */
  15. {0, 0, 0, 0, 0 }, /* 3: Unused */
  16. {0, 0, 0, 0, 0 }, /* 4: Unused */
  17. {0, 0, 0, 0, 0 }, /* 5: Unused */
  18. {0, 0, 0, 0, 0 }, /* 6: Unused */
  19. {0, 0, 0, 0, 0 }, /* 7: Unused */
  20. {0, 0, 0, 0, 0 }, /* 8: Unused */
  21. {0, 0, 0, 0, 0 }, /* 9: Unused */
  22. {0, 0, 0, 0, PCID }, /* 10: PIIX4 USB */
  23. {0, PCIB, 0, 0, 0 }, /* 11: AMD 79C973 Ethernet */
  24. {0, PCIC, 0, 0, 0 }, /* 12: Crystal 4281 Sound */
  25. {0, 0, 0, 0, 0 }, /* 13: Unused */
  26. {0, 0, 0, 0, 0 }, /* 14: Unused */
  27. {0, 0, 0, 0, 0 }, /* 15: Unused */
  28. {0, 0, 0, 0, 0 }, /* 16: Unused */
  29. {0, 0, 0, 0, 0 }, /* 17: Bonito/SOC-it PCI Bridge*/
  30. {0, PCIA, PCIB, PCIC, PCID }, /* 18: PCI Slot 1 */
  31. {0, PCIB, PCIC, PCID, PCIA }, /* 19: PCI Slot 2 */
  32. {0, PCIC, PCID, PCIA, PCIB }, /* 20: PCI Slot 3 */
  33. {0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */
  34. };
  35. int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  36. {
  37. int virq;
  38. virq = irq_tab[slot][pin];
  39. return pci_irq[virq];
  40. }
  41. /* Do platform specific device initialization at pci_enable_device() time */
  42. int pcibios_plat_dev_init(struct pci_dev *dev)
  43. {
  44. return 0;
  45. }
  46. static void __init malta_piix_func0_fixup(struct pci_dev *pdev)
  47. {
  48. unsigned char reg_val;
  49. static int piixirqmap[16] __initdata = { /* PIIX PIRQC[A:D] irq mappings */
  50. 0, 0, 0, 3,
  51. 4, 5, 6, 7,
  52. 0, 9, 10, 11,
  53. 12, 0, 14, 15
  54. };
  55. int i;
  56. /* Interrogate PIIX4 to get PCI IRQ mapping */
  57. for (i = 0; i <= 3; i++) {
  58. pci_read_config_byte(pdev, 0x60+i, &reg_val);
  59. if (reg_val & 0x80)
  60. pci_irq[PCIA+i] = 0; /* Disabled */
  61. else
  62. pci_irq[PCIA+i] = piixirqmap[reg_val & 15];
  63. }
  64. /* Done by YAMON 2.00 onwards */
  65. if (PCI_SLOT(pdev->devfn) == 10) {
  66. /*
  67. * Set top of main memory accessible by ISA or DMA
  68. * devices to 16 Mb.
  69. */
  70. pci_read_config_byte(pdev, 0x69, &reg_val);
  71. pci_write_config_byte(pdev, 0x69, reg_val | 0xf0);
  72. }
  73. }
  74. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
  75. malta_piix_func0_fixup);
  76. static void __init malta_piix_func1_fixup(struct pci_dev *pdev)
  77. {
  78. unsigned char reg_val;
  79. /* Done by YAMON 2.02 onwards */
  80. if (PCI_SLOT(pdev->devfn) == 10) {
  81. /*
  82. * IDE Decode enable.
  83. */
  84. pci_read_config_byte(pdev, 0x41, &reg_val);
  85. pci_write_config_byte(pdev, 0x41, reg_val|0x80);
  86. pci_read_config_byte(pdev, 0x43, &reg_val);
  87. pci_write_config_byte(pdev, 0x43, reg_val|0x80);
  88. }
  89. }
  90. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
  91. malta_piix_func1_fixup);