mach-pcm043.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417
  1. /*
  2. * Copyright (C) 2009 Sascha Hauer, Pengutronix
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <linux/types.h>
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/mtd/physmap.h>
  18. #include <linux/mtd/plat-ram.h>
  19. #include <linux/memory.h>
  20. #include <linux/gpio.h>
  21. #include <linux/smc911x.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/delay.h>
  24. #include <linux/i2c.h>
  25. #include <linux/i2c/at24.h>
  26. #include <linux/usb/otg.h>
  27. #include <linux/usb/ulpi.h>
  28. #include <asm/mach-types.h>
  29. #include <asm/mach/arch.h>
  30. #include <asm/mach/time.h>
  31. #include <asm/mach/map.h>
  32. #include <mach/hardware.h>
  33. #include <mach/common.h>
  34. #include <mach/iomux-mx35.h>
  35. #include <mach/ulpi.h>
  36. #include "devices-imx35.h"
  37. static const struct fb_videomode fb_modedb[] = {
  38. {
  39. /* 240x320 @ 60 Hz */
  40. .name = "Sharp-LQ035Q7",
  41. .refresh = 60,
  42. .xres = 240,
  43. .yres = 320,
  44. .pixclock = 185925,
  45. .left_margin = 9,
  46. .right_margin = 16,
  47. .upper_margin = 7,
  48. .lower_margin = 9,
  49. .hsync_len = 1,
  50. .vsync_len = 1,
  51. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
  52. .vmode = FB_VMODE_NONINTERLACED,
  53. .flag = 0,
  54. }, {
  55. /* 240x320 @ 60 Hz */
  56. .name = "TX090",
  57. .refresh = 60,
  58. .xres = 240,
  59. .yres = 320,
  60. .pixclock = 38255,
  61. .left_margin = 144,
  62. .right_margin = 0,
  63. .upper_margin = 7,
  64. .lower_margin = 40,
  65. .hsync_len = 96,
  66. .vsync_len = 1,
  67. .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
  68. .vmode = FB_VMODE_NONINTERLACED,
  69. .flag = 0,
  70. },
  71. };
  72. static const struct ipu_platform_data mx3_ipu_data __initconst = {
  73. .irq_base = MXC_IPU_IRQ_START,
  74. };
  75. static struct mx3fb_platform_data mx3fb_pdata __initdata = {
  76. .name = "Sharp-LQ035Q7",
  77. .mode = fb_modedb,
  78. .num_modes = ARRAY_SIZE(fb_modedb),
  79. };
  80. static struct physmap_flash_data pcm043_flash_data = {
  81. .width = 2,
  82. };
  83. static struct resource pcm043_flash_resource = {
  84. .start = 0xa0000000,
  85. .end = 0xa1ffffff,
  86. .flags = IORESOURCE_MEM,
  87. };
  88. static struct platform_device pcm043_flash = {
  89. .name = "physmap-flash",
  90. .id = 0,
  91. .dev = {
  92. .platform_data = &pcm043_flash_data,
  93. },
  94. .resource = &pcm043_flash_resource,
  95. .num_resources = 1,
  96. };
  97. static const struct imxuart_platform_data uart_pdata __initconst = {
  98. .flags = IMXUART_HAVE_RTSCTS,
  99. };
  100. static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
  101. .bitrate = 50000,
  102. };
  103. static struct at24_platform_data board_eeprom = {
  104. .byte_len = 4096,
  105. .page_size = 32,
  106. .flags = AT24_FLAG_ADDR16,
  107. };
  108. static struct i2c_board_info pcm043_i2c_devices[] = {
  109. {
  110. I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
  111. .platform_data = &board_eeprom,
  112. }, {
  113. I2C_BOARD_INFO("pcf8563", 0x51),
  114. },
  115. };
  116. static struct platform_device *devices[] __initdata = {
  117. &pcm043_flash,
  118. };
  119. static iomux_v3_cfg_t pcm043_pads[] = {
  120. /* UART1 */
  121. MX35_PAD_CTS1__UART1_CTS,
  122. MX35_PAD_RTS1__UART1_RTS,
  123. MX35_PAD_TXD1__UART1_TXD_MUX,
  124. MX35_PAD_RXD1__UART1_RXD_MUX,
  125. /* UART2 */
  126. MX35_PAD_CTS2__UART2_CTS,
  127. MX35_PAD_RTS2__UART2_RTS,
  128. MX35_PAD_TXD2__UART2_TXD_MUX,
  129. MX35_PAD_RXD2__UART2_RXD_MUX,
  130. /* FEC */
  131. MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
  132. MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
  133. MX35_PAD_FEC_RX_DV__FEC_RX_DV,
  134. MX35_PAD_FEC_COL__FEC_COL,
  135. MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
  136. MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
  137. MX35_PAD_FEC_TX_EN__FEC_TX_EN,
  138. MX35_PAD_FEC_MDC__FEC_MDC,
  139. MX35_PAD_FEC_MDIO__FEC_MDIO,
  140. MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
  141. MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
  142. MX35_PAD_FEC_CRS__FEC_CRS,
  143. MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
  144. MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
  145. MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
  146. MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
  147. MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
  148. MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
  149. /* I2C1 */
  150. MX35_PAD_I2C1_CLK__I2C1_SCL,
  151. MX35_PAD_I2C1_DAT__I2C1_SDA,
  152. /* Display */
  153. MX35_PAD_LD0__IPU_DISPB_DAT_0,
  154. MX35_PAD_LD1__IPU_DISPB_DAT_1,
  155. MX35_PAD_LD2__IPU_DISPB_DAT_2,
  156. MX35_PAD_LD3__IPU_DISPB_DAT_3,
  157. MX35_PAD_LD4__IPU_DISPB_DAT_4,
  158. MX35_PAD_LD5__IPU_DISPB_DAT_5,
  159. MX35_PAD_LD6__IPU_DISPB_DAT_6,
  160. MX35_PAD_LD7__IPU_DISPB_DAT_7,
  161. MX35_PAD_LD8__IPU_DISPB_DAT_8,
  162. MX35_PAD_LD9__IPU_DISPB_DAT_9,
  163. MX35_PAD_LD10__IPU_DISPB_DAT_10,
  164. MX35_PAD_LD11__IPU_DISPB_DAT_11,
  165. MX35_PAD_LD12__IPU_DISPB_DAT_12,
  166. MX35_PAD_LD13__IPU_DISPB_DAT_13,
  167. MX35_PAD_LD14__IPU_DISPB_DAT_14,
  168. MX35_PAD_LD15__IPU_DISPB_DAT_15,
  169. MX35_PAD_LD16__IPU_DISPB_DAT_16,
  170. MX35_PAD_LD17__IPU_DISPB_DAT_17,
  171. MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
  172. MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
  173. MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
  174. MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
  175. MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
  176. MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
  177. MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
  178. /* gpio */
  179. MX35_PAD_ATA_CS0__GPIO2_6,
  180. /* USB host */
  181. MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
  182. MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
  183. /* SSI */
  184. MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
  185. MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
  186. MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
  187. MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
  188. /* CAN2 */
  189. MX35_PAD_TX5_RX0__CAN2_TXCAN,
  190. MX35_PAD_TX4_RX1__CAN2_RXCAN,
  191. /* esdhc */
  192. MX35_PAD_SD1_CMD__ESDHC1_CMD,
  193. MX35_PAD_SD1_CLK__ESDHC1_CLK,
  194. MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
  195. MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
  196. MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
  197. MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
  198. MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */
  199. MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */
  200. };
  201. #define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31)
  202. #define AC97_GPIO_TXD IMX_GPIO_NR(2, 28)
  203. #define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
  204. #define SD1_GPIO_WP IMX_GPIO_NR(2, 23)
  205. #define SD1_GPIO_CD IMX_GPIO_NR(2, 24)
  206. static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
  207. {
  208. iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
  209. iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
  210. int ret;
  211. ret = gpio_request(AC97_GPIO_TXFS, "SSI");
  212. if (ret) {
  213. printk("failed to get GPIO_TXFS: %d\n", ret);
  214. return;
  215. }
  216. mxc_iomux_v3_setup_pad(txfs_gpio);
  217. /* warm reset */
  218. gpio_direction_output(AC97_GPIO_TXFS, 1);
  219. udelay(2);
  220. gpio_set_value(AC97_GPIO_TXFS, 0);
  221. gpio_free(AC97_GPIO_TXFS);
  222. mxc_iomux_v3_setup_pad(txfs);
  223. }
  224. static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
  225. {
  226. iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
  227. iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
  228. iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
  229. iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
  230. iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
  231. int ret;
  232. ret = gpio_request(AC97_GPIO_TXFS, "SSI");
  233. if (ret)
  234. goto err1;
  235. ret = gpio_request(AC97_GPIO_TXD, "SSI");
  236. if (ret)
  237. goto err2;
  238. ret = gpio_request(AC97_GPIO_RESET, "SSI");
  239. if (ret)
  240. goto err3;
  241. mxc_iomux_v3_setup_pad(txfs_gpio);
  242. mxc_iomux_v3_setup_pad(txd_gpio);
  243. mxc_iomux_v3_setup_pad(reset_gpio);
  244. gpio_direction_output(AC97_GPIO_TXFS, 0);
  245. gpio_direction_output(AC97_GPIO_TXD, 0);
  246. /* cold reset */
  247. gpio_direction_output(AC97_GPIO_RESET, 0);
  248. udelay(10);
  249. gpio_direction_output(AC97_GPIO_RESET, 1);
  250. mxc_iomux_v3_setup_pad(txd);
  251. mxc_iomux_v3_setup_pad(txfs);
  252. gpio_free(AC97_GPIO_RESET);
  253. err3:
  254. gpio_free(AC97_GPIO_TXD);
  255. err2:
  256. gpio_free(AC97_GPIO_TXFS);
  257. err1:
  258. if (ret)
  259. printk("%s failed with %d\n", __func__, ret);
  260. mdelay(1);
  261. }
  262. static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
  263. .ac97_reset = pcm043_ac97_cold_reset,
  264. .ac97_warm_reset = pcm043_ac97_warm_reset,
  265. .flags = IMX_SSI_USE_AC97,
  266. };
  267. static const struct mxc_nand_platform_data
  268. pcm037_nand_board_info __initconst = {
  269. .width = 1,
  270. .hw_ecc = 1,
  271. };
  272. static int pcm043_otg_init(struct platform_device *pdev)
  273. {
  274. return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
  275. }
  276. static struct mxc_usbh_platform_data otg_pdata __initdata = {
  277. .init = pcm043_otg_init,
  278. .portsc = MXC_EHCI_MODE_UTMI,
  279. };
  280. static int pcm043_usbh1_init(struct platform_device *pdev)
  281. {
  282. return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
  283. MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
  284. }
  285. static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
  286. .init = pcm043_usbh1_init,
  287. .portsc = MXC_EHCI_MODE_SERIAL,
  288. };
  289. static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
  290. .operating_mode = FSL_USB2_DR_DEVICE,
  291. .phy_mode = FSL_USB2_PHY_UTMI,
  292. };
  293. static int otg_mode_host;
  294. static int __init pcm043_otg_mode(char *options)
  295. {
  296. if (!strcmp(options, "host"))
  297. otg_mode_host = 1;
  298. else if (!strcmp(options, "device"))
  299. otg_mode_host = 0;
  300. else
  301. pr_info("otg_mode neither \"host\" nor \"device\". "
  302. "Defaulting to device\n");
  303. return 0;
  304. }
  305. __setup("otg_mode=", pcm043_otg_mode);
  306. static struct esdhc_platform_data sd1_pdata = {
  307. .wp_gpio = SD1_GPIO_WP,
  308. .cd_gpio = SD1_GPIO_CD,
  309. .wp_type = ESDHC_WP_GPIO,
  310. .cd_type = ESDHC_CD_GPIO,
  311. };
  312. /*
  313. * Board specific initialization.
  314. */
  315. static void __init pcm043_init(void)
  316. {
  317. imx35_soc_init();
  318. mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
  319. imx35_add_fec(NULL);
  320. platform_add_devices(devices, ARRAY_SIZE(devices));
  321. imx35_add_imx2_wdt(NULL);
  322. imx35_add_imx_uart0(&uart_pdata);
  323. imx35_add_mxc_nand(&pcm037_nand_board_info);
  324. imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
  325. imx35_add_imx_uart1(&uart_pdata);
  326. i2c_register_board_info(0, pcm043_i2c_devices,
  327. ARRAY_SIZE(pcm043_i2c_devices));
  328. imx35_add_imx_i2c0(&pcm043_i2c0_data);
  329. imx35_add_ipu_core(&mx3_ipu_data);
  330. imx35_add_mx3_sdc_fb(&mx3fb_pdata);
  331. if (otg_mode_host) {
  332. otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
  333. ULPI_OTG_DRVVBUS_EXT);
  334. if (otg_pdata.otg)
  335. imx35_add_mxc_ehci_otg(&otg_pdata);
  336. }
  337. imx35_add_mxc_ehci_hs(&usbh1_pdata);
  338. if (!otg_mode_host)
  339. imx35_add_fsl_usb2_udc(&otg_device_pdata);
  340. imx35_add_flexcan1(NULL);
  341. imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
  342. }
  343. static void __init pcm043_timer_init(void)
  344. {
  345. mx35_clocks_init();
  346. }
  347. struct sys_timer pcm043_timer = {
  348. .init = pcm043_timer_init,
  349. };
  350. MACHINE_START(PCM043, "Phytec Phycore pcm043")
  351. /* Maintainer: Pengutronix */
  352. .atag_offset = 0x100,
  353. .map_io = mx35_map_io,
  354. .init_early = imx35_init_early,
  355. .init_irq = mx35_init_irq,
  356. .handle_irq = imx35_handle_irq,
  357. .timer = &pcm043_timer,
  358. .init_machine = pcm043_init,
  359. .restart = mxc_restart,
  360. MACHINE_END