cns3420vb.c 4.8 KB

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  1. /*
  2. * Cavium Networks CNS3420 Validation Board
  3. *
  4. * Copyright 2000 Deep Blue Solutions Ltd
  5. * Copyright 2008 ARM Limited
  6. * Copyright 2008 Cavium Networks
  7. * Scott Shu
  8. * Copyright 2010 MontaVista Software, LLC.
  9. * Anton Vorontsov <avorontsov@mvista.com>
  10. *
  11. * This file is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License, Version 2, as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/kernel.h>
  17. #include <linux/compiler.h>
  18. #include <linux/io.h>
  19. #include <linux/dma-mapping.h>
  20. #include <linux/serial_core.h>
  21. #include <linux/serial_8250.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/mtd/mtd.h>
  24. #include <linux/mtd/physmap.h>
  25. #include <linux/mtd/partitions.h>
  26. #include <asm/setup.h>
  27. #include <asm/mach-types.h>
  28. #include <asm/hardware/gic.h>
  29. #include <asm/mach/arch.h>
  30. #include <asm/mach/map.h>
  31. #include <asm/mach/time.h>
  32. #include <mach/cns3xxx.h>
  33. #include <mach/irqs.h>
  34. #include "core.h"
  35. #include "devices.h"
  36. /*
  37. * NOR Flash
  38. */
  39. static struct mtd_partition cns3420_nor_partitions[] = {
  40. {
  41. .name = "uboot",
  42. .size = 0x00040000,
  43. .offset = 0,
  44. .mask_flags = MTD_WRITEABLE,
  45. }, {
  46. .name = "kernel",
  47. .size = 0x004C0000,
  48. .offset = MTDPART_OFS_APPEND,
  49. }, {
  50. .name = "filesystem",
  51. .size = 0x7000000,
  52. .offset = MTDPART_OFS_APPEND,
  53. }, {
  54. .name = "filesystem2",
  55. .size = 0x0AE0000,
  56. .offset = MTDPART_OFS_APPEND,
  57. }, {
  58. .name = "ubootenv",
  59. .size = MTDPART_SIZ_FULL,
  60. .offset = MTDPART_OFS_APPEND,
  61. },
  62. };
  63. static struct physmap_flash_data cns3420_nor_pdata = {
  64. .width = 2,
  65. .parts = cns3420_nor_partitions,
  66. .nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
  67. };
  68. static struct resource cns3420_nor_res = {
  69. .start = CNS3XXX_FLASH_BASE,
  70. .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
  71. .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
  72. };
  73. static struct platform_device cns3420_nor_pdev = {
  74. .name = "physmap-flash",
  75. .id = 0,
  76. .resource = &cns3420_nor_res,
  77. .num_resources = 1,
  78. .dev = {
  79. .platform_data = &cns3420_nor_pdata,
  80. },
  81. };
  82. /*
  83. * UART
  84. */
  85. static void __init cns3420_early_serial_setup(void)
  86. {
  87. #ifdef CONFIG_SERIAL_8250_CONSOLE
  88. static struct uart_port cns3420_serial_port = {
  89. .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
  90. .mapbase = CNS3XXX_UART0_BASE,
  91. .irq = IRQ_CNS3XXX_UART0,
  92. .iotype = UPIO_MEM,
  93. .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
  94. .regshift = 2,
  95. .uartclk = 24000000,
  96. .line = 0,
  97. .type = PORT_16550A,
  98. .fifosize = 16,
  99. };
  100. early_serial_setup(&cns3420_serial_port);
  101. #endif
  102. }
  103. /*
  104. * USB
  105. */
  106. static struct resource cns3xxx_usb_ehci_resources[] = {
  107. [0] = {
  108. .start = CNS3XXX_USB_BASE,
  109. .end = CNS3XXX_USB_BASE + SZ_16M - 1,
  110. .flags = IORESOURCE_MEM,
  111. },
  112. [1] = {
  113. .start = IRQ_CNS3XXX_USB_EHCI,
  114. .flags = IORESOURCE_IRQ,
  115. },
  116. };
  117. static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
  118. static struct platform_device cns3xxx_usb_ehci_device = {
  119. .name = "cns3xxx-ehci",
  120. .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
  121. .resource = cns3xxx_usb_ehci_resources,
  122. .dev = {
  123. .dma_mask = &cns3xxx_usb_ehci_dma_mask,
  124. .coherent_dma_mask = DMA_BIT_MASK(32),
  125. },
  126. };
  127. static struct resource cns3xxx_usb_ohci_resources[] = {
  128. [0] = {
  129. .start = CNS3XXX_USB_OHCI_BASE,
  130. .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
  131. .flags = IORESOURCE_MEM,
  132. },
  133. [1] = {
  134. .start = IRQ_CNS3XXX_USB_OHCI,
  135. .flags = IORESOURCE_IRQ,
  136. },
  137. };
  138. static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
  139. static struct platform_device cns3xxx_usb_ohci_device = {
  140. .name = "cns3xxx-ohci",
  141. .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
  142. .resource = cns3xxx_usb_ohci_resources,
  143. .dev = {
  144. .dma_mask = &cns3xxx_usb_ohci_dma_mask,
  145. .coherent_dma_mask = DMA_BIT_MASK(32),
  146. },
  147. };
  148. /*
  149. * Initialization
  150. */
  151. static struct platform_device *cns3420_pdevs[] __initdata = {
  152. &cns3420_nor_pdev,
  153. &cns3xxx_usb_ehci_device,
  154. &cns3xxx_usb_ohci_device,
  155. };
  156. static void __init cns3420_init(void)
  157. {
  158. cns3xxx_l2x0_init();
  159. platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
  160. cns3xxx_ahci_init();
  161. cns3xxx_sdhci_init();
  162. pm_power_off = cns3xxx_power_off;
  163. }
  164. static struct map_desc cns3420_io_desc[] __initdata = {
  165. {
  166. .virtual = CNS3XXX_UART0_BASE_VIRT,
  167. .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
  168. .length = SZ_4K,
  169. .type = MT_DEVICE,
  170. },
  171. };
  172. static void __init cns3420_map_io(void)
  173. {
  174. cns3xxx_map_io();
  175. iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
  176. cns3420_early_serial_setup();
  177. }
  178. MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
  179. .atag_offset = 0x100,
  180. .map_io = cns3420_map_io,
  181. .init_irq = cns3xxx_init_irq,
  182. .timer = &cns3xxx_timer,
  183. .handle_irq = gic_handle_irq,
  184. .init_machine = cns3420_init,
  185. .restart = cns3xxx_restart,
  186. MACHINE_END