ac97c.c 31 KB

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  1. /*
  2. * Driver for Atmel AC97C
  3. *
  4. * Copyright (C) 2005-2009 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/delay.h>
  12. #include <linux/bitmap.h>
  13. #include <linux/device.h>
  14. #include <linux/dmaengine.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/atmel_pdc.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/mutex.h>
  22. #include <linux/gpio.h>
  23. #include <linux/types.h>
  24. #include <linux/io.h>
  25. #include <sound/core.h>
  26. #include <sound/initval.h>
  27. #include <sound/pcm.h>
  28. #include <sound/pcm_params.h>
  29. #include <sound/ac97_codec.h>
  30. #include <sound/atmel-ac97c.h>
  31. #include <sound/memalloc.h>
  32. #include <linux/dw_dmac.h>
  33. #include <mach/cpu.h>
  34. #include <mach/gpio.h>
  35. #ifdef CONFIG_ARCH_AT91
  36. #include <mach/hardware.h>
  37. #endif
  38. #include "ac97c.h"
  39. enum {
  40. DMA_TX_READY = 0,
  41. DMA_RX_READY,
  42. DMA_TX_CHAN_PRESENT,
  43. DMA_RX_CHAN_PRESENT,
  44. };
  45. /* Serialize access to opened variable */
  46. static DEFINE_MUTEX(opened_mutex);
  47. struct atmel_ac97c_dma {
  48. struct dma_chan *rx_chan;
  49. struct dma_chan *tx_chan;
  50. };
  51. struct atmel_ac97c {
  52. struct clk *pclk;
  53. struct platform_device *pdev;
  54. struct atmel_ac97c_dma dma;
  55. struct snd_pcm_substream *playback_substream;
  56. struct snd_pcm_substream *capture_substream;
  57. struct snd_card *card;
  58. struct snd_pcm *pcm;
  59. struct snd_ac97 *ac97;
  60. struct snd_ac97_bus *ac97_bus;
  61. u64 cur_format;
  62. unsigned int cur_rate;
  63. unsigned long flags;
  64. int playback_period, capture_period;
  65. /* Serialize access to opened variable */
  66. spinlock_t lock;
  67. void __iomem *regs;
  68. int irq;
  69. int opened;
  70. int reset_pin;
  71. };
  72. #define get_chip(card) ((struct atmel_ac97c *)(card)->private_data)
  73. #define ac97c_writel(chip, reg, val) \
  74. __raw_writel((val), (chip)->regs + AC97C_##reg)
  75. #define ac97c_readl(chip, reg) \
  76. __raw_readl((chip)->regs + AC97C_##reg)
  77. /* This function is called by the DMA driver. */
  78. static void atmel_ac97c_dma_playback_period_done(void *arg)
  79. {
  80. struct atmel_ac97c *chip = arg;
  81. snd_pcm_period_elapsed(chip->playback_substream);
  82. }
  83. static void atmel_ac97c_dma_capture_period_done(void *arg)
  84. {
  85. struct atmel_ac97c *chip = arg;
  86. snd_pcm_period_elapsed(chip->capture_substream);
  87. }
  88. static int atmel_ac97c_prepare_dma(struct atmel_ac97c *chip,
  89. struct snd_pcm_substream *substream,
  90. enum dma_transfer_direction direction)
  91. {
  92. struct dma_chan *chan;
  93. struct dw_cyclic_desc *cdesc;
  94. struct snd_pcm_runtime *runtime = substream->runtime;
  95. unsigned long buffer_len, period_len;
  96. /*
  97. * We don't do DMA on "complex" transfers, i.e. with
  98. * non-halfword-aligned buffers or lengths.
  99. */
  100. if (runtime->dma_addr & 1 || runtime->buffer_size & 1) {
  101. dev_dbg(&chip->pdev->dev, "too complex transfer\n");
  102. return -EINVAL;
  103. }
  104. if (direction == DMA_MEM_TO_DEV)
  105. chan = chip->dma.tx_chan;
  106. else
  107. chan = chip->dma.rx_chan;
  108. buffer_len = frames_to_bytes(runtime, runtime->buffer_size);
  109. period_len = frames_to_bytes(runtime, runtime->period_size);
  110. cdesc = dw_dma_cyclic_prep(chan, runtime->dma_addr, buffer_len,
  111. period_len, direction);
  112. if (IS_ERR(cdesc)) {
  113. dev_dbg(&chip->pdev->dev, "could not prepare cyclic DMA\n");
  114. return PTR_ERR(cdesc);
  115. }
  116. if (direction == DMA_MEM_TO_DEV) {
  117. cdesc->period_callback = atmel_ac97c_dma_playback_period_done;
  118. set_bit(DMA_TX_READY, &chip->flags);
  119. } else {
  120. cdesc->period_callback = atmel_ac97c_dma_capture_period_done;
  121. set_bit(DMA_RX_READY, &chip->flags);
  122. }
  123. cdesc->period_callback_param = chip;
  124. return 0;
  125. }
  126. static struct snd_pcm_hardware atmel_ac97c_hw = {
  127. .info = (SNDRV_PCM_INFO_MMAP
  128. | SNDRV_PCM_INFO_MMAP_VALID
  129. | SNDRV_PCM_INFO_INTERLEAVED
  130. | SNDRV_PCM_INFO_BLOCK_TRANSFER
  131. | SNDRV_PCM_INFO_JOINT_DUPLEX
  132. | SNDRV_PCM_INFO_RESUME
  133. | SNDRV_PCM_INFO_PAUSE),
  134. .formats = (SNDRV_PCM_FMTBIT_S16_BE
  135. | SNDRV_PCM_FMTBIT_S16_LE),
  136. .rates = (SNDRV_PCM_RATE_CONTINUOUS),
  137. .rate_min = 4000,
  138. .rate_max = 48000,
  139. .channels_min = 1,
  140. .channels_max = 2,
  141. .buffer_bytes_max = 2 * 2 * 64 * 2048,
  142. .period_bytes_min = 4096,
  143. .period_bytes_max = 4096,
  144. .periods_min = 6,
  145. .periods_max = 64,
  146. };
  147. static int atmel_ac97c_playback_open(struct snd_pcm_substream *substream)
  148. {
  149. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  150. struct snd_pcm_runtime *runtime = substream->runtime;
  151. mutex_lock(&opened_mutex);
  152. chip->opened++;
  153. runtime->hw = atmel_ac97c_hw;
  154. if (chip->cur_rate) {
  155. runtime->hw.rate_min = chip->cur_rate;
  156. runtime->hw.rate_max = chip->cur_rate;
  157. }
  158. if (chip->cur_format)
  159. runtime->hw.formats = (1ULL << chip->cur_format);
  160. mutex_unlock(&opened_mutex);
  161. chip->playback_substream = substream;
  162. return 0;
  163. }
  164. static int atmel_ac97c_capture_open(struct snd_pcm_substream *substream)
  165. {
  166. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  167. struct snd_pcm_runtime *runtime = substream->runtime;
  168. mutex_lock(&opened_mutex);
  169. chip->opened++;
  170. runtime->hw = atmel_ac97c_hw;
  171. if (chip->cur_rate) {
  172. runtime->hw.rate_min = chip->cur_rate;
  173. runtime->hw.rate_max = chip->cur_rate;
  174. }
  175. if (chip->cur_format)
  176. runtime->hw.formats = (1ULL << chip->cur_format);
  177. mutex_unlock(&opened_mutex);
  178. chip->capture_substream = substream;
  179. return 0;
  180. }
  181. static int atmel_ac97c_playback_close(struct snd_pcm_substream *substream)
  182. {
  183. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  184. mutex_lock(&opened_mutex);
  185. chip->opened--;
  186. if (!chip->opened) {
  187. chip->cur_rate = 0;
  188. chip->cur_format = 0;
  189. }
  190. mutex_unlock(&opened_mutex);
  191. chip->playback_substream = NULL;
  192. return 0;
  193. }
  194. static int atmel_ac97c_capture_close(struct snd_pcm_substream *substream)
  195. {
  196. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  197. mutex_lock(&opened_mutex);
  198. chip->opened--;
  199. if (!chip->opened) {
  200. chip->cur_rate = 0;
  201. chip->cur_format = 0;
  202. }
  203. mutex_unlock(&opened_mutex);
  204. chip->capture_substream = NULL;
  205. return 0;
  206. }
  207. static int atmel_ac97c_playback_hw_params(struct snd_pcm_substream *substream,
  208. struct snd_pcm_hw_params *hw_params)
  209. {
  210. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  211. int retval;
  212. retval = snd_pcm_lib_malloc_pages(substream,
  213. params_buffer_bytes(hw_params));
  214. if (retval < 0)
  215. return retval;
  216. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  217. if (cpu_is_at32ap7000()) {
  218. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  219. if (retval == 1)
  220. if (test_and_clear_bit(DMA_TX_READY, &chip->flags))
  221. dw_dma_cyclic_free(chip->dma.tx_chan);
  222. }
  223. /* Set restrictions to params. */
  224. mutex_lock(&opened_mutex);
  225. chip->cur_rate = params_rate(hw_params);
  226. chip->cur_format = params_format(hw_params);
  227. mutex_unlock(&opened_mutex);
  228. return retval;
  229. }
  230. static int atmel_ac97c_capture_hw_params(struct snd_pcm_substream *substream,
  231. struct snd_pcm_hw_params *hw_params)
  232. {
  233. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  234. int retval;
  235. retval = snd_pcm_lib_malloc_pages(substream,
  236. params_buffer_bytes(hw_params));
  237. if (retval < 0)
  238. return retval;
  239. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  240. if (cpu_is_at32ap7000()) {
  241. if (retval < 0)
  242. return retval;
  243. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  244. if (retval == 1)
  245. if (test_and_clear_bit(DMA_RX_READY, &chip->flags))
  246. dw_dma_cyclic_free(chip->dma.rx_chan);
  247. }
  248. /* Set restrictions to params. */
  249. mutex_lock(&opened_mutex);
  250. chip->cur_rate = params_rate(hw_params);
  251. chip->cur_format = params_format(hw_params);
  252. mutex_unlock(&opened_mutex);
  253. return retval;
  254. }
  255. static int atmel_ac97c_playback_hw_free(struct snd_pcm_substream *substream)
  256. {
  257. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  258. if (cpu_is_at32ap7000()) {
  259. if (test_and_clear_bit(DMA_TX_READY, &chip->flags))
  260. dw_dma_cyclic_free(chip->dma.tx_chan);
  261. }
  262. return snd_pcm_lib_free_pages(substream);
  263. }
  264. static int atmel_ac97c_capture_hw_free(struct snd_pcm_substream *substream)
  265. {
  266. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  267. if (cpu_is_at32ap7000()) {
  268. if (test_and_clear_bit(DMA_RX_READY, &chip->flags))
  269. dw_dma_cyclic_free(chip->dma.rx_chan);
  270. }
  271. return snd_pcm_lib_free_pages(substream);
  272. }
  273. static int atmel_ac97c_playback_prepare(struct snd_pcm_substream *substream)
  274. {
  275. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  276. struct snd_pcm_runtime *runtime = substream->runtime;
  277. int block_size = frames_to_bytes(runtime, runtime->period_size);
  278. unsigned long word = ac97c_readl(chip, OCA);
  279. int retval;
  280. chip->playback_period = 0;
  281. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  282. /* assign channels to AC97C channel A */
  283. switch (runtime->channels) {
  284. case 1:
  285. word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
  286. break;
  287. case 2:
  288. word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
  289. | AC97C_CH_ASSIGN(PCM_RIGHT, A);
  290. break;
  291. default:
  292. /* TODO: support more than two channels */
  293. return -EINVAL;
  294. }
  295. ac97c_writel(chip, OCA, word);
  296. /* configure sample format and size */
  297. word = ac97c_readl(chip, CAMR);
  298. if (chip->opened <= 1)
  299. word = AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  300. else
  301. word |= AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  302. switch (runtime->format) {
  303. case SNDRV_PCM_FORMAT_S16_LE:
  304. if (cpu_is_at32ap7000())
  305. word |= AC97C_CMR_CEM_LITTLE;
  306. break;
  307. case SNDRV_PCM_FORMAT_S16_BE: /* fall through */
  308. word &= ~(AC97C_CMR_CEM_LITTLE);
  309. break;
  310. default:
  311. word = ac97c_readl(chip, OCA);
  312. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  313. ac97c_writel(chip, OCA, word);
  314. return -EINVAL;
  315. }
  316. /* Enable underrun interrupt on channel A */
  317. word |= AC97C_CSR_UNRUN;
  318. ac97c_writel(chip, CAMR, word);
  319. /* Enable channel A event interrupt */
  320. word = ac97c_readl(chip, IMR);
  321. word |= AC97C_SR_CAEVT;
  322. ac97c_writel(chip, IER, word);
  323. /* set variable rate if needed */
  324. if (runtime->rate != 48000) {
  325. word = ac97c_readl(chip, MR);
  326. word |= AC97C_MR_VRA;
  327. ac97c_writel(chip, MR, word);
  328. } else {
  329. word = ac97c_readl(chip, MR);
  330. word &= ~(AC97C_MR_VRA);
  331. ac97c_writel(chip, MR, word);
  332. }
  333. retval = snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE,
  334. runtime->rate);
  335. if (retval)
  336. dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n",
  337. runtime->rate);
  338. if (cpu_is_at32ap7000()) {
  339. if (!test_bit(DMA_TX_READY, &chip->flags))
  340. retval = atmel_ac97c_prepare_dma(chip, substream,
  341. DMA_MEM_TO_DEV);
  342. } else {
  343. /* Initialize and start the PDC */
  344. writel(runtime->dma_addr, chip->regs + ATMEL_PDC_TPR);
  345. writel(block_size / 2, chip->regs + ATMEL_PDC_TCR);
  346. writel(runtime->dma_addr + block_size,
  347. chip->regs + ATMEL_PDC_TNPR);
  348. writel(block_size / 2, chip->regs + ATMEL_PDC_TNCR);
  349. }
  350. return retval;
  351. }
  352. static int atmel_ac97c_capture_prepare(struct snd_pcm_substream *substream)
  353. {
  354. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  355. struct snd_pcm_runtime *runtime = substream->runtime;
  356. int block_size = frames_to_bytes(runtime, runtime->period_size);
  357. unsigned long word = ac97c_readl(chip, ICA);
  358. int retval;
  359. chip->capture_period = 0;
  360. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  361. /* assign channels to AC97C channel A */
  362. switch (runtime->channels) {
  363. case 1:
  364. word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
  365. break;
  366. case 2:
  367. word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
  368. | AC97C_CH_ASSIGN(PCM_RIGHT, A);
  369. break;
  370. default:
  371. /* TODO: support more than two channels */
  372. return -EINVAL;
  373. }
  374. ac97c_writel(chip, ICA, word);
  375. /* configure sample format and size */
  376. word = ac97c_readl(chip, CAMR);
  377. if (chip->opened <= 1)
  378. word = AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  379. else
  380. word |= AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  381. switch (runtime->format) {
  382. case SNDRV_PCM_FORMAT_S16_LE:
  383. if (cpu_is_at32ap7000())
  384. word |= AC97C_CMR_CEM_LITTLE;
  385. break;
  386. case SNDRV_PCM_FORMAT_S16_BE: /* fall through */
  387. word &= ~(AC97C_CMR_CEM_LITTLE);
  388. break;
  389. default:
  390. word = ac97c_readl(chip, ICA);
  391. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  392. ac97c_writel(chip, ICA, word);
  393. return -EINVAL;
  394. }
  395. /* Enable overrun interrupt on channel A */
  396. word |= AC97C_CSR_OVRUN;
  397. ac97c_writel(chip, CAMR, word);
  398. /* Enable channel A event interrupt */
  399. word = ac97c_readl(chip, IMR);
  400. word |= AC97C_SR_CAEVT;
  401. ac97c_writel(chip, IER, word);
  402. /* set variable rate if needed */
  403. if (runtime->rate != 48000) {
  404. word = ac97c_readl(chip, MR);
  405. word |= AC97C_MR_VRA;
  406. ac97c_writel(chip, MR, word);
  407. } else {
  408. word = ac97c_readl(chip, MR);
  409. word &= ~(AC97C_MR_VRA);
  410. ac97c_writel(chip, MR, word);
  411. }
  412. retval = snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE,
  413. runtime->rate);
  414. if (retval)
  415. dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n",
  416. runtime->rate);
  417. if (cpu_is_at32ap7000()) {
  418. if (!test_bit(DMA_RX_READY, &chip->flags))
  419. retval = atmel_ac97c_prepare_dma(chip, substream,
  420. DMA_DEV_TO_MEM);
  421. } else {
  422. /* Initialize and start the PDC */
  423. writel(runtime->dma_addr, chip->regs + ATMEL_PDC_RPR);
  424. writel(block_size / 2, chip->regs + ATMEL_PDC_RCR);
  425. writel(runtime->dma_addr + block_size,
  426. chip->regs + ATMEL_PDC_RNPR);
  427. writel(block_size / 2, chip->regs + ATMEL_PDC_RNCR);
  428. }
  429. return retval;
  430. }
  431. static int
  432. atmel_ac97c_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  433. {
  434. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  435. unsigned long camr, ptcr = 0;
  436. int retval = 0;
  437. camr = ac97c_readl(chip, CAMR);
  438. switch (cmd) {
  439. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */
  440. case SNDRV_PCM_TRIGGER_RESUME: /* fall through */
  441. case SNDRV_PCM_TRIGGER_START:
  442. if (cpu_is_at32ap7000()) {
  443. retval = dw_dma_cyclic_start(chip->dma.tx_chan);
  444. if (retval)
  445. goto out;
  446. } else {
  447. ptcr = ATMEL_PDC_TXTEN;
  448. }
  449. camr |= AC97C_CMR_CENA | AC97C_CSR_ENDTX;
  450. break;
  451. case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */
  452. case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */
  453. case SNDRV_PCM_TRIGGER_STOP:
  454. if (cpu_is_at32ap7000())
  455. dw_dma_cyclic_stop(chip->dma.tx_chan);
  456. else
  457. ptcr |= ATMEL_PDC_TXTDIS;
  458. if (chip->opened <= 1)
  459. camr &= ~AC97C_CMR_CENA;
  460. break;
  461. default:
  462. retval = -EINVAL;
  463. goto out;
  464. }
  465. ac97c_writel(chip, CAMR, camr);
  466. if (!cpu_is_at32ap7000())
  467. writel(ptcr, chip->regs + ATMEL_PDC_PTCR);
  468. out:
  469. return retval;
  470. }
  471. static int
  472. atmel_ac97c_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  473. {
  474. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  475. unsigned long camr, ptcr = 0;
  476. int retval = 0;
  477. camr = ac97c_readl(chip, CAMR);
  478. ptcr = readl(chip->regs + ATMEL_PDC_PTSR);
  479. switch (cmd) {
  480. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */
  481. case SNDRV_PCM_TRIGGER_RESUME: /* fall through */
  482. case SNDRV_PCM_TRIGGER_START:
  483. if (cpu_is_at32ap7000()) {
  484. retval = dw_dma_cyclic_start(chip->dma.rx_chan);
  485. if (retval)
  486. goto out;
  487. } else {
  488. ptcr = ATMEL_PDC_RXTEN;
  489. }
  490. camr |= AC97C_CMR_CENA | AC97C_CSR_ENDRX;
  491. break;
  492. case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */
  493. case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */
  494. case SNDRV_PCM_TRIGGER_STOP:
  495. if (cpu_is_at32ap7000())
  496. dw_dma_cyclic_stop(chip->dma.rx_chan);
  497. else
  498. ptcr |= (ATMEL_PDC_RXTDIS);
  499. if (chip->opened <= 1)
  500. camr &= ~AC97C_CMR_CENA;
  501. break;
  502. default:
  503. retval = -EINVAL;
  504. break;
  505. }
  506. ac97c_writel(chip, CAMR, camr);
  507. if (!cpu_is_at32ap7000())
  508. writel(ptcr, chip->regs + ATMEL_PDC_PTCR);
  509. out:
  510. return retval;
  511. }
  512. static snd_pcm_uframes_t
  513. atmel_ac97c_playback_pointer(struct snd_pcm_substream *substream)
  514. {
  515. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  516. struct snd_pcm_runtime *runtime = substream->runtime;
  517. snd_pcm_uframes_t frames;
  518. unsigned long bytes;
  519. if (cpu_is_at32ap7000())
  520. bytes = dw_dma_get_src_addr(chip->dma.tx_chan);
  521. else
  522. bytes = readl(chip->regs + ATMEL_PDC_TPR);
  523. bytes -= runtime->dma_addr;
  524. frames = bytes_to_frames(runtime, bytes);
  525. if (frames >= runtime->buffer_size)
  526. frames -= runtime->buffer_size;
  527. return frames;
  528. }
  529. static snd_pcm_uframes_t
  530. atmel_ac97c_capture_pointer(struct snd_pcm_substream *substream)
  531. {
  532. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  533. struct snd_pcm_runtime *runtime = substream->runtime;
  534. snd_pcm_uframes_t frames;
  535. unsigned long bytes;
  536. if (cpu_is_at32ap7000())
  537. bytes = dw_dma_get_dst_addr(chip->dma.rx_chan);
  538. else
  539. bytes = readl(chip->regs + ATMEL_PDC_RPR);
  540. bytes -= runtime->dma_addr;
  541. frames = bytes_to_frames(runtime, bytes);
  542. if (frames >= runtime->buffer_size)
  543. frames -= runtime->buffer_size;
  544. return frames;
  545. }
  546. static struct snd_pcm_ops atmel_ac97_playback_ops = {
  547. .open = atmel_ac97c_playback_open,
  548. .close = atmel_ac97c_playback_close,
  549. .ioctl = snd_pcm_lib_ioctl,
  550. .hw_params = atmel_ac97c_playback_hw_params,
  551. .hw_free = atmel_ac97c_playback_hw_free,
  552. .prepare = atmel_ac97c_playback_prepare,
  553. .trigger = atmel_ac97c_playback_trigger,
  554. .pointer = atmel_ac97c_playback_pointer,
  555. };
  556. static struct snd_pcm_ops atmel_ac97_capture_ops = {
  557. .open = atmel_ac97c_capture_open,
  558. .close = atmel_ac97c_capture_close,
  559. .ioctl = snd_pcm_lib_ioctl,
  560. .hw_params = atmel_ac97c_capture_hw_params,
  561. .hw_free = atmel_ac97c_capture_hw_free,
  562. .prepare = atmel_ac97c_capture_prepare,
  563. .trigger = atmel_ac97c_capture_trigger,
  564. .pointer = atmel_ac97c_capture_pointer,
  565. };
  566. static irqreturn_t atmel_ac97c_interrupt(int irq, void *dev)
  567. {
  568. struct atmel_ac97c *chip = (struct atmel_ac97c *)dev;
  569. irqreturn_t retval = IRQ_NONE;
  570. u32 sr = ac97c_readl(chip, SR);
  571. u32 casr = ac97c_readl(chip, CASR);
  572. u32 cosr = ac97c_readl(chip, COSR);
  573. u32 camr = ac97c_readl(chip, CAMR);
  574. if (sr & AC97C_SR_CAEVT) {
  575. struct snd_pcm_runtime *runtime;
  576. int offset, next_period, block_size;
  577. dev_dbg(&chip->pdev->dev, "channel A event%s%s%s%s%s%s\n",
  578. casr & AC97C_CSR_OVRUN ? " OVRUN" : "",
  579. casr & AC97C_CSR_RXRDY ? " RXRDY" : "",
  580. casr & AC97C_CSR_UNRUN ? " UNRUN" : "",
  581. casr & AC97C_CSR_TXEMPTY ? " TXEMPTY" : "",
  582. casr & AC97C_CSR_TXRDY ? " TXRDY" : "",
  583. !casr ? " NONE" : "");
  584. if (!cpu_is_at32ap7000()) {
  585. if ((casr & camr) & AC97C_CSR_ENDTX) {
  586. runtime = chip->playback_substream->runtime;
  587. block_size = frames_to_bytes(runtime,
  588. runtime->period_size);
  589. chip->playback_period++;
  590. if (chip->playback_period == runtime->periods)
  591. chip->playback_period = 0;
  592. next_period = chip->playback_period + 1;
  593. if (next_period == runtime->periods)
  594. next_period = 0;
  595. offset = block_size * next_period;
  596. writel(runtime->dma_addr + offset,
  597. chip->regs + ATMEL_PDC_TNPR);
  598. writel(block_size / 2,
  599. chip->regs + ATMEL_PDC_TNCR);
  600. snd_pcm_period_elapsed(
  601. chip->playback_substream);
  602. }
  603. if ((casr & camr) & AC97C_CSR_ENDRX) {
  604. runtime = chip->capture_substream->runtime;
  605. block_size = frames_to_bytes(runtime,
  606. runtime->period_size);
  607. chip->capture_period++;
  608. if (chip->capture_period == runtime->periods)
  609. chip->capture_period = 0;
  610. next_period = chip->capture_period + 1;
  611. if (next_period == runtime->periods)
  612. next_period = 0;
  613. offset = block_size * next_period;
  614. writel(runtime->dma_addr + offset,
  615. chip->regs + ATMEL_PDC_RNPR);
  616. writel(block_size / 2,
  617. chip->regs + ATMEL_PDC_RNCR);
  618. snd_pcm_period_elapsed(chip->capture_substream);
  619. }
  620. }
  621. retval = IRQ_HANDLED;
  622. }
  623. if (sr & AC97C_SR_COEVT) {
  624. dev_info(&chip->pdev->dev, "codec channel event%s%s%s%s%s\n",
  625. cosr & AC97C_CSR_OVRUN ? " OVRUN" : "",
  626. cosr & AC97C_CSR_RXRDY ? " RXRDY" : "",
  627. cosr & AC97C_CSR_TXEMPTY ? " TXEMPTY" : "",
  628. cosr & AC97C_CSR_TXRDY ? " TXRDY" : "",
  629. !cosr ? " NONE" : "");
  630. retval = IRQ_HANDLED;
  631. }
  632. if (retval == IRQ_NONE) {
  633. dev_err(&chip->pdev->dev, "spurious interrupt sr 0x%08x "
  634. "casr 0x%08x cosr 0x%08x\n", sr, casr, cosr);
  635. }
  636. return retval;
  637. }
  638. static struct ac97_pcm at91_ac97_pcm_defs[] __devinitdata = {
  639. /* Playback */
  640. {
  641. .exclusive = 1,
  642. .r = { {
  643. .slots = ((1 << AC97_SLOT_PCM_LEFT)
  644. | (1 << AC97_SLOT_PCM_RIGHT)),
  645. } },
  646. },
  647. /* PCM in */
  648. {
  649. .stream = 1,
  650. .exclusive = 1,
  651. .r = { {
  652. .slots = ((1 << AC97_SLOT_PCM_LEFT)
  653. | (1 << AC97_SLOT_PCM_RIGHT)),
  654. } }
  655. },
  656. /* Mic in */
  657. {
  658. .stream = 1,
  659. .exclusive = 1,
  660. .r = { {
  661. .slots = (1<<AC97_SLOT_MIC),
  662. } }
  663. },
  664. };
  665. static int __devinit atmel_ac97c_pcm_new(struct atmel_ac97c *chip)
  666. {
  667. struct snd_pcm *pcm;
  668. struct snd_pcm_hardware hw = atmel_ac97c_hw;
  669. int capture, playback, retval, err;
  670. capture = test_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  671. playback = test_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  672. if (!cpu_is_at32ap7000()) {
  673. err = snd_ac97_pcm_assign(chip->ac97_bus,
  674. ARRAY_SIZE(at91_ac97_pcm_defs),
  675. at91_ac97_pcm_defs);
  676. if (err)
  677. return err;
  678. }
  679. retval = snd_pcm_new(chip->card, chip->card->shortname,
  680. chip->pdev->id, playback, capture, &pcm);
  681. if (retval)
  682. return retval;
  683. if (capture)
  684. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  685. &atmel_ac97_capture_ops);
  686. if (playback)
  687. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  688. &atmel_ac97_playback_ops);
  689. retval = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  690. &chip->pdev->dev, hw.periods_min * hw.period_bytes_min,
  691. hw.buffer_bytes_max);
  692. if (retval)
  693. return retval;
  694. pcm->private_data = chip;
  695. pcm->info_flags = 0;
  696. strcpy(pcm->name, chip->card->shortname);
  697. chip->pcm = pcm;
  698. return 0;
  699. }
  700. static int atmel_ac97c_mixer_new(struct atmel_ac97c *chip)
  701. {
  702. struct snd_ac97_template template;
  703. memset(&template, 0, sizeof(template));
  704. template.private_data = chip;
  705. return snd_ac97_mixer(chip->ac97_bus, &template, &chip->ac97);
  706. }
  707. static void atmel_ac97c_write(struct snd_ac97 *ac97, unsigned short reg,
  708. unsigned short val)
  709. {
  710. struct atmel_ac97c *chip = get_chip(ac97);
  711. unsigned long word;
  712. int timeout = 40;
  713. word = (reg & 0x7f) << 16 | val;
  714. do {
  715. if (ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) {
  716. ac97c_writel(chip, COTHR, word);
  717. return;
  718. }
  719. udelay(1);
  720. } while (--timeout);
  721. dev_dbg(&chip->pdev->dev, "codec write timeout\n");
  722. }
  723. static unsigned short atmel_ac97c_read(struct snd_ac97 *ac97,
  724. unsigned short reg)
  725. {
  726. struct atmel_ac97c *chip = get_chip(ac97);
  727. unsigned long word;
  728. int timeout = 40;
  729. int write = 10;
  730. word = (0x80 | (reg & 0x7f)) << 16;
  731. if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0)
  732. ac97c_readl(chip, CORHR);
  733. retry_write:
  734. timeout = 40;
  735. do {
  736. if ((ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) != 0) {
  737. ac97c_writel(chip, COTHR, word);
  738. goto read_reg;
  739. }
  740. udelay(10);
  741. } while (--timeout);
  742. if (!--write)
  743. goto timed_out;
  744. goto retry_write;
  745. read_reg:
  746. do {
  747. if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0) {
  748. unsigned short val = ac97c_readl(chip, CORHR);
  749. return val;
  750. }
  751. udelay(10);
  752. } while (--timeout);
  753. if (!--write)
  754. goto timed_out;
  755. goto retry_write;
  756. timed_out:
  757. dev_dbg(&chip->pdev->dev, "codec read timeout\n");
  758. return 0xffff;
  759. }
  760. static bool filter(struct dma_chan *chan, void *slave)
  761. {
  762. struct dw_dma_slave *dws = slave;
  763. if (dws->dma_dev == chan->device->dev) {
  764. chan->private = dws;
  765. return true;
  766. } else
  767. return false;
  768. }
  769. static void atmel_ac97c_reset(struct atmel_ac97c *chip)
  770. {
  771. ac97c_writel(chip, MR, 0);
  772. ac97c_writel(chip, MR, AC97C_MR_ENA);
  773. ac97c_writel(chip, CAMR, 0);
  774. ac97c_writel(chip, COMR, 0);
  775. if (gpio_is_valid(chip->reset_pin)) {
  776. gpio_set_value(chip->reset_pin, 0);
  777. /* AC97 v2.2 specifications says minimum 1 us. */
  778. udelay(2);
  779. gpio_set_value(chip->reset_pin, 1);
  780. } else {
  781. ac97c_writel(chip, MR, AC97C_MR_WRST | AC97C_MR_ENA);
  782. udelay(2);
  783. ac97c_writel(chip, MR, AC97C_MR_ENA);
  784. }
  785. }
  786. static int __devinit atmel_ac97c_probe(struct platform_device *pdev)
  787. {
  788. struct snd_card *card;
  789. struct atmel_ac97c *chip;
  790. struct resource *regs;
  791. struct ac97c_platform_data *pdata;
  792. struct clk *pclk;
  793. static struct snd_ac97_bus_ops ops = {
  794. .write = atmel_ac97c_write,
  795. .read = atmel_ac97c_read,
  796. };
  797. int retval;
  798. int irq;
  799. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  800. if (!regs) {
  801. dev_dbg(&pdev->dev, "no memory resource\n");
  802. return -ENXIO;
  803. }
  804. pdata = pdev->dev.platform_data;
  805. if (!pdata) {
  806. dev_dbg(&pdev->dev, "no platform data\n");
  807. return -ENXIO;
  808. }
  809. irq = platform_get_irq(pdev, 0);
  810. if (irq < 0) {
  811. dev_dbg(&pdev->dev, "could not get irq\n");
  812. return -ENXIO;
  813. }
  814. if (cpu_is_at32ap7000()) {
  815. pclk = clk_get(&pdev->dev, "pclk");
  816. } else {
  817. pclk = clk_get(&pdev->dev, "ac97_clk");
  818. }
  819. if (IS_ERR(pclk)) {
  820. dev_dbg(&pdev->dev, "no peripheral clock\n");
  821. return PTR_ERR(pclk);
  822. }
  823. clk_enable(pclk);
  824. retval = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  825. THIS_MODULE, sizeof(struct atmel_ac97c), &card);
  826. if (retval) {
  827. dev_dbg(&pdev->dev, "could not create sound card device\n");
  828. goto err_snd_card_new;
  829. }
  830. chip = get_chip(card);
  831. retval = request_irq(irq, atmel_ac97c_interrupt, 0, "AC97C", chip);
  832. if (retval) {
  833. dev_dbg(&pdev->dev, "unable to request irq %d\n", irq);
  834. goto err_request_irq;
  835. }
  836. chip->irq = irq;
  837. spin_lock_init(&chip->lock);
  838. strcpy(card->driver, "Atmel AC97C");
  839. strcpy(card->shortname, "Atmel AC97C");
  840. sprintf(card->longname, "Atmel AC97 controller");
  841. chip->card = card;
  842. chip->pclk = pclk;
  843. chip->pdev = pdev;
  844. chip->regs = ioremap(regs->start, resource_size(regs));
  845. if (!chip->regs) {
  846. dev_dbg(&pdev->dev, "could not remap register memory\n");
  847. goto err_ioremap;
  848. }
  849. if (gpio_is_valid(pdata->reset_pin)) {
  850. if (gpio_request(pdata->reset_pin, "reset_pin")) {
  851. dev_dbg(&pdev->dev, "reset pin not available\n");
  852. chip->reset_pin = -ENODEV;
  853. } else {
  854. gpio_direction_output(pdata->reset_pin, 1);
  855. chip->reset_pin = pdata->reset_pin;
  856. }
  857. }
  858. snd_card_set_dev(card, &pdev->dev);
  859. atmel_ac97c_reset(chip);
  860. /* Enable overrun interrupt from codec channel */
  861. ac97c_writel(chip, COMR, AC97C_CSR_OVRUN);
  862. ac97c_writel(chip, IER, ac97c_readl(chip, IMR) | AC97C_SR_COEVT);
  863. retval = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
  864. if (retval) {
  865. dev_dbg(&pdev->dev, "could not register on ac97 bus\n");
  866. goto err_ac97_bus;
  867. }
  868. retval = atmel_ac97c_mixer_new(chip);
  869. if (retval) {
  870. dev_dbg(&pdev->dev, "could not register ac97 mixer\n");
  871. goto err_ac97_bus;
  872. }
  873. if (cpu_is_at32ap7000()) {
  874. if (pdata->rx_dws.dma_dev) {
  875. dma_cap_mask_t mask;
  876. dma_cap_zero(mask);
  877. dma_cap_set(DMA_SLAVE, mask);
  878. chip->dma.rx_chan = dma_request_channel(mask, filter,
  879. &pdata->rx_dws);
  880. if (chip->dma.rx_chan) {
  881. struct dma_slave_config dma_conf = {
  882. .src_addr = regs->start + AC97C_CARHR +
  883. 2,
  884. .src_addr_width =
  885. DMA_SLAVE_BUSWIDTH_2_BYTES,
  886. .src_maxburst = 1,
  887. .dst_maxburst = 1,
  888. .direction = DMA_DEV_TO_MEM,
  889. .device_fc = false,
  890. };
  891. dmaengine_slave_config(chip->dma.rx_chan,
  892. &dma_conf);
  893. }
  894. dev_info(&chip->pdev->dev, "using %s for DMA RX\n",
  895. dev_name(&chip->dma.rx_chan->dev->device));
  896. set_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  897. }
  898. if (pdata->tx_dws.dma_dev) {
  899. dma_cap_mask_t mask;
  900. dma_cap_zero(mask);
  901. dma_cap_set(DMA_SLAVE, mask);
  902. chip->dma.tx_chan = dma_request_channel(mask, filter,
  903. &pdata->tx_dws);
  904. if (chip->dma.tx_chan) {
  905. struct dma_slave_config dma_conf = {
  906. .dst_addr = regs->start + AC97C_CATHR +
  907. 2,
  908. .dst_addr_width =
  909. DMA_SLAVE_BUSWIDTH_2_BYTES,
  910. .src_maxburst = 1,
  911. .dst_maxburst = 1,
  912. .direction = DMA_MEM_TO_DEV,
  913. .device_fc = false,
  914. };
  915. dmaengine_slave_config(chip->dma.tx_chan,
  916. &dma_conf);
  917. }
  918. dev_info(&chip->pdev->dev, "using %s for DMA TX\n",
  919. dev_name(&chip->dma.tx_chan->dev->device));
  920. set_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  921. }
  922. if (!test_bit(DMA_RX_CHAN_PRESENT, &chip->flags) &&
  923. !test_bit(DMA_TX_CHAN_PRESENT, &chip->flags)) {
  924. dev_dbg(&pdev->dev, "DMA not available\n");
  925. retval = -ENODEV;
  926. goto err_dma;
  927. }
  928. } else {
  929. /* Just pretend that we have DMA channel(for at91 i is actually
  930. * the PDC) */
  931. set_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  932. set_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  933. }
  934. retval = atmel_ac97c_pcm_new(chip);
  935. if (retval) {
  936. dev_dbg(&pdev->dev, "could not register ac97 pcm device\n");
  937. goto err_dma;
  938. }
  939. retval = snd_card_register(card);
  940. if (retval) {
  941. dev_dbg(&pdev->dev, "could not register sound card\n");
  942. goto err_dma;
  943. }
  944. platform_set_drvdata(pdev, card);
  945. dev_info(&pdev->dev, "Atmel AC97 controller at 0x%p, irq = %d\n",
  946. chip->regs, irq);
  947. return 0;
  948. err_dma:
  949. if (cpu_is_at32ap7000()) {
  950. if (test_bit(DMA_RX_CHAN_PRESENT, &chip->flags))
  951. dma_release_channel(chip->dma.rx_chan);
  952. if (test_bit(DMA_TX_CHAN_PRESENT, &chip->flags))
  953. dma_release_channel(chip->dma.tx_chan);
  954. clear_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  955. clear_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  956. chip->dma.rx_chan = NULL;
  957. chip->dma.tx_chan = NULL;
  958. }
  959. err_ac97_bus:
  960. snd_card_set_dev(card, NULL);
  961. if (gpio_is_valid(chip->reset_pin))
  962. gpio_free(chip->reset_pin);
  963. iounmap(chip->regs);
  964. err_ioremap:
  965. free_irq(irq, chip);
  966. err_request_irq:
  967. snd_card_free(card);
  968. err_snd_card_new:
  969. clk_disable(pclk);
  970. clk_put(pclk);
  971. return retval;
  972. }
  973. #ifdef CONFIG_PM
  974. static int atmel_ac97c_suspend(struct platform_device *pdev, pm_message_t msg)
  975. {
  976. struct snd_card *card = platform_get_drvdata(pdev);
  977. struct atmel_ac97c *chip = card->private_data;
  978. if (cpu_is_at32ap7000()) {
  979. if (test_bit(DMA_RX_READY, &chip->flags))
  980. dw_dma_cyclic_stop(chip->dma.rx_chan);
  981. if (test_bit(DMA_TX_READY, &chip->flags))
  982. dw_dma_cyclic_stop(chip->dma.tx_chan);
  983. }
  984. clk_disable(chip->pclk);
  985. return 0;
  986. }
  987. static int atmel_ac97c_resume(struct platform_device *pdev)
  988. {
  989. struct snd_card *card = platform_get_drvdata(pdev);
  990. struct atmel_ac97c *chip = card->private_data;
  991. clk_enable(chip->pclk);
  992. if (cpu_is_at32ap7000()) {
  993. if (test_bit(DMA_RX_READY, &chip->flags))
  994. dw_dma_cyclic_start(chip->dma.rx_chan);
  995. if (test_bit(DMA_TX_READY, &chip->flags))
  996. dw_dma_cyclic_start(chip->dma.tx_chan);
  997. }
  998. return 0;
  999. }
  1000. #else
  1001. #define atmel_ac97c_suspend NULL
  1002. #define atmel_ac97c_resume NULL
  1003. #endif
  1004. static int __devexit atmel_ac97c_remove(struct platform_device *pdev)
  1005. {
  1006. struct snd_card *card = platform_get_drvdata(pdev);
  1007. struct atmel_ac97c *chip = get_chip(card);
  1008. if (gpio_is_valid(chip->reset_pin))
  1009. gpio_free(chip->reset_pin);
  1010. ac97c_writel(chip, CAMR, 0);
  1011. ac97c_writel(chip, COMR, 0);
  1012. ac97c_writel(chip, MR, 0);
  1013. clk_disable(chip->pclk);
  1014. clk_put(chip->pclk);
  1015. iounmap(chip->regs);
  1016. free_irq(chip->irq, chip);
  1017. if (cpu_is_at32ap7000()) {
  1018. if (test_bit(DMA_RX_CHAN_PRESENT, &chip->flags))
  1019. dma_release_channel(chip->dma.rx_chan);
  1020. if (test_bit(DMA_TX_CHAN_PRESENT, &chip->flags))
  1021. dma_release_channel(chip->dma.tx_chan);
  1022. clear_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  1023. clear_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  1024. chip->dma.rx_chan = NULL;
  1025. chip->dma.tx_chan = NULL;
  1026. }
  1027. snd_card_set_dev(card, NULL);
  1028. snd_card_free(card);
  1029. platform_set_drvdata(pdev, NULL);
  1030. return 0;
  1031. }
  1032. static struct platform_driver atmel_ac97c_driver = {
  1033. .remove = __devexit_p(atmel_ac97c_remove),
  1034. .driver = {
  1035. .name = "atmel_ac97c",
  1036. },
  1037. .suspend = atmel_ac97c_suspend,
  1038. .resume = atmel_ac97c_resume,
  1039. };
  1040. static int __init atmel_ac97c_init(void)
  1041. {
  1042. return platform_driver_probe(&atmel_ac97c_driver,
  1043. atmel_ac97c_probe);
  1044. }
  1045. module_init(atmel_ac97c_init);
  1046. static void __exit atmel_ac97c_exit(void)
  1047. {
  1048. platform_driver_unregister(&atmel_ac97c_driver);
  1049. }
  1050. module_exit(atmel_ac97c_exit);
  1051. MODULE_LICENSE("GPL");
  1052. MODULE_DESCRIPTION("Driver for Atmel AC97 controller");
  1053. MODULE_AUTHOR("Hans-Christian Egtvedt <egtvedt@samfundet.no>");