s3c-i2s-v2.h 3.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107
  1. /* sound/soc/samsung/s3c-i2s-v2.h
  2. *
  3. * ALSA Soc Audio Layer - S3C_I2SV2 I2S driver
  4. *
  5. * Copyright (c) 2007 Simtec Electronics
  6. * http://armlinux.simtec.co.uk/
  7. * Ben Dooks <ben@simtec.co.uk>
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. /* This code is the core support for the I2S block found in a number of
  15. * Samsung SoC devices which is unofficially named I2S-V2. Currently the
  16. * S3C2412 and the S3C64XX series use this block to provide 1 or 2 I2S
  17. * channels via configurable GPIO.
  18. */
  19. #ifndef __SND_SOC_S3C24XX_S3C_I2SV2_I2S_H
  20. #define __SND_SOC_S3C24XX_S3C_I2SV2_I2S_H __FILE__
  21. #define S3C_I2SV2_DIV_BCLK (1)
  22. #define S3C_I2SV2_DIV_RCLK (2)
  23. #define S3C_I2SV2_DIV_PRESCALER (3)
  24. #define S3C_I2SV2_CLKSRC_PCLK 0
  25. #define S3C_I2SV2_CLKSRC_AUDIOBUS 1
  26. #define S3C_I2SV2_CLKSRC_CDCLK 2
  27. /* Set this flag for I2S controllers that have the bit IISMOD[12]
  28. * bridge/break RCLK signal and external Xi2sCDCLK pin.
  29. */
  30. #define S3C_FEATURE_CDCLKCON (1 << 0)
  31. /**
  32. * struct s3c_i2sv2_info - S3C I2S-V2 information
  33. * @dev: The parent device passed to use from the probe.
  34. * @regs: The pointer to the device registe block.
  35. * @feature: Set of bit-flags indicating features of the controller.
  36. * @master: True if the I2S core is the I2S bit clock master.
  37. * @dma_playback: DMA information for playback channel.
  38. * @dma_capture: DMA information for capture channel.
  39. * @suspend_iismod: PM save for the IISMOD register.
  40. * @suspend_iiscon: PM save for the IISCON register.
  41. * @suspend_iispsr: PM save for the IISPSR register.
  42. *
  43. * This is the private codec state for the hardware associated with an
  44. * I2S channel such as the register mappings and clock sources.
  45. */
  46. struct s3c_i2sv2_info {
  47. struct device *dev;
  48. void __iomem *regs;
  49. u32 feature;
  50. struct clk *iis_pclk;
  51. struct clk *iis_cclk;
  52. unsigned char master;
  53. struct s3c_dma_params *dma_playback;
  54. struct s3c_dma_params *dma_capture;
  55. u32 suspend_iismod;
  56. u32 suspend_iiscon;
  57. u32 suspend_iispsr;
  58. unsigned long base;
  59. };
  60. extern struct clk *s3c_i2sv2_get_clock(struct snd_soc_dai *cpu_dai);
  61. struct s3c_i2sv2_rate_calc {
  62. unsigned int clk_div; /* for prescaler */
  63. unsigned int fs_div; /* for root frame clock */
  64. };
  65. extern int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
  66. unsigned int *fstab,
  67. unsigned int rate, struct clk *clk);
  68. /**
  69. * s3c_i2sv2_probe - probe for i2s device helper
  70. * @dai: The ASoC DAI structure supplied to the original probe.
  71. * @i2s: Our local i2s structure to fill in.
  72. * @base: The base address for the registers.
  73. */
  74. extern int s3c_i2sv2_probe(struct snd_soc_dai *dai,
  75. struct s3c_i2sv2_info *i2s,
  76. unsigned long base);
  77. /**
  78. * s3c_i2sv2_register_dai - register dai with soc core
  79. * @dev: DAI device
  80. * @id: DAI ID
  81. * @drv: The driver structure to register
  82. *
  83. * Fill in any missing fields and then register the given dai with the
  84. * soc core.
  85. */
  86. extern int s3c_i2sv2_register_dai(struct device *dev, int id,
  87. struct snd_soc_dai_driver *drv);
  88. #endif /* __SND_SOC_S3C24XX_S3C_I2SV2_I2S_H */