idma.c 9.9 KB

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  1. /*
  2. * sound/soc/samsung/idma.c
  3. *
  4. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * I2S0's Internal DMA driver
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. #include <linux/interrupt.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/slab.h>
  18. #include <linux/module.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include "i2s.h"
  23. #include "idma.h"
  24. #include "dma.h"
  25. #include "i2s-regs.h"
  26. #define ST_RUNNING (1<<0)
  27. #define ST_OPENED (1<<1)
  28. static const struct snd_pcm_hardware idma_hardware = {
  29. .info = SNDRV_PCM_INFO_INTERLEAVED |
  30. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  31. SNDRV_PCM_INFO_MMAP |
  32. SNDRV_PCM_INFO_MMAP_VALID |
  33. SNDRV_PCM_INFO_PAUSE |
  34. SNDRV_PCM_INFO_RESUME,
  35. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  36. SNDRV_PCM_FMTBIT_U16_LE |
  37. SNDRV_PCM_FMTBIT_S24_LE |
  38. SNDRV_PCM_FMTBIT_U24_LE |
  39. SNDRV_PCM_FMTBIT_U8 |
  40. SNDRV_PCM_FMTBIT_S8,
  41. .channels_min = 2,
  42. .channels_max = 2,
  43. .buffer_bytes_max = MAX_IDMA_BUFFER,
  44. .period_bytes_min = 128,
  45. .period_bytes_max = MAX_IDMA_PERIOD,
  46. .periods_min = 1,
  47. .periods_max = 2,
  48. };
  49. struct idma_ctrl {
  50. spinlock_t lock;
  51. int state;
  52. dma_addr_t start;
  53. dma_addr_t pos;
  54. dma_addr_t end;
  55. dma_addr_t period;
  56. dma_addr_t periodsz;
  57. void *token;
  58. void (*cb)(void *dt, int bytes_xfer);
  59. };
  60. static struct idma_info {
  61. spinlock_t lock;
  62. void __iomem *regs;
  63. dma_addr_t lp_tx_addr;
  64. } idma;
  65. static void idma_getpos(dma_addr_t *src)
  66. {
  67. *src = idma.lp_tx_addr +
  68. (readl(idma.regs + I2STRNCNT) & 0xffffff) * 4;
  69. }
  70. static int idma_enqueue(struct snd_pcm_substream *substream)
  71. {
  72. struct snd_pcm_runtime *runtime = substream->runtime;
  73. struct idma_ctrl *prtd = substream->runtime->private_data;
  74. u32 val;
  75. spin_lock(&prtd->lock);
  76. prtd->token = (void *) substream;
  77. spin_unlock(&prtd->lock);
  78. /* Internal DMA Level0 Interrupt Address */
  79. val = idma.lp_tx_addr + prtd->periodsz;
  80. writel(val, idma.regs + I2SLVL0ADDR);
  81. /* Start address0 of I2S internal DMA operation. */
  82. val = idma.lp_tx_addr;
  83. writel(val, idma.regs + I2SSTR0);
  84. /*
  85. * Transfer block size for I2S internal DMA.
  86. * Should decide transfer size before start dma operation
  87. */
  88. val = readl(idma.regs + I2SSIZE);
  89. val &= ~(I2SSIZE_TRNMSK << I2SSIZE_SHIFT);
  90. val |= (((runtime->dma_bytes >> 2) &
  91. I2SSIZE_TRNMSK) << I2SSIZE_SHIFT);
  92. writel(val, idma.regs + I2SSIZE);
  93. val = readl(idma.regs + I2SAHB);
  94. val |= AHB_INTENLVL0;
  95. writel(val, idma.regs + I2SAHB);
  96. return 0;
  97. }
  98. static void idma_setcallbk(struct snd_pcm_substream *substream,
  99. void (*cb)(void *, int))
  100. {
  101. struct idma_ctrl *prtd = substream->runtime->private_data;
  102. spin_lock(&prtd->lock);
  103. prtd->cb = cb;
  104. spin_unlock(&prtd->lock);
  105. }
  106. static void idma_control(int op)
  107. {
  108. u32 val = readl(idma.regs + I2SAHB);
  109. spin_lock(&idma.lock);
  110. switch (op) {
  111. case LPAM_DMA_START:
  112. val |= (AHB_INTENLVL0 | AHB_DMAEN);
  113. break;
  114. case LPAM_DMA_STOP:
  115. val &= ~(AHB_INTENLVL0 | AHB_DMAEN);
  116. break;
  117. default:
  118. spin_unlock(&idma.lock);
  119. return;
  120. }
  121. writel(val, idma.regs + I2SAHB);
  122. spin_unlock(&idma.lock);
  123. }
  124. static void idma_done(void *id, int bytes_xfer)
  125. {
  126. struct snd_pcm_substream *substream = id;
  127. struct idma_ctrl *prtd = substream->runtime->private_data;
  128. if (prtd && (prtd->state & ST_RUNNING))
  129. snd_pcm_period_elapsed(substream);
  130. }
  131. static int idma_hw_params(struct snd_pcm_substream *substream,
  132. struct snd_pcm_hw_params *params)
  133. {
  134. struct snd_pcm_runtime *runtime = substream->runtime;
  135. struct idma_ctrl *prtd = substream->runtime->private_data;
  136. u32 mod = readl(idma.regs + I2SMOD);
  137. u32 ahb = readl(idma.regs + I2SAHB);
  138. ahb |= (AHB_DMARLD | AHB_INTMASK);
  139. mod |= MOD_TXS_IDMA;
  140. writel(ahb, idma.regs + I2SAHB);
  141. writel(mod, idma.regs + I2SMOD);
  142. snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
  143. runtime->dma_bytes = params_buffer_bytes(params);
  144. prtd->start = prtd->pos = runtime->dma_addr;
  145. prtd->period = params_periods(params);
  146. prtd->periodsz = params_period_bytes(params);
  147. prtd->end = runtime->dma_addr + runtime->dma_bytes;
  148. idma_setcallbk(substream, idma_done);
  149. return 0;
  150. }
  151. static int idma_hw_free(struct snd_pcm_substream *substream)
  152. {
  153. snd_pcm_set_runtime_buffer(substream, NULL);
  154. return 0;
  155. }
  156. static int idma_prepare(struct snd_pcm_substream *substream)
  157. {
  158. struct idma_ctrl *prtd = substream->runtime->private_data;
  159. prtd->pos = prtd->start;
  160. /* flush the DMA channel */
  161. idma_control(LPAM_DMA_STOP);
  162. idma_enqueue(substream);
  163. return 0;
  164. }
  165. static int idma_trigger(struct snd_pcm_substream *substream, int cmd)
  166. {
  167. struct idma_ctrl *prtd = substream->runtime->private_data;
  168. int ret = 0;
  169. spin_lock(&prtd->lock);
  170. switch (cmd) {
  171. case SNDRV_PCM_TRIGGER_RESUME:
  172. case SNDRV_PCM_TRIGGER_START:
  173. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  174. prtd->state |= ST_RUNNING;
  175. idma_control(LPAM_DMA_START);
  176. break;
  177. case SNDRV_PCM_TRIGGER_SUSPEND:
  178. case SNDRV_PCM_TRIGGER_STOP:
  179. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  180. prtd->state &= ~ST_RUNNING;
  181. idma_control(LPAM_DMA_STOP);
  182. break;
  183. default:
  184. ret = -EINVAL;
  185. break;
  186. }
  187. spin_unlock(&prtd->lock);
  188. return ret;
  189. }
  190. static snd_pcm_uframes_t
  191. idma_pointer(struct snd_pcm_substream *substream)
  192. {
  193. struct snd_pcm_runtime *runtime = substream->runtime;
  194. struct idma_ctrl *prtd = runtime->private_data;
  195. dma_addr_t src;
  196. unsigned long res;
  197. spin_lock(&prtd->lock);
  198. idma_getpos(&src);
  199. res = src - prtd->start;
  200. spin_unlock(&prtd->lock);
  201. return bytes_to_frames(substream->runtime, res);
  202. }
  203. static int idma_mmap(struct snd_pcm_substream *substream,
  204. struct vm_area_struct *vma)
  205. {
  206. struct snd_pcm_runtime *runtime = substream->runtime;
  207. unsigned long size, offset;
  208. int ret;
  209. /* From snd_pcm_lib_mmap_iomem */
  210. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  211. vma->vm_flags |= VM_IO;
  212. size = vma->vm_end - vma->vm_start;
  213. offset = vma->vm_pgoff << PAGE_SHIFT;
  214. ret = io_remap_pfn_range(vma, vma->vm_start,
  215. (runtime->dma_addr + offset) >> PAGE_SHIFT,
  216. size, vma->vm_page_prot);
  217. return ret;
  218. }
  219. static irqreturn_t iis_irq(int irqno, void *dev_id)
  220. {
  221. struct idma_ctrl *prtd = (struct idma_ctrl *)dev_id;
  222. u32 iiscon, iisahb, val, addr;
  223. iisahb = readl(idma.regs + I2SAHB);
  224. iiscon = readl(idma.regs + I2SCON);
  225. val = (iisahb & AHB_LVL0INT) ? AHB_CLRLVL0INT : 0;
  226. if (val) {
  227. iisahb |= val;
  228. writel(iisahb, idma.regs + I2SAHB);
  229. addr = readl(idma.regs + I2SLVL0ADDR) - idma.lp_tx_addr;
  230. addr += prtd->periodsz;
  231. addr %= (prtd->end - prtd->start);
  232. addr += idma.lp_tx_addr;
  233. writel(addr, idma.regs + I2SLVL0ADDR);
  234. if (prtd->cb)
  235. prtd->cb(prtd->token, prtd->period);
  236. }
  237. return IRQ_HANDLED;
  238. }
  239. static int idma_open(struct snd_pcm_substream *substream)
  240. {
  241. struct snd_pcm_runtime *runtime = substream->runtime;
  242. struct idma_ctrl *prtd;
  243. int ret;
  244. snd_soc_set_runtime_hwparams(substream, &idma_hardware);
  245. prtd = kzalloc(sizeof(struct idma_ctrl), GFP_KERNEL);
  246. if (prtd == NULL)
  247. return -ENOMEM;
  248. ret = request_irq(IRQ_I2S0, iis_irq, 0, "i2s", prtd);
  249. if (ret < 0) {
  250. pr_err("fail to claim i2s irq , ret = %d\n", ret);
  251. kfree(prtd);
  252. return ret;
  253. }
  254. spin_lock_init(&prtd->lock);
  255. runtime->private_data = prtd;
  256. return 0;
  257. }
  258. static int idma_close(struct snd_pcm_substream *substream)
  259. {
  260. struct snd_pcm_runtime *runtime = substream->runtime;
  261. struct idma_ctrl *prtd = runtime->private_data;
  262. free_irq(IRQ_I2S0, prtd);
  263. if (!prtd)
  264. pr_err("idma_close called with prtd == NULL\n");
  265. kfree(prtd);
  266. return 0;
  267. }
  268. static struct snd_pcm_ops idma_ops = {
  269. .open = idma_open,
  270. .close = idma_close,
  271. .ioctl = snd_pcm_lib_ioctl,
  272. .trigger = idma_trigger,
  273. .pointer = idma_pointer,
  274. .mmap = idma_mmap,
  275. .hw_params = idma_hw_params,
  276. .hw_free = idma_hw_free,
  277. .prepare = idma_prepare,
  278. };
  279. static void idma_free(struct snd_pcm *pcm)
  280. {
  281. struct snd_pcm_substream *substream;
  282. struct snd_dma_buffer *buf;
  283. substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
  284. if (!substream)
  285. return;
  286. buf = &substream->dma_buffer;
  287. if (!buf->area)
  288. return;
  289. iounmap(buf->area);
  290. buf->area = NULL;
  291. buf->addr = 0;
  292. }
  293. static int preallocate_idma_buffer(struct snd_pcm *pcm, int stream)
  294. {
  295. struct snd_pcm_substream *substream = pcm->streams[stream].substream;
  296. struct snd_dma_buffer *buf = &substream->dma_buffer;
  297. buf->dev.dev = pcm->card->dev;
  298. buf->private_data = NULL;
  299. /* Assign PCM buffer pointers */
  300. buf->dev.type = SNDRV_DMA_TYPE_CONTINUOUS;
  301. buf->addr = idma.lp_tx_addr;
  302. buf->bytes = idma_hardware.buffer_bytes_max;
  303. buf->area = (unsigned char *)ioremap(buf->addr, buf->bytes);
  304. return 0;
  305. }
  306. static u64 idma_mask = DMA_BIT_MASK(32);
  307. static int idma_new(struct snd_soc_pcm_runtime *rtd)
  308. {
  309. struct snd_card *card = rtd->card->snd_card;
  310. struct snd_pcm *pcm = rtd->pcm;
  311. int ret = 0;
  312. if (!card->dev->dma_mask)
  313. card->dev->dma_mask = &idma_mask;
  314. if (!card->dev->coherent_dma_mask)
  315. card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
  316. if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
  317. ret = preallocate_idma_buffer(pcm,
  318. SNDRV_PCM_STREAM_PLAYBACK);
  319. }
  320. return ret;
  321. }
  322. void idma_reg_addr_init(void __iomem *regs, dma_addr_t addr)
  323. {
  324. spin_lock_init(&idma.lock);
  325. idma.regs = regs;
  326. idma.lp_tx_addr = addr;
  327. }
  328. static struct snd_soc_platform_driver asoc_idma_platform = {
  329. .ops = &idma_ops,
  330. .pcm_new = idma_new,
  331. .pcm_free = idma_free,
  332. };
  333. static int __devinit asoc_idma_platform_probe(struct platform_device *pdev)
  334. {
  335. return snd_soc_register_platform(&pdev->dev, &asoc_idma_platform);
  336. }
  337. static int __devexit asoc_idma_platform_remove(struct platform_device *pdev)
  338. {
  339. snd_soc_unregister_platform(&pdev->dev);
  340. return 0;
  341. }
  342. static struct platform_driver asoc_idma_driver = {
  343. .driver = {
  344. .name = "samsung-idma",
  345. .owner = THIS_MODULE,
  346. },
  347. .probe = asoc_idma_platform_probe,
  348. .remove = __devexit_p(asoc_idma_platform_remove),
  349. };
  350. module_platform_driver(asoc_idma_driver);
  351. MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
  352. MODULE_DESCRIPTION("Samsung ASoC IDMA Driver");
  353. MODULE_LICENSE("GPL");