wm8991.c 43 KB

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  1. /*
  2. * wm8991.c -- WM8991 ALSA Soc Audio driver
  3. *
  4. * Copyright 2007-2010 Wolfson Microelectronics PLC.
  5. * Author: Graeme Gregory
  6. * Graeme.Gregory@wolfsonmicro.com
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/delay.h>
  18. #include <linux/pm.h>
  19. #include <linux/i2c.h>
  20. #include <linux/slab.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/initval.h>
  27. #include <sound/tlv.h>
  28. #include <asm/div64.h>
  29. #include "wm8991.h"
  30. struct wm8991_priv {
  31. enum snd_soc_control_type control_type;
  32. unsigned int pcmclk;
  33. };
  34. static const u16 wm8991_reg_defs[] = {
  35. 0x8991, /* R0 - Reset */
  36. 0x0000, /* R1 - Power Management (1) */
  37. 0x6000, /* R2 - Power Management (2) */
  38. 0x0000, /* R3 - Power Management (3) */
  39. 0x4050, /* R4 - Audio Interface (1) */
  40. 0x4000, /* R5 - Audio Interface (2) */
  41. 0x01C8, /* R6 - Clocking (1) */
  42. 0x0000, /* R7 - Clocking (2) */
  43. 0x0040, /* R8 - Audio Interface (3) */
  44. 0x0040, /* R9 - Audio Interface (4) */
  45. 0x0004, /* R10 - DAC CTRL */
  46. 0x00C0, /* R11 - Left DAC Digital Volume */
  47. 0x00C0, /* R12 - Right DAC Digital Volume */
  48. 0x0000, /* R13 - Digital Side Tone */
  49. 0x0100, /* R14 - ADC CTRL */
  50. 0x00C0, /* R15 - Left ADC Digital Volume */
  51. 0x00C0, /* R16 - Right ADC Digital Volume */
  52. 0x0000, /* R17 */
  53. 0x0000, /* R18 - GPIO CTRL 1 */
  54. 0x1000, /* R19 - GPIO1 & GPIO2 */
  55. 0x1010, /* R20 - GPIO3 & GPIO4 */
  56. 0x1010, /* R21 - GPIO5 & GPIO6 */
  57. 0x8000, /* R22 - GPIOCTRL 2 */
  58. 0x0800, /* R23 - GPIO_POL */
  59. 0x008B, /* R24 - Left Line Input 1&2 Volume */
  60. 0x008B, /* R25 - Left Line Input 3&4 Volume */
  61. 0x008B, /* R26 - Right Line Input 1&2 Volume */
  62. 0x008B, /* R27 - Right Line Input 3&4 Volume */
  63. 0x0000, /* R28 - Left Output Volume */
  64. 0x0000, /* R29 - Right Output Volume */
  65. 0x0066, /* R30 - Line Outputs Volume */
  66. 0x0022, /* R31 - Out3/4 Volume */
  67. 0x0079, /* R32 - Left OPGA Volume */
  68. 0x0079, /* R33 - Right OPGA Volume */
  69. 0x0003, /* R34 - Speaker Volume */
  70. 0x0003, /* R35 - ClassD1 */
  71. 0x0000, /* R36 */
  72. 0x0100, /* R37 - ClassD3 */
  73. 0x0000, /* R38 */
  74. 0x0000, /* R39 - Input Mixer1 */
  75. 0x0000, /* R40 - Input Mixer2 */
  76. 0x0000, /* R41 - Input Mixer3 */
  77. 0x0000, /* R42 - Input Mixer4 */
  78. 0x0000, /* R43 - Input Mixer5 */
  79. 0x0000, /* R44 - Input Mixer6 */
  80. 0x0000, /* R45 - Output Mixer1 */
  81. 0x0000, /* R46 - Output Mixer2 */
  82. 0x0000, /* R47 - Output Mixer3 */
  83. 0x0000, /* R48 - Output Mixer4 */
  84. 0x0000, /* R49 - Output Mixer5 */
  85. 0x0000, /* R50 - Output Mixer6 */
  86. 0x0180, /* R51 - Out3/4 Mixer */
  87. 0x0000, /* R52 - Line Mixer1 */
  88. 0x0000, /* R53 - Line Mixer2 */
  89. 0x0000, /* R54 - Speaker Mixer */
  90. 0x0000, /* R55 - Additional Control */
  91. 0x0000, /* R56 - AntiPOP1 */
  92. 0x0000, /* R57 - AntiPOP2 */
  93. 0x0000, /* R58 - MICBIAS */
  94. 0x0000, /* R59 */
  95. 0x0008, /* R60 - PLL1 */
  96. 0x0031, /* R61 - PLL2 */
  97. 0x0026, /* R62 - PLL3 */
  98. };
  99. #define wm8991_reset(c) snd_soc_write(c, WM8991_RESET, 0)
  100. static const unsigned int rec_mix_tlv[] = {
  101. TLV_DB_RANGE_HEAD(1),
  102. 0, 7, TLV_DB_LINEAR_ITEM(-1500, 600),
  103. };
  104. static const unsigned int in_pga_tlv[] = {
  105. TLV_DB_RANGE_HEAD(1),
  106. 0, 0x1F, TLV_DB_LINEAR_ITEM(-1650, 3000),
  107. };
  108. static const unsigned int out_mix_tlv[] = {
  109. TLV_DB_RANGE_HEAD(1),
  110. 0, 7, TLV_DB_LINEAR_ITEM(0, -2100),
  111. };
  112. static const unsigned int out_pga_tlv[] = {
  113. TLV_DB_RANGE_HEAD(1),
  114. 0, 127, TLV_DB_LINEAR_ITEM(-7300, 600),
  115. };
  116. static const unsigned int out_omix_tlv[] = {
  117. TLV_DB_RANGE_HEAD(1),
  118. 0, 7, TLV_DB_LINEAR_ITEM(-600, 0),
  119. };
  120. static const unsigned int out_dac_tlv[] = {
  121. TLV_DB_RANGE_HEAD(1),
  122. 0, 255, TLV_DB_LINEAR_ITEM(-7163, 0),
  123. };
  124. static const unsigned int in_adc_tlv[] = {
  125. TLV_DB_RANGE_HEAD(1),
  126. 0, 255, TLV_DB_LINEAR_ITEM(-7163, 1763),
  127. };
  128. static const unsigned int out_sidetone_tlv[] = {
  129. TLV_DB_RANGE_HEAD(1),
  130. 0, 31, TLV_DB_LINEAR_ITEM(-3600, 0),
  131. };
  132. static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
  133. struct snd_ctl_elem_value *ucontrol)
  134. {
  135. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  136. int reg = kcontrol->private_value & 0xff;
  137. int ret;
  138. u16 val;
  139. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  140. if (ret < 0)
  141. return ret;
  142. /* now hit the volume update bits (always bit 8) */
  143. val = snd_soc_read(codec, reg);
  144. return snd_soc_write(codec, reg, val | 0x0100);
  145. }
  146. static const char *wm8991_digital_sidetone[] =
  147. {"None", "Left ADC", "Right ADC", "Reserved"};
  148. static const struct soc_enum wm8991_left_digital_sidetone_enum =
  149. SOC_ENUM_SINGLE(WM8991_DIGITAL_SIDE_TONE,
  150. WM8991_ADC_TO_DACL_SHIFT,
  151. WM8991_ADC_TO_DACL_MASK,
  152. wm8991_digital_sidetone);
  153. static const struct soc_enum wm8991_right_digital_sidetone_enum =
  154. SOC_ENUM_SINGLE(WM8991_DIGITAL_SIDE_TONE,
  155. WM8991_ADC_TO_DACR_SHIFT,
  156. WM8991_ADC_TO_DACR_MASK,
  157. wm8991_digital_sidetone);
  158. static const char *wm8991_adcmode[] =
  159. {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
  160. static const struct soc_enum wm8991_right_adcmode_enum =
  161. SOC_ENUM_SINGLE(WM8991_ADC_CTRL,
  162. WM8991_ADC_HPF_CUT_SHIFT,
  163. WM8991_ADC_HPF_CUT_MASK,
  164. wm8991_adcmode);
  165. static const struct snd_kcontrol_new wm8991_snd_controls[] = {
  166. /* INMIXL */
  167. SOC_SINGLE("LIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L12MNBST_BIT, 1, 0),
  168. SOC_SINGLE("LIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L34MNBST_BIT, 1, 0),
  169. /* INMIXR */
  170. SOC_SINGLE("RIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R12MNBST_BIT, 1, 0),
  171. SOC_SINGLE("RIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R34MNBST_BIT, 1, 0),
  172. /* LOMIX */
  173. SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER3,
  174. WM8991_LLI3LOVOL_SHIFT, WM8991_LLI3LOVOL_MASK, 1, out_mix_tlv),
  175. SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3,
  176. WM8991_LR12LOVOL_SHIFT, WM8991_LR12LOVOL_MASK, 1, out_mix_tlv),
  177. SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3,
  178. WM8991_LL12LOVOL_SHIFT, WM8991_LL12LOVOL_MASK, 1, out_mix_tlv),
  179. SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER5,
  180. WM8991_LRI3LOVOL_SHIFT, WM8991_LRI3LOVOL_MASK, 1, out_mix_tlv),
  181. SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER5,
  182. WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv),
  183. SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER5,
  184. WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv),
  185. /* ROMIX */
  186. SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER4,
  187. WM8991_RRI3ROVOL_SHIFT, WM8991_RRI3ROVOL_MASK, 1, out_mix_tlv),
  188. SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4,
  189. WM8991_RL12ROVOL_SHIFT, WM8991_RL12ROVOL_MASK, 1, out_mix_tlv),
  190. SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4,
  191. WM8991_RR12ROVOL_SHIFT, WM8991_RR12ROVOL_MASK, 1, out_mix_tlv),
  192. SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER6,
  193. WM8991_RLI3ROVOL_SHIFT, WM8991_RLI3ROVOL_MASK, 1, out_mix_tlv),
  194. SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER6,
  195. WM8991_RLBROVOL_SHIFT, WM8991_RLBROVOL_MASK, 1, out_mix_tlv),
  196. SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER6,
  197. WM8991_RRBROVOL_SHIFT, WM8991_RRBROVOL_MASK, 1, out_mix_tlv),
  198. /* LOUT */
  199. SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8991_LEFT_OUTPUT_VOLUME,
  200. WM8991_LOUTVOL_SHIFT, WM8991_LOUTVOL_MASK, 0, out_pga_tlv),
  201. SOC_SINGLE("LOUT ZC", WM8991_LEFT_OUTPUT_VOLUME, WM8991_LOZC_BIT, 1, 0),
  202. /* ROUT */
  203. SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8991_RIGHT_OUTPUT_VOLUME,
  204. WM8991_ROUTVOL_SHIFT, WM8991_ROUTVOL_MASK, 0, out_pga_tlv),
  205. SOC_SINGLE("ROUT ZC", WM8991_RIGHT_OUTPUT_VOLUME, WM8991_ROZC_BIT, 1, 0),
  206. /* LOPGA */
  207. SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8991_LEFT_OPGA_VOLUME,
  208. WM8991_LOPGAVOL_SHIFT, WM8991_LOPGAVOL_MASK, 0, out_pga_tlv),
  209. SOC_SINGLE("LOPGA ZC Switch", WM8991_LEFT_OPGA_VOLUME,
  210. WM8991_LOPGAZC_BIT, 1, 0),
  211. /* ROPGA */
  212. SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8991_RIGHT_OPGA_VOLUME,
  213. WM8991_ROPGAVOL_SHIFT, WM8991_ROPGAVOL_MASK, 0, out_pga_tlv),
  214. SOC_SINGLE("ROPGA ZC Switch", WM8991_RIGHT_OPGA_VOLUME,
  215. WM8991_ROPGAZC_BIT, 1, 0),
  216. SOC_SINGLE("LON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
  217. WM8991_LONMUTE_BIT, 1, 0),
  218. SOC_SINGLE("LOP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
  219. WM8991_LOPMUTE_BIT, 1, 0),
  220. SOC_SINGLE("LOP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME,
  221. WM8991_LOATTN_BIT, 1, 0),
  222. SOC_SINGLE("RON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
  223. WM8991_RONMUTE_BIT, 1, 0),
  224. SOC_SINGLE("ROP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
  225. WM8991_ROPMUTE_BIT, 1, 0),
  226. SOC_SINGLE("ROP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME,
  227. WM8991_ROATTN_BIT, 1, 0),
  228. SOC_SINGLE("OUT3 Mute Switch", WM8991_OUT3_4_VOLUME,
  229. WM8991_OUT3MUTE_BIT, 1, 0),
  230. SOC_SINGLE("OUT3 Attenuation Switch", WM8991_OUT3_4_VOLUME,
  231. WM8991_OUT3ATTN_BIT, 1, 0),
  232. SOC_SINGLE("OUT4 Mute Switch", WM8991_OUT3_4_VOLUME,
  233. WM8991_OUT4MUTE_BIT, 1, 0),
  234. SOC_SINGLE("OUT4 Attenuation Switch", WM8991_OUT3_4_VOLUME,
  235. WM8991_OUT4ATTN_BIT, 1, 0),
  236. SOC_SINGLE("Speaker Mode Switch", WM8991_CLASSD1,
  237. WM8991_CDMODE_BIT, 1, 0),
  238. SOC_SINGLE("Speaker Output Attenuation Volume", WM8991_SPEAKER_VOLUME,
  239. WM8991_SPKVOL_SHIFT, WM8991_SPKVOL_MASK, 0),
  240. SOC_SINGLE("Speaker DC Boost Volume", WM8991_CLASSD3,
  241. WM8991_DCGAIN_SHIFT, WM8991_DCGAIN_MASK, 0),
  242. SOC_SINGLE("Speaker AC Boost Volume", WM8991_CLASSD3,
  243. WM8991_ACGAIN_SHIFT, WM8991_ACGAIN_MASK, 0),
  244. SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
  245. WM8991_LEFT_DAC_DIGITAL_VOLUME,
  246. WM8991_DACL_VOL_SHIFT,
  247. WM8991_DACL_VOL_MASK,
  248. 0,
  249. out_dac_tlv),
  250. SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
  251. WM8991_RIGHT_DAC_DIGITAL_VOLUME,
  252. WM8991_DACR_VOL_SHIFT,
  253. WM8991_DACR_VOL_MASK,
  254. 0,
  255. out_dac_tlv),
  256. SOC_ENUM("Left Digital Sidetone", wm8991_left_digital_sidetone_enum),
  257. SOC_ENUM("Right Digital Sidetone", wm8991_right_digital_sidetone_enum),
  258. SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE,
  259. WM8991_ADCL_DAC_SVOL_SHIFT, WM8991_ADCL_DAC_SVOL_MASK, 0,
  260. out_sidetone_tlv),
  261. SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE,
  262. WM8991_ADCR_DAC_SVOL_SHIFT, WM8991_ADCR_DAC_SVOL_MASK, 0,
  263. out_sidetone_tlv),
  264. SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8991_ADC_CTRL,
  265. WM8991_ADC_HPF_ENA_BIT, 1, 0),
  266. SOC_ENUM("ADC HPF Mode", wm8991_right_adcmode_enum),
  267. SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
  268. WM8991_LEFT_ADC_DIGITAL_VOLUME,
  269. WM8991_ADCL_VOL_SHIFT,
  270. WM8991_ADCL_VOL_MASK,
  271. 0,
  272. in_adc_tlv),
  273. SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
  274. WM8991_RIGHT_ADC_DIGITAL_VOLUME,
  275. WM8991_ADCR_VOL_SHIFT,
  276. WM8991_ADCR_VOL_MASK,
  277. 0,
  278. in_adc_tlv),
  279. SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
  280. WM8991_LEFT_LINE_INPUT_1_2_VOLUME,
  281. WM8991_LIN12VOL_SHIFT,
  282. WM8991_LIN12VOL_MASK,
  283. 0,
  284. in_pga_tlv),
  285. SOC_SINGLE("LIN12 ZC Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME,
  286. WM8991_LI12ZC_BIT, 1, 0),
  287. SOC_SINGLE("LIN12 Mute Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME,
  288. WM8991_LI12MUTE_BIT, 1, 0),
  289. SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
  290. WM8991_LEFT_LINE_INPUT_3_4_VOLUME,
  291. WM8991_LIN34VOL_SHIFT,
  292. WM8991_LIN34VOL_MASK,
  293. 0,
  294. in_pga_tlv),
  295. SOC_SINGLE("LIN34 ZC Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME,
  296. WM8991_LI34ZC_BIT, 1, 0),
  297. SOC_SINGLE("LIN34 Mute Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME,
  298. WM8991_LI34MUTE_BIT, 1, 0),
  299. SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
  300. WM8991_RIGHT_LINE_INPUT_1_2_VOLUME,
  301. WM8991_RIN12VOL_SHIFT,
  302. WM8991_RIN12VOL_MASK,
  303. 0,
  304. in_pga_tlv),
  305. SOC_SINGLE("RIN12 ZC Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME,
  306. WM8991_RI12ZC_BIT, 1, 0),
  307. SOC_SINGLE("RIN12 Mute Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME,
  308. WM8991_RI12MUTE_BIT, 1, 0),
  309. SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
  310. WM8991_RIGHT_LINE_INPUT_3_4_VOLUME,
  311. WM8991_RIN34VOL_SHIFT,
  312. WM8991_RIN34VOL_MASK,
  313. 0,
  314. in_pga_tlv),
  315. SOC_SINGLE("RIN34 ZC Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME,
  316. WM8991_RI34ZC_BIT, 1, 0),
  317. SOC_SINGLE("RIN34 Mute Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME,
  318. WM8991_RI34MUTE_BIT, 1, 0),
  319. };
  320. /*
  321. * _DAPM_ Controls
  322. */
  323. static int inmixer_event(struct snd_soc_dapm_widget *w,
  324. struct snd_kcontrol *kcontrol, int event)
  325. {
  326. u16 reg, fakepower;
  327. reg = snd_soc_read(w->codec, WM8991_POWER_MANAGEMENT_2);
  328. fakepower = snd_soc_read(w->codec, WM8991_INTDRIVBITS);
  329. if (fakepower & ((1 << WM8991_INMIXL_PWR_BIT) |
  330. (1 << WM8991_AINLMUX_PWR_BIT)))
  331. reg |= WM8991_AINL_ENA;
  332. else
  333. reg &= ~WM8991_AINL_ENA;
  334. if (fakepower & ((1 << WM8991_INMIXR_PWR_BIT) |
  335. (1 << WM8991_AINRMUX_PWR_BIT)))
  336. reg |= WM8991_AINR_ENA;
  337. else
  338. reg &= ~WM8991_AINR_ENA;
  339. snd_soc_write(w->codec, WM8991_POWER_MANAGEMENT_2, reg);
  340. return 0;
  341. }
  342. static int outmixer_event(struct snd_soc_dapm_widget *w,
  343. struct snd_kcontrol *kcontrol, int event)
  344. {
  345. u32 reg_shift = kcontrol->private_value & 0xfff;
  346. int ret = 0;
  347. u16 reg;
  348. switch (reg_shift) {
  349. case WM8991_SPEAKER_MIXER | (WM8991_LDSPK_BIT << 8):
  350. reg = snd_soc_read(w->codec, WM8991_OUTPUT_MIXER1);
  351. if (reg & WM8991_LDLO) {
  352. printk(KERN_WARNING
  353. "Cannot set as Output Mixer 1 LDLO Set\n");
  354. ret = -1;
  355. }
  356. break;
  357. case WM8991_SPEAKER_MIXER | (WM8991_RDSPK_BIT << 8):
  358. reg = snd_soc_read(w->codec, WM8991_OUTPUT_MIXER2);
  359. if (reg & WM8991_RDRO) {
  360. printk(KERN_WARNING
  361. "Cannot set as Output Mixer 2 RDRO Set\n");
  362. ret = -1;
  363. }
  364. break;
  365. case WM8991_OUTPUT_MIXER1 | (WM8991_LDLO_BIT << 8):
  366. reg = snd_soc_read(w->codec, WM8991_SPEAKER_MIXER);
  367. if (reg & WM8991_LDSPK) {
  368. printk(KERN_WARNING
  369. "Cannot set as Speaker Mixer LDSPK Set\n");
  370. ret = -1;
  371. }
  372. break;
  373. case WM8991_OUTPUT_MIXER2 | (WM8991_RDRO_BIT << 8):
  374. reg = snd_soc_read(w->codec, WM8991_SPEAKER_MIXER);
  375. if (reg & WM8991_RDSPK) {
  376. printk(KERN_WARNING
  377. "Cannot set as Speaker Mixer RDSPK Set\n");
  378. ret = -1;
  379. }
  380. break;
  381. }
  382. return ret;
  383. }
  384. /* INMIX dB values */
  385. static const unsigned int in_mix_tlv[] = {
  386. TLV_DB_RANGE_HEAD(1),
  387. 0, 7, TLV_DB_LINEAR_ITEM(-1200, 600),
  388. };
  389. /* Left In PGA Connections */
  390. static const struct snd_kcontrol_new wm8991_dapm_lin12_pga_controls[] = {
  391. SOC_DAPM_SINGLE("LIN1 Switch", WM8991_INPUT_MIXER2, WM8991_LMN1_BIT, 1, 0),
  392. SOC_DAPM_SINGLE("LIN2 Switch", WM8991_INPUT_MIXER2, WM8991_LMP2_BIT, 1, 0),
  393. };
  394. static const struct snd_kcontrol_new wm8991_dapm_lin34_pga_controls[] = {
  395. SOC_DAPM_SINGLE("LIN3 Switch", WM8991_INPUT_MIXER2, WM8991_LMN3_BIT, 1, 0),
  396. SOC_DAPM_SINGLE("LIN4 Switch", WM8991_INPUT_MIXER2, WM8991_LMP4_BIT, 1, 0),
  397. };
  398. /* Right In PGA Connections */
  399. static const struct snd_kcontrol_new wm8991_dapm_rin12_pga_controls[] = {
  400. SOC_DAPM_SINGLE("RIN1 Switch", WM8991_INPUT_MIXER2, WM8991_RMN1_BIT, 1, 0),
  401. SOC_DAPM_SINGLE("RIN2 Switch", WM8991_INPUT_MIXER2, WM8991_RMP2_BIT, 1, 0),
  402. };
  403. static const struct snd_kcontrol_new wm8991_dapm_rin34_pga_controls[] = {
  404. SOC_DAPM_SINGLE("RIN3 Switch", WM8991_INPUT_MIXER2, WM8991_RMN3_BIT, 1, 0),
  405. SOC_DAPM_SINGLE("RIN4 Switch", WM8991_INPUT_MIXER2, WM8991_RMP4_BIT, 1, 0),
  406. };
  407. /* INMIXL */
  408. static const struct snd_kcontrol_new wm8991_dapm_inmixl_controls[] = {
  409. SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8991_INPUT_MIXER3,
  410. WM8991_LDBVOL_SHIFT, WM8991_LDBVOL_MASK, 0, in_mix_tlv),
  411. SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8991_INPUT_MIXER5, WM8991_LI2BVOL_SHIFT,
  412. 7, 0, in_mix_tlv),
  413. SOC_DAPM_SINGLE("LINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT,
  414. 1, 0),
  415. SOC_DAPM_SINGLE("LINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT,
  416. 1, 0),
  417. };
  418. /* INMIXR */
  419. static const struct snd_kcontrol_new wm8991_dapm_inmixr_controls[] = {
  420. SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8991_INPUT_MIXER4,
  421. WM8991_RDBVOL_SHIFT, WM8991_RDBVOL_MASK, 0, in_mix_tlv),
  422. SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8991_INPUT_MIXER6, WM8991_RI2BVOL_SHIFT,
  423. 7, 0, in_mix_tlv),
  424. SOC_DAPM_SINGLE("RINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT,
  425. 1, 0),
  426. SOC_DAPM_SINGLE("RINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT,
  427. 1, 0),
  428. };
  429. /* AINLMUX */
  430. static const char *wm8991_ainlmux[] =
  431. {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
  432. static const struct soc_enum wm8991_ainlmux_enum =
  433. SOC_ENUM_SINGLE(WM8991_INPUT_MIXER1, WM8991_AINLMODE_SHIFT,
  434. ARRAY_SIZE(wm8991_ainlmux), wm8991_ainlmux);
  435. static const struct snd_kcontrol_new wm8991_dapm_ainlmux_controls =
  436. SOC_DAPM_ENUM("Route", wm8991_ainlmux_enum);
  437. /* DIFFINL */
  438. /* AINRMUX */
  439. static const char *wm8991_ainrmux[] =
  440. {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
  441. static const struct soc_enum wm8991_ainrmux_enum =
  442. SOC_ENUM_SINGLE(WM8991_INPUT_MIXER1, WM8991_AINRMODE_SHIFT,
  443. ARRAY_SIZE(wm8991_ainrmux), wm8991_ainrmux);
  444. static const struct snd_kcontrol_new wm8991_dapm_ainrmux_controls =
  445. SOC_DAPM_ENUM("Route", wm8991_ainrmux_enum);
  446. /* RXVOICE */
  447. static const struct snd_kcontrol_new wm8991_dapm_rxvoice_controls[] = {
  448. SOC_DAPM_SINGLE_TLV("LIN4RXN", WM8991_INPUT_MIXER5, WM8991_LR4BVOL_SHIFT,
  449. WM8991_LR4BVOL_MASK, 0, in_mix_tlv),
  450. SOC_DAPM_SINGLE_TLV("RIN4RXP", WM8991_INPUT_MIXER6, WM8991_RL4BVOL_SHIFT,
  451. WM8991_RL4BVOL_MASK, 0, in_mix_tlv),
  452. };
  453. /* LOMIX */
  454. static const struct snd_kcontrol_new wm8991_dapm_lomix_controls[] = {
  455. SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER1,
  456. WM8991_LRBLO_BIT, 1, 0),
  457. SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER1,
  458. WM8991_LLBLO_BIT, 1, 0),
  459. SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER1,
  460. WM8991_LRI3LO_BIT, 1, 0),
  461. SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER1,
  462. WM8991_LLI3LO_BIT, 1, 0),
  463. SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1,
  464. WM8991_LR12LO_BIT, 1, 0),
  465. SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1,
  466. WM8991_LL12LO_BIT, 1, 0),
  467. SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8991_OUTPUT_MIXER1,
  468. WM8991_LDLO_BIT, 1, 0),
  469. };
  470. /* ROMIX */
  471. static const struct snd_kcontrol_new wm8991_dapm_romix_controls[] = {
  472. SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER2,
  473. WM8991_RLBRO_BIT, 1, 0),
  474. SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER2,
  475. WM8991_RRBRO_BIT, 1, 0),
  476. SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER2,
  477. WM8991_RLI3RO_BIT, 1, 0),
  478. SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER2,
  479. WM8991_RRI3RO_BIT, 1, 0),
  480. SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2,
  481. WM8991_RL12RO_BIT, 1, 0),
  482. SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2,
  483. WM8991_RR12RO_BIT, 1, 0),
  484. SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8991_OUTPUT_MIXER2,
  485. WM8991_RDRO_BIT, 1, 0),
  486. };
  487. /* LONMIX */
  488. static const struct snd_kcontrol_new wm8991_dapm_lonmix_controls[] = {
  489. SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1,
  490. WM8991_LLOPGALON_BIT, 1, 0),
  491. SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER1,
  492. WM8991_LROPGALON_BIT, 1, 0),
  493. SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8991_LINE_MIXER1,
  494. WM8991_LOPLON_BIT, 1, 0),
  495. };
  496. /* LOPMIX */
  497. static const struct snd_kcontrol_new wm8991_dapm_lopmix_controls[] = {
  498. SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER1,
  499. WM8991_LR12LOP_BIT, 1, 0),
  500. SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER1,
  501. WM8991_LL12LOP_BIT, 1, 0),
  502. SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1,
  503. WM8991_LLOPGALOP_BIT, 1, 0),
  504. };
  505. /* RONMIX */
  506. static const struct snd_kcontrol_new wm8991_dapm_ronmix_controls[] = {
  507. SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2,
  508. WM8991_RROPGARON_BIT, 1, 0),
  509. SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER2,
  510. WM8991_RLOPGARON_BIT, 1, 0),
  511. SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8991_LINE_MIXER2,
  512. WM8991_ROPRON_BIT, 1, 0),
  513. };
  514. /* ROPMIX */
  515. static const struct snd_kcontrol_new wm8991_dapm_ropmix_controls[] = {
  516. SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER2,
  517. WM8991_RL12ROP_BIT, 1, 0),
  518. SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER2,
  519. WM8991_RR12ROP_BIT, 1, 0),
  520. SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2,
  521. WM8991_RROPGAROP_BIT, 1, 0),
  522. };
  523. /* OUT3MIX */
  524. static const struct snd_kcontrol_new wm8991_dapm_out3mix_controls[] = {
  525. SOC_DAPM_SINGLE("OUT3MIX LIN4RXN Bypass Switch", WM8991_OUT3_4_MIXER,
  526. WM8991_LI4O3_BIT, 1, 0),
  527. SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8991_OUT3_4_MIXER,
  528. WM8991_LPGAO3_BIT, 1, 0),
  529. };
  530. /* OUT4MIX */
  531. static const struct snd_kcontrol_new wm8991_dapm_out4mix_controls[] = {
  532. SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8991_OUT3_4_MIXER,
  533. WM8991_RPGAO4_BIT, 1, 0),
  534. SOC_DAPM_SINGLE("OUT4MIX RIN4RXP Bypass Switch", WM8991_OUT3_4_MIXER,
  535. WM8991_RI4O4_BIT, 1, 0),
  536. };
  537. /* SPKMIX */
  538. static const struct snd_kcontrol_new wm8991_dapm_spkmix_controls[] = {
  539. SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8991_SPEAKER_MIXER,
  540. WM8991_LI2SPK_BIT, 1, 0),
  541. SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8991_SPEAKER_MIXER,
  542. WM8991_LB2SPK_BIT, 1, 0),
  543. SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8991_SPEAKER_MIXER,
  544. WM8991_LOPGASPK_BIT, 1, 0),
  545. SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8991_SPEAKER_MIXER,
  546. WM8991_LDSPK_BIT, 1, 0),
  547. SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8991_SPEAKER_MIXER,
  548. WM8991_RDSPK_BIT, 1, 0),
  549. SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8991_SPEAKER_MIXER,
  550. WM8991_ROPGASPK_BIT, 1, 0),
  551. SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8991_SPEAKER_MIXER,
  552. WM8991_RL12ROP_BIT, 1, 0),
  553. SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8991_SPEAKER_MIXER,
  554. WM8991_RI2SPK_BIT, 1, 0),
  555. };
  556. static const struct snd_soc_dapm_widget wm8991_dapm_widgets[] = {
  557. /* Input Side */
  558. /* Input Lines */
  559. SND_SOC_DAPM_INPUT("LIN1"),
  560. SND_SOC_DAPM_INPUT("LIN2"),
  561. SND_SOC_DAPM_INPUT("LIN3"),
  562. SND_SOC_DAPM_INPUT("LIN4RXN"),
  563. SND_SOC_DAPM_INPUT("RIN3"),
  564. SND_SOC_DAPM_INPUT("RIN4RXP"),
  565. SND_SOC_DAPM_INPUT("RIN1"),
  566. SND_SOC_DAPM_INPUT("RIN2"),
  567. SND_SOC_DAPM_INPUT("Internal ADC Source"),
  568. /* DACs */
  569. SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8991_POWER_MANAGEMENT_2,
  570. WM8991_ADCL_ENA_BIT, 0),
  571. SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8991_POWER_MANAGEMENT_2,
  572. WM8991_ADCR_ENA_BIT, 0),
  573. /* Input PGAs */
  574. SND_SOC_DAPM_MIXER("LIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN12_ENA_BIT,
  575. 0, &wm8991_dapm_lin12_pga_controls[0],
  576. ARRAY_SIZE(wm8991_dapm_lin12_pga_controls)),
  577. SND_SOC_DAPM_MIXER("LIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN34_ENA_BIT,
  578. 0, &wm8991_dapm_lin34_pga_controls[0],
  579. ARRAY_SIZE(wm8991_dapm_lin34_pga_controls)),
  580. SND_SOC_DAPM_MIXER("RIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN12_ENA_BIT,
  581. 0, &wm8991_dapm_rin12_pga_controls[0],
  582. ARRAY_SIZE(wm8991_dapm_rin12_pga_controls)),
  583. SND_SOC_DAPM_MIXER("RIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN34_ENA_BIT,
  584. 0, &wm8991_dapm_rin34_pga_controls[0],
  585. ARRAY_SIZE(wm8991_dapm_rin34_pga_controls)),
  586. /* INMIXL */
  587. SND_SOC_DAPM_MIXER_E("INMIXL", WM8991_INTDRIVBITS, WM8991_INMIXL_PWR_BIT, 0,
  588. &wm8991_dapm_inmixl_controls[0],
  589. ARRAY_SIZE(wm8991_dapm_inmixl_controls),
  590. inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  591. /* AINLMUX */
  592. SND_SOC_DAPM_MUX_E("AINLMUX", WM8991_INTDRIVBITS, WM8991_AINLMUX_PWR_BIT, 0,
  593. &wm8991_dapm_ainlmux_controls, inmixer_event,
  594. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  595. /* INMIXR */
  596. SND_SOC_DAPM_MIXER_E("INMIXR", WM8991_INTDRIVBITS, WM8991_INMIXR_PWR_BIT, 0,
  597. &wm8991_dapm_inmixr_controls[0],
  598. ARRAY_SIZE(wm8991_dapm_inmixr_controls),
  599. inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  600. /* AINRMUX */
  601. SND_SOC_DAPM_MUX_E("AINRMUX", WM8991_INTDRIVBITS, WM8991_AINRMUX_PWR_BIT, 0,
  602. &wm8991_dapm_ainrmux_controls, inmixer_event,
  603. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  604. /* Output Side */
  605. /* DACs */
  606. SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8991_POWER_MANAGEMENT_3,
  607. WM8991_DACL_ENA_BIT, 0),
  608. SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8991_POWER_MANAGEMENT_3,
  609. WM8991_DACR_ENA_BIT, 0),
  610. /* LOMIX */
  611. SND_SOC_DAPM_MIXER_E("LOMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOMIX_ENA_BIT,
  612. 0, &wm8991_dapm_lomix_controls[0],
  613. ARRAY_SIZE(wm8991_dapm_lomix_controls),
  614. outmixer_event, SND_SOC_DAPM_PRE_REG),
  615. /* LONMIX */
  616. SND_SOC_DAPM_MIXER("LONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LON_ENA_BIT, 0,
  617. &wm8991_dapm_lonmix_controls[0],
  618. ARRAY_SIZE(wm8991_dapm_lonmix_controls)),
  619. /* LOPMIX */
  620. SND_SOC_DAPM_MIXER("LOPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOP_ENA_BIT, 0,
  621. &wm8991_dapm_lopmix_controls[0],
  622. ARRAY_SIZE(wm8991_dapm_lopmix_controls)),
  623. /* OUT3MIX */
  624. SND_SOC_DAPM_MIXER("OUT3MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT3_ENA_BIT, 0,
  625. &wm8991_dapm_out3mix_controls[0],
  626. ARRAY_SIZE(wm8991_dapm_out3mix_controls)),
  627. /* SPKMIX */
  628. SND_SOC_DAPM_MIXER_E("SPKMIX", WM8991_POWER_MANAGEMENT_1, WM8991_SPK_ENA_BIT, 0,
  629. &wm8991_dapm_spkmix_controls[0],
  630. ARRAY_SIZE(wm8991_dapm_spkmix_controls), outmixer_event,
  631. SND_SOC_DAPM_PRE_REG),
  632. /* OUT4MIX */
  633. SND_SOC_DAPM_MIXER("OUT4MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT4_ENA_BIT, 0,
  634. &wm8991_dapm_out4mix_controls[0],
  635. ARRAY_SIZE(wm8991_dapm_out4mix_controls)),
  636. /* ROPMIX */
  637. SND_SOC_DAPM_MIXER("ROPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROP_ENA_BIT, 0,
  638. &wm8991_dapm_ropmix_controls[0],
  639. ARRAY_SIZE(wm8991_dapm_ropmix_controls)),
  640. /* RONMIX */
  641. SND_SOC_DAPM_MIXER("RONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_RON_ENA_BIT, 0,
  642. &wm8991_dapm_ronmix_controls[0],
  643. ARRAY_SIZE(wm8991_dapm_ronmix_controls)),
  644. /* ROMIX */
  645. SND_SOC_DAPM_MIXER_E("ROMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROMIX_ENA_BIT,
  646. 0, &wm8991_dapm_romix_controls[0],
  647. ARRAY_SIZE(wm8991_dapm_romix_controls),
  648. outmixer_event, SND_SOC_DAPM_PRE_REG),
  649. /* LOUT PGA */
  650. SND_SOC_DAPM_PGA("LOUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_LOUT_ENA_BIT, 0,
  651. NULL, 0),
  652. /* ROUT PGA */
  653. SND_SOC_DAPM_PGA("ROUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_ROUT_ENA_BIT, 0,
  654. NULL, 0),
  655. /* LOPGA */
  656. SND_SOC_DAPM_PGA("LOPGA", WM8991_POWER_MANAGEMENT_3, WM8991_LOPGA_ENA_BIT, 0,
  657. NULL, 0),
  658. /* ROPGA */
  659. SND_SOC_DAPM_PGA("ROPGA", WM8991_POWER_MANAGEMENT_3, WM8991_ROPGA_ENA_BIT, 0,
  660. NULL, 0),
  661. /* MICBIAS */
  662. SND_SOC_DAPM_SUPPLY("MICBIAS", WM8991_POWER_MANAGEMENT_1,
  663. WM8991_MICBIAS_ENA_BIT, 0, NULL, 0),
  664. SND_SOC_DAPM_OUTPUT("LON"),
  665. SND_SOC_DAPM_OUTPUT("LOP"),
  666. SND_SOC_DAPM_OUTPUT("OUT3"),
  667. SND_SOC_DAPM_OUTPUT("LOUT"),
  668. SND_SOC_DAPM_OUTPUT("SPKN"),
  669. SND_SOC_DAPM_OUTPUT("SPKP"),
  670. SND_SOC_DAPM_OUTPUT("ROUT"),
  671. SND_SOC_DAPM_OUTPUT("OUT4"),
  672. SND_SOC_DAPM_OUTPUT("ROP"),
  673. SND_SOC_DAPM_OUTPUT("RON"),
  674. SND_SOC_DAPM_OUTPUT("OUT"),
  675. SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
  676. };
  677. static const struct snd_soc_dapm_route audio_map[] = {
  678. /* Make DACs turn on when playing even if not mixed into any outputs */
  679. {"Internal DAC Sink", NULL, "Left DAC"},
  680. {"Internal DAC Sink", NULL, "Right DAC"},
  681. /* Make ADCs turn on when recording even if not mixed from any inputs */
  682. {"Left ADC", NULL, "Internal ADC Source"},
  683. {"Right ADC", NULL, "Internal ADC Source"},
  684. /* Input Side */
  685. /* LIN12 PGA */
  686. {"LIN12 PGA", "LIN1 Switch", "LIN1"},
  687. {"LIN12 PGA", "LIN2 Switch", "LIN2"},
  688. /* LIN34 PGA */
  689. {"LIN34 PGA", "LIN3 Switch", "LIN3"},
  690. {"LIN34 PGA", "LIN4 Switch", "LIN4RXN"},
  691. /* INMIXL */
  692. {"INMIXL", "Record Left Volume", "LOMIX"},
  693. {"INMIXL", "LIN2 Volume", "LIN2"},
  694. {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
  695. {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
  696. /* AINLMUX */
  697. {"AINLMUX", "INMIXL Mix", "INMIXL"},
  698. {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
  699. {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
  700. {"AINLMUX", "RXVOICE Mix", "LIN4RXN"},
  701. {"AINLMUX", "RXVOICE Mix", "RIN4RXP"},
  702. /* ADC */
  703. {"Left ADC", NULL, "AINLMUX"},
  704. /* RIN12 PGA */
  705. {"RIN12 PGA", "RIN1 Switch", "RIN1"},
  706. {"RIN12 PGA", "RIN2 Switch", "RIN2"},
  707. /* RIN34 PGA */
  708. {"RIN34 PGA", "RIN3 Switch", "RIN3"},
  709. {"RIN34 PGA", "RIN4 Switch", "RIN4RXP"},
  710. /* INMIXL */
  711. {"INMIXR", "Record Right Volume", "ROMIX"},
  712. {"INMIXR", "RIN2 Volume", "RIN2"},
  713. {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
  714. {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
  715. /* AINRMUX */
  716. {"AINRMUX", "INMIXR Mix", "INMIXR"},
  717. {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
  718. {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
  719. {"AINRMUX", "RXVOICE Mix", "LIN4RXN"},
  720. {"AINRMUX", "RXVOICE Mix", "RIN4RXP"},
  721. /* ADC */
  722. {"Right ADC", NULL, "AINRMUX"},
  723. /* LOMIX */
  724. {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
  725. {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
  726. {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
  727. {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
  728. {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
  729. {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
  730. {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
  731. /* ROMIX */
  732. {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
  733. {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
  734. {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
  735. {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
  736. {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
  737. {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
  738. {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
  739. /* SPKMIX */
  740. {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
  741. {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
  742. {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
  743. {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
  744. {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
  745. {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
  746. {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
  747. {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
  748. /* LONMIX */
  749. {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
  750. {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
  751. {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
  752. /* LOPMIX */
  753. {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
  754. {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
  755. {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
  756. /* OUT3MIX */
  757. {"OUT3MIX", "OUT3MIX LIN4RXN Bypass Switch", "LIN4RXN"},
  758. {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
  759. /* OUT4MIX */
  760. {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
  761. {"OUT4MIX", "OUT4MIX RIN4RXP Bypass Switch", "RIN4RXP"},
  762. /* RONMIX */
  763. {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
  764. {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
  765. {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
  766. /* ROPMIX */
  767. {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
  768. {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
  769. {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
  770. /* Out Mixer PGAs */
  771. {"LOPGA", NULL, "LOMIX"},
  772. {"ROPGA", NULL, "ROMIX"},
  773. {"LOUT PGA", NULL, "LOMIX"},
  774. {"ROUT PGA", NULL, "ROMIX"},
  775. /* Output Pins */
  776. {"LON", NULL, "LONMIX"},
  777. {"LOP", NULL, "LOPMIX"},
  778. {"OUT", NULL, "OUT3MIX"},
  779. {"LOUT", NULL, "LOUT PGA"},
  780. {"SPKN", NULL, "SPKMIX"},
  781. {"ROUT", NULL, "ROUT PGA"},
  782. {"OUT4", NULL, "OUT4MIX"},
  783. {"ROP", NULL, "ROPMIX"},
  784. {"RON", NULL, "RONMIX"},
  785. };
  786. /* PLL divisors */
  787. struct _pll_div {
  788. u32 div2;
  789. u32 n;
  790. u32 k;
  791. };
  792. /* The size in bits of the pll divide multiplied by 10
  793. * to allow rounding later */
  794. #define FIXED_PLL_SIZE ((1 << 16) * 10)
  795. static void pll_factors(struct _pll_div *pll_div, unsigned int target,
  796. unsigned int source)
  797. {
  798. u64 Kpart;
  799. unsigned int K, Ndiv, Nmod;
  800. Ndiv = target / source;
  801. if (Ndiv < 6) {
  802. source >>= 1;
  803. pll_div->div2 = 1;
  804. Ndiv = target / source;
  805. } else
  806. pll_div->div2 = 0;
  807. if ((Ndiv < 6) || (Ndiv > 12))
  808. printk(KERN_WARNING
  809. "WM8991 N value outwith recommended range! N = %d\n", Ndiv);
  810. pll_div->n = Ndiv;
  811. Nmod = target % source;
  812. Kpart = FIXED_PLL_SIZE * (long long)Nmod;
  813. do_div(Kpart, source);
  814. K = Kpart & 0xFFFFFFFF;
  815. /* Check if we need to round */
  816. if ((K % 10) >= 5)
  817. K += 5;
  818. /* Move down to proper range now rounding is done */
  819. K /= 10;
  820. pll_div->k = K;
  821. }
  822. static int wm8991_set_dai_pll(struct snd_soc_dai *codec_dai,
  823. int pll_id, int src, unsigned int freq_in, unsigned int freq_out)
  824. {
  825. u16 reg;
  826. struct snd_soc_codec *codec = codec_dai->codec;
  827. struct _pll_div pll_div;
  828. if (freq_in && freq_out) {
  829. pll_factors(&pll_div, freq_out * 4, freq_in);
  830. /* Turn on PLL */
  831. reg = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_2);
  832. reg |= WM8991_PLL_ENA;
  833. snd_soc_write(codec, WM8991_POWER_MANAGEMENT_2, reg);
  834. /* sysclk comes from PLL */
  835. reg = snd_soc_read(codec, WM8991_CLOCKING_2);
  836. snd_soc_write(codec, WM8991_CLOCKING_2, reg | WM8991_SYSCLK_SRC);
  837. /* set up N , fractional mode and pre-divisor if necessary */
  838. snd_soc_write(codec, WM8991_PLL1, pll_div.n | WM8991_SDM |
  839. (pll_div.div2 ? WM8991_PRESCALE : 0));
  840. snd_soc_write(codec, WM8991_PLL2, (u8)(pll_div.k>>8));
  841. snd_soc_write(codec, WM8991_PLL3, (u8)(pll_div.k & 0xFF));
  842. } else {
  843. /* Turn on PLL */
  844. reg = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_2);
  845. reg &= ~WM8991_PLL_ENA;
  846. snd_soc_write(codec, WM8991_POWER_MANAGEMENT_2, reg);
  847. }
  848. return 0;
  849. }
  850. /*
  851. * Set's ADC and Voice DAC format.
  852. */
  853. static int wm8991_set_dai_fmt(struct snd_soc_dai *codec_dai,
  854. unsigned int fmt)
  855. {
  856. struct snd_soc_codec *codec = codec_dai->codec;
  857. u16 audio1, audio3;
  858. audio1 = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_1);
  859. audio3 = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_3);
  860. /* set master/slave audio interface */
  861. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  862. case SND_SOC_DAIFMT_CBS_CFS:
  863. audio3 &= ~WM8991_AIF_MSTR1;
  864. break;
  865. case SND_SOC_DAIFMT_CBM_CFM:
  866. audio3 |= WM8991_AIF_MSTR1;
  867. break;
  868. default:
  869. return -EINVAL;
  870. }
  871. audio1 &= ~WM8991_AIF_FMT_MASK;
  872. /* interface format */
  873. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  874. case SND_SOC_DAIFMT_I2S:
  875. audio1 |= WM8991_AIF_TMF_I2S;
  876. audio1 &= ~WM8991_AIF_LRCLK_INV;
  877. break;
  878. case SND_SOC_DAIFMT_RIGHT_J:
  879. audio1 |= WM8991_AIF_TMF_RIGHTJ;
  880. audio1 &= ~WM8991_AIF_LRCLK_INV;
  881. break;
  882. case SND_SOC_DAIFMT_LEFT_J:
  883. audio1 |= WM8991_AIF_TMF_LEFTJ;
  884. audio1 &= ~WM8991_AIF_LRCLK_INV;
  885. break;
  886. case SND_SOC_DAIFMT_DSP_A:
  887. audio1 |= WM8991_AIF_TMF_DSP;
  888. audio1 &= ~WM8991_AIF_LRCLK_INV;
  889. break;
  890. case SND_SOC_DAIFMT_DSP_B:
  891. audio1 |= WM8991_AIF_TMF_DSP | WM8991_AIF_LRCLK_INV;
  892. break;
  893. default:
  894. return -EINVAL;
  895. }
  896. snd_soc_write(codec, WM8991_AUDIO_INTERFACE_1, audio1);
  897. snd_soc_write(codec, WM8991_AUDIO_INTERFACE_3, audio3);
  898. return 0;
  899. }
  900. static int wm8991_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
  901. int div_id, int div)
  902. {
  903. struct snd_soc_codec *codec = codec_dai->codec;
  904. u16 reg;
  905. switch (div_id) {
  906. case WM8991_MCLK_DIV:
  907. reg = snd_soc_read(codec, WM8991_CLOCKING_2) &
  908. ~WM8991_MCLK_DIV_MASK;
  909. snd_soc_write(codec, WM8991_CLOCKING_2, reg | div);
  910. break;
  911. case WM8991_DACCLK_DIV:
  912. reg = snd_soc_read(codec, WM8991_CLOCKING_2) &
  913. ~WM8991_DAC_CLKDIV_MASK;
  914. snd_soc_write(codec, WM8991_CLOCKING_2, reg | div);
  915. break;
  916. case WM8991_ADCCLK_DIV:
  917. reg = snd_soc_read(codec, WM8991_CLOCKING_2) &
  918. ~WM8991_ADC_CLKDIV_MASK;
  919. snd_soc_write(codec, WM8991_CLOCKING_2, reg | div);
  920. break;
  921. case WM8991_BCLK_DIV:
  922. reg = snd_soc_read(codec, WM8991_CLOCKING_1) &
  923. ~WM8991_BCLK_DIV_MASK;
  924. snd_soc_write(codec, WM8991_CLOCKING_1, reg | div);
  925. break;
  926. default:
  927. return -EINVAL;
  928. }
  929. return 0;
  930. }
  931. /*
  932. * Set PCM DAI bit size and sample rate.
  933. */
  934. static int wm8991_hw_params(struct snd_pcm_substream *substream,
  935. struct snd_pcm_hw_params *params,
  936. struct snd_soc_dai *dai)
  937. {
  938. struct snd_soc_codec *codec = dai->codec;
  939. u16 audio1 = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_1);
  940. audio1 &= ~WM8991_AIF_WL_MASK;
  941. /* bit size */
  942. switch (params_format(params)) {
  943. case SNDRV_PCM_FORMAT_S16_LE:
  944. break;
  945. case SNDRV_PCM_FORMAT_S20_3LE:
  946. audio1 |= WM8991_AIF_WL_20BITS;
  947. break;
  948. case SNDRV_PCM_FORMAT_S24_LE:
  949. audio1 |= WM8991_AIF_WL_24BITS;
  950. break;
  951. case SNDRV_PCM_FORMAT_S32_LE:
  952. audio1 |= WM8991_AIF_WL_32BITS;
  953. break;
  954. }
  955. snd_soc_write(codec, WM8991_AUDIO_INTERFACE_1, audio1);
  956. return 0;
  957. }
  958. static int wm8991_mute(struct snd_soc_dai *dai, int mute)
  959. {
  960. struct snd_soc_codec *codec = dai->codec;
  961. u16 val;
  962. val = snd_soc_read(codec, WM8991_DAC_CTRL) & ~WM8991_DAC_MUTE;
  963. if (mute)
  964. snd_soc_write(codec, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE);
  965. else
  966. snd_soc_write(codec, WM8991_DAC_CTRL, val);
  967. return 0;
  968. }
  969. static int wm8991_set_bias_level(struct snd_soc_codec *codec,
  970. enum snd_soc_bias_level level)
  971. {
  972. u16 val;
  973. switch (level) {
  974. case SND_SOC_BIAS_ON:
  975. break;
  976. case SND_SOC_BIAS_PREPARE:
  977. /* VMID=2*50k */
  978. val = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_1) &
  979. ~WM8991_VMID_MODE_MASK;
  980. snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, val | 0x2);
  981. break;
  982. case SND_SOC_BIAS_STANDBY:
  983. if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
  984. snd_soc_cache_sync(codec);
  985. /* Enable all output discharge bits */
  986. snd_soc_write(codec, WM8991_ANTIPOP1, WM8991_DIS_LLINE |
  987. WM8991_DIS_RLINE | WM8991_DIS_OUT3 |
  988. WM8991_DIS_OUT4 | WM8991_DIS_LOUT |
  989. WM8991_DIS_ROUT);
  990. /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
  991. snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST |
  992. WM8991_BUFDCOPEN | WM8991_POBCTRL |
  993. WM8991_VMIDTOG);
  994. /* Delay to allow output caps to discharge */
  995. msleep(300);
  996. /* Disable VMIDTOG */
  997. snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST |
  998. WM8991_BUFDCOPEN | WM8991_POBCTRL);
  999. /* disable all output discharge bits */
  1000. snd_soc_write(codec, WM8991_ANTIPOP1, 0);
  1001. /* Enable outputs */
  1002. snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1b00);
  1003. msleep(50);
  1004. /* Enable VMID at 2x50k */
  1005. snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f02);
  1006. msleep(100);
  1007. /* Enable VREF */
  1008. snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f03);
  1009. msleep(600);
  1010. /* Enable BUFIOEN */
  1011. snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST |
  1012. WM8991_BUFDCOPEN | WM8991_POBCTRL |
  1013. WM8991_BUFIOEN);
  1014. /* Disable outputs */
  1015. snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x3);
  1016. /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
  1017. snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_BUFIOEN);
  1018. }
  1019. /* VMID=2*250k */
  1020. val = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_1) &
  1021. ~WM8991_VMID_MODE_MASK;
  1022. snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, val | 0x4);
  1023. break;
  1024. case SND_SOC_BIAS_OFF:
  1025. /* Enable POBCTRL and SOFT_ST */
  1026. snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST |
  1027. WM8991_POBCTRL | WM8991_BUFIOEN);
  1028. /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
  1029. snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST |
  1030. WM8991_BUFDCOPEN | WM8991_POBCTRL |
  1031. WM8991_BUFIOEN);
  1032. /* mute DAC */
  1033. val = snd_soc_read(codec, WM8991_DAC_CTRL);
  1034. snd_soc_write(codec, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE);
  1035. /* Enable any disabled outputs */
  1036. snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f03);
  1037. /* Disable VMID */
  1038. snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f01);
  1039. msleep(300);
  1040. /* Enable all output discharge bits */
  1041. snd_soc_write(codec, WM8991_ANTIPOP1, WM8991_DIS_LLINE |
  1042. WM8991_DIS_RLINE | WM8991_DIS_OUT3 |
  1043. WM8991_DIS_OUT4 | WM8991_DIS_LOUT |
  1044. WM8991_DIS_ROUT);
  1045. /* Disable VREF */
  1046. snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x0);
  1047. /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
  1048. snd_soc_write(codec, WM8991_ANTIPOP2, 0x0);
  1049. codec->cache_sync = 1;
  1050. break;
  1051. }
  1052. codec->dapm.bias_level = level;
  1053. return 0;
  1054. }
  1055. static int wm8991_suspend(struct snd_soc_codec *codec)
  1056. {
  1057. wm8991_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1058. return 0;
  1059. }
  1060. static int wm8991_resume(struct snd_soc_codec *codec)
  1061. {
  1062. wm8991_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1063. return 0;
  1064. }
  1065. /* power down chip */
  1066. static int wm8991_remove(struct snd_soc_codec *codec)
  1067. {
  1068. wm8991_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1069. return 0;
  1070. }
  1071. static int wm8991_probe(struct snd_soc_codec *codec)
  1072. {
  1073. struct wm8991_priv *wm8991;
  1074. int ret;
  1075. wm8991 = snd_soc_codec_get_drvdata(codec);
  1076. ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm8991->control_type);
  1077. if (ret < 0) {
  1078. dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
  1079. return ret;
  1080. }
  1081. ret = wm8991_reset(codec);
  1082. if (ret < 0) {
  1083. dev_err(codec->dev, "Failed to issue reset\n");
  1084. return ret;
  1085. }
  1086. wm8991_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1087. snd_soc_update_bits(codec, WM8991_AUDIO_INTERFACE_4,
  1088. WM8991_ALRCGPIO1, WM8991_ALRCGPIO1);
  1089. snd_soc_update_bits(codec, WM8991_GPIO1_GPIO2,
  1090. WM8991_GPIO1_SEL_MASK, 1);
  1091. snd_soc_update_bits(codec, WM8991_POWER_MANAGEMENT_1,
  1092. WM8991_VREF_ENA | WM8991_VMID_MODE_MASK,
  1093. WM8991_VREF_ENA | WM8991_VMID_MODE_MASK);
  1094. snd_soc_update_bits(codec, WM8991_POWER_MANAGEMENT_2,
  1095. WM8991_OPCLK_ENA, WM8991_OPCLK_ENA);
  1096. snd_soc_write(codec, WM8991_DAC_CTRL, 0);
  1097. snd_soc_write(codec, WM8991_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
  1098. snd_soc_write(codec, WM8991_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
  1099. snd_soc_add_codec_controls(codec, wm8991_snd_controls,
  1100. ARRAY_SIZE(wm8991_snd_controls));
  1101. snd_soc_dapm_new_controls(&codec->dapm, wm8991_dapm_widgets,
  1102. ARRAY_SIZE(wm8991_dapm_widgets));
  1103. snd_soc_dapm_add_routes(&codec->dapm, audio_map,
  1104. ARRAY_SIZE(audio_map));
  1105. return 0;
  1106. }
  1107. #define WM8991_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  1108. SNDRV_PCM_FMTBIT_S24_LE)
  1109. static const struct snd_soc_dai_ops wm8991_ops = {
  1110. .hw_params = wm8991_hw_params,
  1111. .digital_mute = wm8991_mute,
  1112. .set_fmt = wm8991_set_dai_fmt,
  1113. .set_clkdiv = wm8991_set_dai_clkdiv,
  1114. .set_pll = wm8991_set_dai_pll
  1115. };
  1116. /*
  1117. * The WM8991 supports 2 different and mutually exclusive DAI
  1118. * configurations.
  1119. *
  1120. * 1. ADC/DAC on Primary Interface
  1121. * 2. ADC on Primary Interface/DAC on secondary
  1122. */
  1123. static struct snd_soc_dai_driver wm8991_dai = {
  1124. /* ADC/DAC on primary */
  1125. .name = "wm8991",
  1126. .id = 1,
  1127. .playback = {
  1128. .stream_name = "Playback",
  1129. .channels_min = 1,
  1130. .channels_max = 2,
  1131. .rates = SNDRV_PCM_RATE_8000_96000,
  1132. .formats = WM8991_FORMATS
  1133. },
  1134. .capture = {
  1135. .stream_name = "Capture",
  1136. .channels_min = 1,
  1137. .channels_max = 2,
  1138. .rates = SNDRV_PCM_RATE_8000_96000,
  1139. .formats = WM8991_FORMATS
  1140. },
  1141. .ops = &wm8991_ops
  1142. };
  1143. static struct snd_soc_codec_driver soc_codec_dev_wm8991 = {
  1144. .probe = wm8991_probe,
  1145. .remove = wm8991_remove,
  1146. .suspend = wm8991_suspend,
  1147. .resume = wm8991_resume,
  1148. .set_bias_level = wm8991_set_bias_level,
  1149. .reg_cache_size = WM8991_MAX_REGISTER + 1,
  1150. .reg_word_size = sizeof(u16),
  1151. .reg_cache_default = wm8991_reg_defs
  1152. };
  1153. static __devinit int wm8991_i2c_probe(struct i2c_client *i2c,
  1154. const struct i2c_device_id *id)
  1155. {
  1156. struct wm8991_priv *wm8991;
  1157. int ret;
  1158. wm8991 = kzalloc(sizeof *wm8991, GFP_KERNEL);
  1159. if (!wm8991)
  1160. return -ENOMEM;
  1161. wm8991->control_type = SND_SOC_I2C;
  1162. i2c_set_clientdata(i2c, wm8991);
  1163. ret = snd_soc_register_codec(&i2c->dev,
  1164. &soc_codec_dev_wm8991, &wm8991_dai, 1);
  1165. if (ret < 0)
  1166. kfree(wm8991);
  1167. return ret;
  1168. }
  1169. static __devexit int wm8991_i2c_remove(struct i2c_client *client)
  1170. {
  1171. snd_soc_unregister_codec(&client->dev);
  1172. kfree(i2c_get_clientdata(client));
  1173. return 0;
  1174. }
  1175. static const struct i2c_device_id wm8991_i2c_id[] = {
  1176. { "wm8991", 0 },
  1177. { }
  1178. };
  1179. MODULE_DEVICE_TABLE(i2c, wm8991_i2c_id);
  1180. static struct i2c_driver wm8991_i2c_driver = {
  1181. .driver = {
  1182. .name = "wm8991",
  1183. .owner = THIS_MODULE,
  1184. },
  1185. .probe = wm8991_i2c_probe,
  1186. .remove = __devexit_p(wm8991_i2c_remove),
  1187. .id_table = wm8991_i2c_id,
  1188. };
  1189. static int __init wm8991_modinit(void)
  1190. {
  1191. int ret;
  1192. ret = i2c_add_driver(&wm8991_i2c_driver);
  1193. if (ret != 0) {
  1194. printk(KERN_ERR "Failed to register WM8991 I2C driver: %d\n",
  1195. ret);
  1196. }
  1197. return 0;
  1198. }
  1199. module_init(wm8991_modinit);
  1200. static void __exit wm8991_exit(void)
  1201. {
  1202. i2c_del_driver(&wm8991_i2c_driver);
  1203. }
  1204. module_exit(wm8991_exit);
  1205. MODULE_DESCRIPTION("ASoC WM8991 driver");
  1206. MODULE_AUTHOR("Graeme Gregory");
  1207. MODULE_LICENSE("GPL");